Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4423082 |
1 |
|
|
T22 |
128 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2231366 |
1 |
|
|
T22 |
129 |
|
T1 |
650 |
|
T12 |
46 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5643524 |
1 |
|
|
T22 |
207 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
1010924 |
1 |
|
|
T22 |
50 |
|
T1 |
128 |
|
T12 |
7 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4417777 |
1 |
|
|
T22 |
179 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2236671 |
1 |
|
|
T22 |
78 |
|
T1 |
457 |
|
T12 |
25 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
609116 |
1 |
|
|
T22 |
13 |
|
T1 |
177 |
|
T12 |
16 |
| auto[1] |
auto[0] |
auto[1] |
504127 |
1 |
|
|
T22 |
33 |
|
T1 |
60 |
|
T12 |
2 |
| auto[1] |
auto[1] |
auto[0] |
616631 |
1 |
|
|
T22 |
15 |
|
T1 |
152 |
|
T12 |
2 |
| auto[1] |
auto[1] |
auto[1] |
506797 |
1 |
|
|
T22 |
17 |
|
T1 |
68 |
|
T12 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |