Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4420187 |
1 |
|
|
T22 |
89 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2234261 |
1 |
|
|
T22 |
168 |
|
T1 |
824 |
|
T12 |
64 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5643941 |
1 |
|
|
T22 |
201 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
1010507 |
1 |
|
|
T22 |
56 |
|
T1 |
189 |
|
T12 |
12 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4417153 |
1 |
|
|
T22 |
164 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2237295 |
1 |
|
|
T22 |
93 |
|
T1 |
784 |
|
T12 |
28 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
610652 |
1 |
|
|
T22 |
5 |
|
T1 |
324 |
|
T12 |
5 |
| auto[1] |
auto[0] |
auto[1] |
501530 |
1 |
|
|
T22 |
14 |
|
T1 |
102 |
|
T12 |
4 |
| auto[1] |
auto[1] |
auto[0] |
616136 |
1 |
|
|
T22 |
32 |
|
T1 |
271 |
|
T12 |
11 |
| auto[1] |
auto[1] |
auto[1] |
508977 |
1 |
|
|
T22 |
42 |
|
T1 |
87 |
|
T12 |
8 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |