Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4410292 |
1 |
|
|
T22 |
104 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2244156 |
1 |
|
|
T22 |
153 |
|
T1 |
754 |
|
T12 |
41 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6373087 |
1 |
|
|
T22 |
249 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
281361 |
1 |
|
|
T22 |
8 |
|
T1 |
35 |
|
T12 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4427399 |
1 |
|
|
T22 |
119 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2227049 |
1 |
|
|
T22 |
138 |
|
T1 |
833 |
|
T12 |
47 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
969402 |
1 |
|
|
T22 |
61 |
|
T1 |
487 |
|
T12 |
36 |
| auto[1] |
auto[0] |
auto[1] |
139586 |
1 |
|
|
T22 |
2 |
|
T1 |
19 |
|
T12 |
1 |
| auto[1] |
auto[1] |
auto[0] |
976286 |
1 |
|
|
T22 |
69 |
|
T1 |
311 |
|
T12 |
10 |
| auto[1] |
auto[1] |
auto[1] |
141775 |
1 |
|
|
T22 |
6 |
|
T1 |
16 |
|
T13 |
13 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |