Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4426099 |
1 |
|
|
T22 |
133 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2228349 |
1 |
|
|
T22 |
124 |
|
T1 |
678 |
|
T12 |
31 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5645518 |
1 |
|
|
T22 |
201 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
1008930 |
1 |
|
|
T22 |
56 |
|
T1 |
196 |
|
T12 |
18 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4418979 |
1 |
|
|
T22 |
156 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2235469 |
1 |
|
|
T22 |
101 |
|
T1 |
682 |
|
T12 |
29 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
613506 |
1 |
|
|
T22 |
29 |
|
T1 |
253 |
|
T12 |
10 |
| auto[1] |
auto[0] |
auto[1] |
503210 |
1 |
|
|
T22 |
19 |
|
T1 |
117 |
|
T12 |
15 |
| auto[1] |
auto[1] |
auto[0] |
613033 |
1 |
|
|
T22 |
16 |
|
T1 |
233 |
|
T12 |
1 |
| auto[1] |
auto[1] |
auto[1] |
505720 |
1 |
|
|
T22 |
37 |
|
T1 |
79 |
|
T12 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |