Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4430896 |
1 |
|
|
T22 |
94 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2223552 |
1 |
|
|
T22 |
163 |
|
T1 |
576 |
|
T12 |
37 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5648360 |
1 |
|
|
T22 |
181 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
1006088 |
1 |
|
|
T22 |
76 |
|
T1 |
251 |
|
T12 |
17 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4424806 |
1 |
|
|
T22 |
132 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2229642 |
1 |
|
|
T22 |
125 |
|
T1 |
819 |
|
T12 |
27 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
610213 |
1 |
|
|
T22 |
27 |
|
T1 |
394 |
|
T12 |
7 |
| auto[1] |
auto[0] |
auto[1] |
502921 |
1 |
|
|
T22 |
28 |
|
T1 |
173 |
|
T12 |
10 |
| auto[1] |
auto[1] |
auto[0] |
613341 |
1 |
|
|
T22 |
22 |
|
T1 |
174 |
|
T12 |
3 |
| auto[1] |
auto[1] |
auto[1] |
503167 |
1 |
|
|
T22 |
48 |
|
T1 |
78 |
|
T12 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |