Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4426928 |
1 |
|
|
T22 |
155 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2227520 |
1 |
|
|
T22 |
102 |
|
T1 |
845 |
|
T12 |
40 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5652923 |
1 |
|
|
T22 |
194 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
1001525 |
1 |
|
|
T22 |
63 |
|
T1 |
217 |
|
T12 |
9 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4441339 |
1 |
|
|
T22 |
169 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2213109 |
1 |
|
|
T22 |
88 |
|
T1 |
763 |
|
T12 |
22 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
611762 |
1 |
|
|
T22 |
11 |
|
T1 |
232 |
|
T12 |
7 |
| auto[1] |
auto[0] |
auto[1] |
503119 |
1 |
|
|
T22 |
40 |
|
T1 |
80 |
|
T12 |
7 |
| auto[1] |
auto[1] |
auto[0] |
599822 |
1 |
|
|
T22 |
14 |
|
T1 |
314 |
|
T12 |
6 |
| auto[1] |
auto[1] |
auto[1] |
498406 |
1 |
|
|
T22 |
23 |
|
T1 |
137 |
|
T12 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |