Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4420537 |
1 |
|
|
T22 |
93 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2233911 |
1 |
|
|
T22 |
164 |
|
T1 |
839 |
|
T12 |
50 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6373897 |
1 |
|
|
T22 |
251 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
280551 |
1 |
|
|
T22 |
6 |
|
T1 |
39 |
|
T13 |
16 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4426760 |
1 |
|
|
T22 |
125 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2227688 |
1 |
|
|
T22 |
132 |
|
T1 |
972 |
|
T12 |
52 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
973757 |
1 |
|
|
T22 |
44 |
|
T1 |
480 |
|
T12 |
39 |
| auto[1] |
auto[0] |
auto[1] |
140291 |
1 |
|
|
T1 |
15 |
|
T13 |
7 |
|
T16 |
2 |
| auto[1] |
auto[1] |
auto[0] |
973380 |
1 |
|
|
T22 |
82 |
|
T1 |
453 |
|
T12 |
13 |
| auto[1] |
auto[1] |
auto[1] |
140260 |
1 |
|
|
T22 |
6 |
|
T1 |
24 |
|
T13 |
9 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |