Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4413865 |
1 |
|
|
T22 |
166 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2240583 |
1 |
|
|
T22 |
91 |
|
T1 |
983 |
|
T12 |
66 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6375997 |
1 |
|
|
T22 |
250 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
278451 |
1 |
|
|
T22 |
7 |
|
T1 |
32 |
|
T12 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4436168 |
1 |
|
|
T22 |
128 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2218280 |
1 |
|
|
T22 |
129 |
|
T1 |
802 |
|
T12 |
52 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
970562 |
1 |
|
|
T22 |
89 |
|
T1 |
216 |
|
T12 |
21 |
| auto[1] |
auto[0] |
auto[1] |
139341 |
1 |
|
|
T22 |
6 |
|
T1 |
11 |
|
T12 |
1 |
| auto[1] |
auto[1] |
auto[0] |
969267 |
1 |
|
|
T22 |
33 |
|
T1 |
554 |
|
T12 |
28 |
| auto[1] |
auto[1] |
auto[1] |
139110 |
1 |
|
|
T22 |
1 |
|
T1 |
21 |
|
T12 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |