Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4425812 |
1 |
|
|
T22 |
98 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2228636 |
1 |
|
|
T22 |
159 |
|
T1 |
835 |
|
T12 |
43 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6375038 |
1 |
|
|
T22 |
246 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
279410 |
1 |
|
|
T22 |
11 |
|
T1 |
29 |
|
T13 |
15 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4432873 |
1 |
|
|
T22 |
82 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2221575 |
1 |
|
|
T22 |
175 |
|
T1 |
799 |
|
T12 |
60 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
973284 |
1 |
|
|
T22 |
82 |
|
T1 |
385 |
|
T12 |
35 |
| auto[1] |
auto[0] |
auto[1] |
139862 |
1 |
|
|
T22 |
2 |
|
T1 |
15 |
|
T13 |
10 |
| auto[1] |
auto[1] |
auto[0] |
968881 |
1 |
|
|
T22 |
82 |
|
T1 |
385 |
|
T12 |
25 |
| auto[1] |
auto[1] |
auto[1] |
139548 |
1 |
|
|
T22 |
9 |
|
T1 |
14 |
|
T13 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |