Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4430055 |
1 |
|
|
T22 |
103 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2224393 |
1 |
|
|
T22 |
154 |
|
T1 |
608 |
|
T12 |
72 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6374031 |
1 |
|
|
T22 |
252 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
280417 |
1 |
|
|
T22 |
5 |
|
T1 |
33 |
|
T12 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4428241 |
1 |
|
|
T22 |
180 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2226207 |
1 |
|
|
T22 |
77 |
|
T1 |
792 |
|
T12 |
46 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
979192 |
1 |
|
|
T22 |
25 |
|
T1 |
461 |
|
T12 |
18 |
| auto[1] |
auto[0] |
auto[1] |
140409 |
1 |
|
|
T22 |
2 |
|
T1 |
20 |
|
T12 |
1 |
| auto[1] |
auto[1] |
auto[0] |
966598 |
1 |
|
|
T22 |
47 |
|
T1 |
298 |
|
T12 |
26 |
| auto[1] |
auto[1] |
auto[1] |
140008 |
1 |
|
|
T22 |
3 |
|
T1 |
13 |
|
T12 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |