Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4425693 |
1 |
|
|
T22 |
106 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2228755 |
1 |
|
|
T22 |
151 |
|
T1 |
935 |
|
T12 |
43 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6375755 |
1 |
|
|
T22 |
249 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
278693 |
1 |
|
|
T22 |
8 |
|
T1 |
41 |
|
T12 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4437231 |
1 |
|
|
T22 |
143 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2217217 |
1 |
|
|
T22 |
114 |
|
T1 |
875 |
|
T12 |
60 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
979551 |
1 |
|
|
T22 |
40 |
|
T1 |
327 |
|
T12 |
39 |
| auto[1] |
auto[0] |
auto[1] |
140602 |
1 |
|
|
T22 |
3 |
|
T1 |
18 |
|
T12 |
1 |
| auto[1] |
auto[1] |
auto[0] |
958973 |
1 |
|
|
T22 |
66 |
|
T1 |
507 |
|
T12 |
20 |
| auto[1] |
auto[1] |
auto[1] |
138091 |
1 |
|
|
T22 |
5 |
|
T1 |
23 |
|
T13 |
16 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |