Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4442131 |
1 |
|
|
T22 |
146 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2212317 |
1 |
|
|
T22 |
111 |
|
T1 |
664 |
|
T12 |
56 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6372967 |
1 |
|
|
T22 |
251 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
281481 |
1 |
|
|
T22 |
6 |
|
T1 |
27 |
|
T13 |
16 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4421479 |
1 |
|
|
T22 |
129 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2232969 |
1 |
|
|
T22 |
128 |
|
T1 |
755 |
|
T12 |
39 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
983896 |
1 |
|
|
T22 |
86 |
|
T1 |
433 |
|
T12 |
27 |
| auto[1] |
auto[0] |
auto[1] |
142278 |
1 |
|
|
T22 |
5 |
|
T1 |
13 |
|
T13 |
7 |
| auto[1] |
auto[1] |
auto[0] |
967592 |
1 |
|
|
T22 |
36 |
|
T1 |
295 |
|
T12 |
12 |
| auto[1] |
auto[1] |
auto[1] |
139203 |
1 |
|
|
T22 |
1 |
|
T1 |
14 |
|
T13 |
9 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |