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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 934
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T97 /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.224510255 Aug 17 05:27:20 PM PDT 24 Aug 17 05:27:21 PM PDT 24 183958211 ps
T767 /workspace/coverage/cover_reg_top/15.gpio_csr_rw.4220505336 Aug 17 05:27:54 PM PDT 24 Aug 17 05:27:55 PM PDT 24 23501015 ps
T768 /workspace/coverage/cover_reg_top/35.gpio_intr_test.1492540691 Aug 17 05:27:37 PM PDT 24 Aug 17 05:27:37 PM PDT 24 14970369 ps
T39 /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.4144451267 Aug 17 05:27:39 PM PDT 24 Aug 17 05:27:40 PM PDT 24 187367447 ps
T45 /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.2011922869 Aug 17 05:27:31 PM PDT 24 Aug 17 05:27:32 PM PDT 24 47894757 ps
T769 /workspace/coverage/cover_reg_top/6.gpio_csr_rw.3891415903 Aug 17 05:27:19 PM PDT 24 Aug 17 05:27:20 PM PDT 24 13788583 ps
T770 /workspace/coverage/cover_reg_top/1.gpio_csr_rw.2187174830 Aug 17 05:27:17 PM PDT 24 Aug 17 05:27:18 PM PDT 24 114909018 ps
T40 /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.717394234 Aug 17 05:27:37 PM PDT 24 Aug 17 05:27:38 PM PDT 24 48952747 ps
T42 /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.752524167 Aug 17 05:27:22 PM PDT 24 Aug 17 05:27:23 PM PDT 24 489777357 ps
T771 /workspace/coverage/cover_reg_top/13.gpio_intr_test.1772378900 Aug 17 05:27:37 PM PDT 24 Aug 17 05:27:37 PM PDT 24 17795795 ps
T772 /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.2629291237 Aug 17 05:27:26 PM PDT 24 Aug 17 05:27:27 PM PDT 24 58349111 ps
T81 /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.962134773 Aug 17 05:27:16 PM PDT 24 Aug 17 05:27:17 PM PDT 24 22906947 ps
T773 /workspace/coverage/cover_reg_top/9.gpio_intr_test.3510749388 Aug 17 05:27:30 PM PDT 24 Aug 17 05:27:31 PM PDT 24 18506563 ps
T94 /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.780212542 Aug 17 05:27:33 PM PDT 24 Aug 17 05:27:34 PM PDT 24 67640822 ps
T774 /workspace/coverage/cover_reg_top/12.gpio_tl_errors.3916716363 Aug 17 05:27:44 PM PDT 24 Aug 17 05:27:46 PM PDT 24 64183889 ps
T775 /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.3154276454 Aug 17 05:27:31 PM PDT 24 Aug 17 05:27:32 PM PDT 24 18171469 ps
T776 /workspace/coverage/cover_reg_top/36.gpio_intr_test.4231938556 Aug 17 05:27:30 PM PDT 24 Aug 17 05:27:31 PM PDT 24 16834715 ps
T777 /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.1344824414 Aug 17 05:27:17 PM PDT 24 Aug 17 05:27:18 PM PDT 24 34803026 ps
T778 /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.574722060 Aug 17 05:27:23 PM PDT 24 Aug 17 05:27:24 PM PDT 24 137692642 ps
T779 /workspace/coverage/cover_reg_top/11.gpio_tl_errors.1952775620 Aug 17 05:27:36 PM PDT 24 Aug 17 05:27:38 PM PDT 24 60708667 ps
T780 /workspace/coverage/cover_reg_top/7.gpio_csr_rw.3080394528 Aug 17 05:27:24 PM PDT 24 Aug 17 05:27:24 PM PDT 24 55965811 ps
T781 /workspace/coverage/cover_reg_top/40.gpio_intr_test.3744209189 Aug 17 05:27:34 PM PDT 24 Aug 17 05:27:35 PM PDT 24 13206754 ps
T782 /workspace/coverage/cover_reg_top/38.gpio_intr_test.516552338 Aug 17 05:27:42 PM PDT 24 Aug 17 05:27:42 PM PDT 24 21567773 ps
T783 /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.3253987199 Aug 17 05:27:34 PM PDT 24 Aug 17 05:27:35 PM PDT 24 28251287 ps
T46 /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.1408469022 Aug 17 05:27:18 PM PDT 24 Aug 17 05:27:19 PM PDT 24 46918757 ps
T784 /workspace/coverage/cover_reg_top/21.gpio_intr_test.608307076 Aug 17 05:27:26 PM PDT 24 Aug 17 05:27:27 PM PDT 24 16823343 ps
T785 /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.3778512923 Aug 17 05:27:15 PM PDT 24 Aug 17 05:27:16 PM PDT 24 191828332 ps
T82 /workspace/coverage/cover_reg_top/14.gpio_csr_rw.551840140 Aug 17 05:27:26 PM PDT 24 Aug 17 05:27:27 PM PDT 24 21901941 ps
T786 /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.2942003297 Aug 17 05:27:27 PM PDT 24 Aug 17 05:27:28 PM PDT 24 46080951 ps
T787 /workspace/coverage/cover_reg_top/31.gpio_intr_test.13789317 Aug 17 05:27:34 PM PDT 24 Aug 17 05:27:35 PM PDT 24 22963287 ps
T788 /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.2614336059 Aug 17 05:27:27 PM PDT 24 Aug 17 05:27:28 PM PDT 24 154070824 ps
T86 /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.1820177361 Aug 17 05:27:24 PM PDT 24 Aug 17 05:27:28 PM PDT 24 79984326 ps
T789 /workspace/coverage/cover_reg_top/18.gpio_intr_test.3052864146 Aug 17 05:27:36 PM PDT 24 Aug 17 05:27:37 PM PDT 24 13528857 ps
T790 /workspace/coverage/cover_reg_top/18.gpio_tl_errors.3894352622 Aug 17 05:27:28 PM PDT 24 Aug 17 05:27:30 PM PDT 24 52252758 ps
T47 /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.1845928781 Aug 17 05:27:33 PM PDT 24 Aug 17 05:27:34 PM PDT 24 99593822 ps
T791 /workspace/coverage/cover_reg_top/8.gpio_intr_test.959846137 Aug 17 05:27:19 PM PDT 24 Aug 17 05:27:20 PM PDT 24 25133854 ps
T792 /workspace/coverage/cover_reg_top/13.gpio_tl_errors.1184606225 Aug 17 05:27:27 PM PDT 24 Aug 17 05:27:29 PM PDT 24 54683372 ps
T793 /workspace/coverage/cover_reg_top/0.gpio_tl_errors.4267692770 Aug 17 05:27:17 PM PDT 24 Aug 17 05:27:18 PM PDT 24 87885070 ps
T794 /workspace/coverage/cover_reg_top/32.gpio_intr_test.1553709932 Aug 17 05:27:34 PM PDT 24 Aug 17 05:27:35 PM PDT 24 30587955 ps
T795 /workspace/coverage/cover_reg_top/5.gpio_tl_errors.3416889998 Aug 17 05:27:19 PM PDT 24 Aug 17 05:27:22 PM PDT 24 152149015 ps
T796 /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.1948452618 Aug 17 05:27:34 PM PDT 24 Aug 17 05:27:35 PM PDT 24 48480122 ps
T797 /workspace/coverage/cover_reg_top/7.gpio_intr_test.264845254 Aug 17 05:27:20 PM PDT 24 Aug 17 05:27:21 PM PDT 24 29010132 ps
T798 /workspace/coverage/cover_reg_top/18.gpio_csr_rw.252521635 Aug 17 05:27:31 PM PDT 24 Aug 17 05:27:31 PM PDT 24 28923289 ps
T799 /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.1157553271 Aug 17 05:27:27 PM PDT 24 Aug 17 05:27:27 PM PDT 24 36082150 ps
T800 /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.4082058949 Aug 17 05:27:26 PM PDT 24 Aug 17 05:27:27 PM PDT 24 192941396 ps
T801 /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.2042287122 Aug 17 05:27:19 PM PDT 24 Aug 17 05:27:19 PM PDT 24 64071187 ps
T802 /workspace/coverage/cover_reg_top/24.gpio_intr_test.2897340477 Aug 17 05:27:42 PM PDT 24 Aug 17 05:27:43 PM PDT 24 12467552 ps
T803 /workspace/coverage/cover_reg_top/19.gpio_csr_rw.4039962636 Aug 17 05:27:31 PM PDT 24 Aug 17 05:27:32 PM PDT 24 22024672 ps
T804 /workspace/coverage/cover_reg_top/16.gpio_csr_rw.3401642727 Aug 17 05:27:34 PM PDT 24 Aug 17 05:27:36 PM PDT 24 12690380 ps
T43 /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.2675551088 Aug 17 05:27:31 PM PDT 24 Aug 17 05:27:32 PM PDT 24 271561273 ps
T805 /workspace/coverage/cover_reg_top/7.gpio_tl_errors.3717051827 Aug 17 05:27:34 PM PDT 24 Aug 17 05:27:36 PM PDT 24 75138095 ps
T83 /workspace/coverage/cover_reg_top/0.gpio_csr_rw.1622428194 Aug 17 05:27:15 PM PDT 24 Aug 17 05:27:15 PM PDT 24 43877699 ps
T806 /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.578961811 Aug 17 05:27:27 PM PDT 24 Aug 17 05:27:28 PM PDT 24 43169917 ps
T807 /workspace/coverage/cover_reg_top/43.gpio_intr_test.3334449051 Aug 17 05:27:43 PM PDT 24 Aug 17 05:27:44 PM PDT 24 26007431 ps
T808 /workspace/coverage/cover_reg_top/34.gpio_intr_test.4234823402 Aug 17 05:27:36 PM PDT 24 Aug 17 05:27:37 PM PDT 24 48928683 ps
T809 /workspace/coverage/cover_reg_top/14.gpio_intr_test.2261259953 Aug 17 05:27:35 PM PDT 24 Aug 17 05:27:36 PM PDT 24 32174747 ps
T810 /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.1874354960 Aug 17 05:27:29 PM PDT 24 Aug 17 05:27:30 PM PDT 24 55123136 ps
T811 /workspace/coverage/cover_reg_top/30.gpio_intr_test.1624435005 Aug 17 05:27:26 PM PDT 24 Aug 17 05:27:26 PM PDT 24 43668783 ps
T812 /workspace/coverage/cover_reg_top/9.gpio_tl_errors.3087083210 Aug 17 05:27:22 PM PDT 24 Aug 17 05:27:23 PM PDT 24 111448569 ps
T813 /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.1468880316 Aug 17 05:27:52 PM PDT 24 Aug 17 05:27:53 PM PDT 24 375394876 ps
T814 /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.4197045743 Aug 17 05:27:13 PM PDT 24 Aug 17 05:27:14 PM PDT 24 14263617 ps
T815 /workspace/coverage/cover_reg_top/14.gpio_tl_errors.755651616 Aug 17 05:27:27 PM PDT 24 Aug 17 05:27:30 PM PDT 24 132997875 ps
T816 /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.3288757430 Aug 17 05:27:34 PM PDT 24 Aug 17 05:27:36 PM PDT 24 46314189 ps
T817 /workspace/coverage/cover_reg_top/45.gpio_intr_test.3930418997 Aug 17 05:27:55 PM PDT 24 Aug 17 05:27:56 PM PDT 24 20941788 ps
T818 /workspace/coverage/cover_reg_top/33.gpio_intr_test.3140774558 Aug 17 05:27:33 PM PDT 24 Aug 17 05:27:33 PM PDT 24 61118508 ps
T41 /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.4122929923 Aug 17 05:27:28 PM PDT 24 Aug 17 05:27:29 PM PDT 24 47776931 ps
T819 /workspace/coverage/cover_reg_top/3.gpio_tl_errors.33401375 Aug 17 05:27:19 PM PDT 24 Aug 17 05:27:21 PM PDT 24 101383736 ps
T820 /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.2224444812 Aug 17 05:27:31 PM PDT 24 Aug 17 05:27:33 PM PDT 24 640887123 ps
T821 /workspace/coverage/cover_reg_top/13.gpio_csr_rw.615277251 Aug 17 05:27:35 PM PDT 24 Aug 17 05:27:36 PM PDT 24 35714708 ps
T822 /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.3814499174 Aug 17 05:27:37 PM PDT 24 Aug 17 05:27:38 PM PDT 24 40423759 ps
T823 /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.2983412829 Aug 17 05:27:29 PM PDT 24 Aug 17 05:27:31 PM PDT 24 126891112 ps
T824 /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.644244347 Aug 17 05:27:29 PM PDT 24 Aug 17 05:27:31 PM PDT 24 131600433 ps
T825 /workspace/coverage/cover_reg_top/3.gpio_csr_rw.2711934480 Aug 17 05:27:18 PM PDT 24 Aug 17 05:27:19 PM PDT 24 43353410 ps
T84 /workspace/coverage/cover_reg_top/2.gpio_csr_rw.3445471058 Aug 17 05:27:21 PM PDT 24 Aug 17 05:27:22 PM PDT 24 15164422 ps
T826 /workspace/coverage/cover_reg_top/10.gpio_intr_test.1801999035 Aug 17 05:27:24 PM PDT 24 Aug 17 05:27:24 PM PDT 24 43961275 ps
T87 /workspace/coverage/cover_reg_top/9.gpio_csr_rw.319308620 Aug 17 05:27:19 PM PDT 24 Aug 17 05:27:20 PM PDT 24 12572227 ps
T827 /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.4240839139 Aug 17 05:27:42 PM PDT 24 Aug 17 05:27:43 PM PDT 24 75607957 ps
T828 /workspace/coverage/cover_reg_top/4.gpio_tl_errors.3030940567 Aug 17 05:27:24 PM PDT 24 Aug 17 05:27:26 PM PDT 24 497922121 ps
T829 /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.813498024 Aug 17 05:27:30 PM PDT 24 Aug 17 05:27:31 PM PDT 24 64308290 ps
T830 /workspace/coverage/cover_reg_top/15.gpio_intr_test.3129355508 Aug 17 05:27:29 PM PDT 24 Aug 17 05:27:30 PM PDT 24 19054191 ps
T831 /workspace/coverage/cover_reg_top/8.gpio_tl_errors.2122788454 Aug 17 05:27:33 PM PDT 24 Aug 17 05:27:35 PM PDT 24 47455489 ps
T832 /workspace/coverage/cover_reg_top/27.gpio_intr_test.1944807689 Aug 17 05:27:35 PM PDT 24 Aug 17 05:27:36 PM PDT 24 17478948 ps
T833 /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.80141921 Aug 17 05:27:19 PM PDT 24 Aug 17 05:27:20 PM PDT 24 68449679 ps
T834 /workspace/coverage/cover_reg_top/12.gpio_intr_test.162652875 Aug 17 05:27:35 PM PDT 24 Aug 17 05:27:36 PM PDT 24 20226256 ps
T835 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2579982523 Aug 17 05:27:56 PM PDT 24 Aug 17 05:27:56 PM PDT 24 26803641 ps
T836 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2573291808 Aug 17 05:27:48 PM PDT 24 Aug 17 05:27:49 PM PDT 24 56328146 ps
T837 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4002989793 Aug 17 05:27:51 PM PDT 24 Aug 17 05:27:53 PM PDT 24 173094128 ps
T838 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.2289412328 Aug 17 05:27:53 PM PDT 24 Aug 17 05:27:54 PM PDT 24 64064712 ps
T839 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.885874355 Aug 17 05:27:56 PM PDT 24 Aug 17 05:27:57 PM PDT 24 21529168 ps
T840 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.1525568784 Aug 17 05:27:47 PM PDT 24 Aug 17 05:27:48 PM PDT 24 43611967 ps
T841 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.1607495251 Aug 17 05:27:55 PM PDT 24 Aug 17 05:27:56 PM PDT 24 73223805 ps
T842 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1779282894 Aug 17 05:27:54 PM PDT 24 Aug 17 05:27:55 PM PDT 24 28779074 ps
T843 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.3982101298 Aug 17 05:27:58 PM PDT 24 Aug 17 05:27:59 PM PDT 24 69915878 ps
T844 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.1144278530 Aug 17 05:28:05 PM PDT 24 Aug 17 05:28:11 PM PDT 24 31465327 ps
T845 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.694483508 Aug 17 05:27:47 PM PDT 24 Aug 17 05:27:48 PM PDT 24 59088399 ps
T846 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.3510542280 Aug 17 05:27:32 PM PDT 24 Aug 17 05:27:33 PM PDT 24 99918563 ps
T847 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1449992735 Aug 17 05:27:59 PM PDT 24 Aug 17 05:28:00 PM PDT 24 51532678 ps
T848 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.1974129705 Aug 17 05:27:59 PM PDT 24 Aug 17 05:28:00 PM PDT 24 65354812 ps
T849 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.2627872192 Aug 17 05:27:59 PM PDT 24 Aug 17 05:28:01 PM PDT 24 100774524 ps
T850 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1289114079 Aug 17 05:27:39 PM PDT 24 Aug 17 05:27:40 PM PDT 24 91638475 ps
T851 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1207559048 Aug 17 05:28:01 PM PDT 24 Aug 17 05:28:02 PM PDT 24 28047276 ps
T852 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3991019054 Aug 17 05:27:57 PM PDT 24 Aug 17 05:27:58 PM PDT 24 296813307 ps
T853 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.3015616154 Aug 17 05:27:58 PM PDT 24 Aug 17 05:28:00 PM PDT 24 95157146 ps
T854 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1400744131 Aug 17 05:27:58 PM PDT 24 Aug 17 05:28:00 PM PDT 24 67674562 ps
T855 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2487315213 Aug 17 05:27:57 PM PDT 24 Aug 17 05:27:59 PM PDT 24 91460346 ps
T856 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.3097759331 Aug 17 05:27:53 PM PDT 24 Aug 17 05:27:55 PM PDT 24 167924044 ps
T857 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1925312058 Aug 17 05:27:53 PM PDT 24 Aug 17 05:27:54 PM PDT 24 187066628 ps
T858 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.1218867296 Aug 17 05:27:55 PM PDT 24 Aug 17 05:27:57 PM PDT 24 524807347 ps
T859 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2833563451 Aug 17 05:27:55 PM PDT 24 Aug 17 05:27:56 PM PDT 24 52002598 ps
T860 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.457464768 Aug 17 05:28:01 PM PDT 24 Aug 17 05:28:03 PM PDT 24 45845572 ps
T861 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2575904089 Aug 17 05:27:58 PM PDT 24 Aug 17 05:27:59 PM PDT 24 128793656 ps
T862 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.1760876450 Aug 17 05:28:04 PM PDT 24 Aug 17 05:28:05 PM PDT 24 290174810 ps
T863 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.69576614 Aug 17 05:27:59 PM PDT 24 Aug 17 05:28:00 PM PDT 24 158782676 ps
T864 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.3408616488 Aug 17 05:27:38 PM PDT 24 Aug 17 05:27:39 PM PDT 24 40822456 ps
T865 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1830973341 Aug 17 05:27:59 PM PDT 24 Aug 17 05:28:00 PM PDT 24 32769163 ps
T866 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.54119123 Aug 17 05:27:41 PM PDT 24 Aug 17 05:27:42 PM PDT 24 64704426 ps
T867 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2955132632 Aug 17 05:27:52 PM PDT 24 Aug 17 05:27:53 PM PDT 24 59666087 ps
T868 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.61459344 Aug 17 05:27:49 PM PDT 24 Aug 17 05:27:50 PM PDT 24 71846200 ps
T869 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2598134817 Aug 17 05:27:34 PM PDT 24 Aug 17 05:27:35 PM PDT 24 118308682 ps
T870 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.2427678968 Aug 17 05:27:51 PM PDT 24 Aug 17 05:27:52 PM PDT 24 106687145 ps
T871 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.3151851061 Aug 17 05:27:47 PM PDT 24 Aug 17 05:27:48 PM PDT 24 99479282 ps
T872 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.2734830436 Aug 17 05:27:52 PM PDT 24 Aug 17 05:27:53 PM PDT 24 88557742 ps
T873 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.1858747183 Aug 17 05:27:56 PM PDT 24 Aug 17 05:27:58 PM PDT 24 67220707 ps
T874 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.3107272114 Aug 17 05:27:37 PM PDT 24 Aug 17 05:27:38 PM PDT 24 45211362 ps
T875 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.930533976 Aug 17 05:27:58 PM PDT 24 Aug 17 05:27:59 PM PDT 24 143408622 ps
T876 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.2789724963 Aug 17 05:27:48 PM PDT 24 Aug 17 05:27:50 PM PDT 24 81519537 ps
T877 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.929255060 Aug 17 05:27:53 PM PDT 24 Aug 17 05:27:54 PM PDT 24 51934068 ps
T878 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.4281938872 Aug 17 05:27:45 PM PDT 24 Aug 17 05:27:46 PM PDT 24 341108000 ps
T879 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.552794816 Aug 17 05:27:59 PM PDT 24 Aug 17 05:28:01 PM PDT 24 189284287 ps
T880 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.501913493 Aug 17 05:27:56 PM PDT 24 Aug 17 05:27:57 PM PDT 24 172378691 ps
T881 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.1320114821 Aug 17 05:27:50 PM PDT 24 Aug 17 05:27:51 PM PDT 24 248122810 ps
T882 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.302062591 Aug 17 05:27:48 PM PDT 24 Aug 17 05:27:49 PM PDT 24 149332408 ps
T883 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.3019451817 Aug 17 05:27:50 PM PDT 24 Aug 17 05:27:52 PM PDT 24 461417526 ps
T884 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.4101260676 Aug 17 05:27:43 PM PDT 24 Aug 17 05:27:44 PM PDT 24 109155638 ps
T885 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.2112579 Aug 17 05:27:59 PM PDT 24 Aug 17 05:28:00 PM PDT 24 806949935 ps
T886 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1523600631 Aug 17 05:27:51 PM PDT 24 Aug 17 05:27:52 PM PDT 24 93664864 ps
T887 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3276738896 Aug 17 05:27:56 PM PDT 24 Aug 17 05:27:57 PM PDT 24 79956461 ps
T888 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2657561137 Aug 17 05:27:59 PM PDT 24 Aug 17 05:28:01 PM PDT 24 262392393 ps
T889 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2017113107 Aug 17 05:27:51 PM PDT 24 Aug 17 05:27:52 PM PDT 24 34722676 ps
T890 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.3110450973 Aug 17 05:27:58 PM PDT 24 Aug 17 05:27:59 PM PDT 24 92833640 ps
T891 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.2622697858 Aug 17 05:28:00 PM PDT 24 Aug 17 05:28:01 PM PDT 24 51209524 ps
T892 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2471164936 Aug 17 05:28:01 PM PDT 24 Aug 17 05:28:02 PM PDT 24 42685881 ps
T893 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2133955397 Aug 17 05:27:53 PM PDT 24 Aug 17 05:27:54 PM PDT 24 320108045 ps
T894 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.2673879551 Aug 17 05:27:50 PM PDT 24 Aug 17 05:27:51 PM PDT 24 76940756 ps
T895 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.922779505 Aug 17 05:27:53 PM PDT 24 Aug 17 05:27:54 PM PDT 24 18729474 ps
T896 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.40233950 Aug 17 05:27:54 PM PDT 24 Aug 17 05:27:55 PM PDT 24 70933262 ps
T897 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.798255464 Aug 17 05:28:01 PM PDT 24 Aug 17 05:28:02 PM PDT 24 512165800 ps
T898 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.525440901 Aug 17 05:27:59 PM PDT 24 Aug 17 05:27:59 PM PDT 24 69929724 ps
T899 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.1223816150 Aug 17 05:27:33 PM PDT 24 Aug 17 05:27:34 PM PDT 24 99567267 ps
T900 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.22000261 Aug 17 05:27:54 PM PDT 24 Aug 17 05:27:56 PM PDT 24 122318533 ps
T901 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2720181909 Aug 17 05:27:34 PM PDT 24 Aug 17 05:27:36 PM PDT 24 171121881 ps
T902 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.3797378314 Aug 17 05:27:45 PM PDT 24 Aug 17 05:27:46 PM PDT 24 155012152 ps
T903 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3923653523 Aug 17 05:27:57 PM PDT 24 Aug 17 05:27:58 PM PDT 24 64599899 ps
T904 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.1492158781 Aug 17 05:27:55 PM PDT 24 Aug 17 05:27:56 PM PDT 24 55667370 ps
T905 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.2021412300 Aug 17 05:27:53 PM PDT 24 Aug 17 05:27:54 PM PDT 24 31199193 ps
T906 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3409994901 Aug 17 05:28:00 PM PDT 24 Aug 17 05:28:01 PM PDT 24 267690996 ps
T907 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4135378861 Aug 17 05:27:59 PM PDT 24 Aug 17 05:28:00 PM PDT 24 233620073 ps
T908 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1535544 Aug 17 05:27:45 PM PDT 24 Aug 17 05:27:46 PM PDT 24 281500406 ps
T909 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.683020250 Aug 17 05:27:51 PM PDT 24 Aug 17 05:27:53 PM PDT 24 103092581 ps
T910 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2996026958 Aug 17 05:27:48 PM PDT 24 Aug 17 05:27:50 PM PDT 24 52773553 ps
T911 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1262260520 Aug 17 05:28:00 PM PDT 24 Aug 17 05:28:01 PM PDT 24 53039552 ps
T912 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.1840502252 Aug 17 05:27:57 PM PDT 24 Aug 17 05:27:58 PM PDT 24 244041366 ps
T913 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3001574187 Aug 17 05:27:40 PM PDT 24 Aug 17 05:27:41 PM PDT 24 32007247 ps
T914 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.2343845423 Aug 17 05:27:41 PM PDT 24 Aug 17 05:27:42 PM PDT 24 442799462 ps
T915 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.3672112129 Aug 17 05:27:59 PM PDT 24 Aug 17 05:28:00 PM PDT 24 171188364 ps
T916 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.3727455265 Aug 17 05:27:53 PM PDT 24 Aug 17 05:27:55 PM PDT 24 498101935 ps
T917 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3452408217 Aug 17 05:28:00 PM PDT 24 Aug 17 05:28:02 PM PDT 24 695152849 ps
T918 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.3006427025 Aug 17 05:27:45 PM PDT 24 Aug 17 05:27:46 PM PDT 24 58655530 ps
T919 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.328457614 Aug 17 05:27:53 PM PDT 24 Aug 17 05:27:55 PM PDT 24 168061469 ps
T920 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3059981472 Aug 17 05:27:35 PM PDT 24 Aug 17 05:27:36 PM PDT 24 47910820 ps
T921 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.1043796512 Aug 17 05:28:01 PM PDT 24 Aug 17 05:28:03 PM PDT 24 321080937 ps
T922 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.863682971 Aug 17 05:28:02 PM PDT 24 Aug 17 05:28:03 PM PDT 24 92236603 ps
T923 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.789259200 Aug 17 05:27:56 PM PDT 24 Aug 17 05:27:57 PM PDT 24 35339453 ps
T924 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.1771979233 Aug 17 05:28:01 PM PDT 24 Aug 17 05:28:02 PM PDT 24 41672071 ps
T925 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1291871304 Aug 17 05:28:04 PM PDT 24 Aug 17 05:28:05 PM PDT 24 42920491 ps
T926 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.1546897947 Aug 17 05:27:42 PM PDT 24 Aug 17 05:27:43 PM PDT 24 252113447 ps
T927 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3500060316 Aug 17 05:27:59 PM PDT 24 Aug 17 05:28:01 PM PDT 24 61816384 ps
T928 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1748606844 Aug 17 05:27:54 PM PDT 24 Aug 17 05:27:56 PM PDT 24 103903062 ps
T929 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.1354753921 Aug 17 05:27:58 PM PDT 24 Aug 17 05:27:59 PM PDT 24 86169794 ps
T930 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.43120846 Aug 17 05:27:53 PM PDT 24 Aug 17 05:27:54 PM PDT 24 583354011 ps
T931 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.2283079459 Aug 17 05:28:01 PM PDT 24 Aug 17 05:28:02 PM PDT 24 40766626 ps
T932 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.91348437 Aug 17 05:27:41 PM PDT 24 Aug 17 05:27:43 PM PDT 24 60537875 ps
T933 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3029118211 Aug 17 05:27:47 PM PDT 24 Aug 17 05:27:49 PM PDT 24 63765634 ps
T934 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2174596353 Aug 17 05:28:01 PM PDT 24 Aug 17 05:28:03 PM PDT 24 56712801 ps

Test location /workspace/coverage/default/1.gpio_full_random.3442604305
Short name T12
Test name
Test status
Simulation time 136877609 ps
CPU time 0.94 seconds
Started Aug 17 05:32:29 PM PDT 24
Finished Aug 17 05:32:30 PM PDT 24
Peak memory 197984 kb
Host smart-533063d3-9b79-48f5-b7e8-ec1e62c934a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442604305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.3442604305
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.1676283867
Short name T17
Test name
Test status
Simulation time 86314297 ps
CPU time 2.97 seconds
Started Aug 17 05:32:54 PM PDT 24
Finished Aug 17 05:32:57 PM PDT 24
Peak memory 198204 kb
Host smart-9bf12c0a-5a1e-450e-9e44-131d1145c65b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676283867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.1676283867
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_stress_all_with_rand_reset.859865061
Short name T28
Test name
Test status
Simulation time 5693529783 ps
CPU time 190.83 seconds
Started Aug 17 05:35:07 PM PDT 24
Finished Aug 17 05:38:18 PM PDT 24
Peak memory 198560 kb
Host smart-fbb2a2d3-59e2-41e6-8d85-f85359096043
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=859865061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_stress_all_with_rand_reset.859865061
Directory /workspace/36.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.3579296726
Short name T1
Test name
Test status
Simulation time 386387581 ps
CPU time 4.42 seconds
Started Aug 17 05:34:15 PM PDT 24
Finished Aug 17 05:34:20 PM PDT 24
Peak memory 198080 kb
Host smart-5457d03a-bd63-40ed-a2dd-cd72576ffb7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579296726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.3579296726
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.1638262239
Short name T15
Test name
Test status
Simulation time 92429384 ps
CPU time 1.01 seconds
Started Aug 17 05:32:44 PM PDT 24
Finished Aug 17 05:32:45 PM PDT 24
Peak memory 215112 kb
Host smart-bfc3d4e5-0353-47ef-bc01-cac69954ae9a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638262239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.1638262239
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.2915869535
Short name T72
Test name
Test status
Simulation time 30504719 ps
CPU time 0.64 seconds
Started Aug 17 05:27:32 PM PDT 24
Finished Aug 17 05:27:32 PM PDT 24
Peak memory 195336 kb
Host smart-b973c478-e2ad-408a-8dba-95ed76c88cee
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915869535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.2915869535
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.4144451267
Short name T39
Test name
Test status
Simulation time 187367447 ps
CPU time 1.44 seconds
Started Aug 17 05:27:39 PM PDT 24
Finished Aug 17 05:27:40 PM PDT 24
Peak memory 198492 kb
Host smart-221e6e14-f2bd-42aa-aaa9-bab8d053b1f1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144451267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.4144451267
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/17.gpio_alert_test.581203346
Short name T150
Test name
Test status
Simulation time 26261349 ps
CPU time 0.56 seconds
Started Aug 17 05:33:51 PM PDT 24
Finished Aug 17 05:33:51 PM PDT 24
Peak memory 194016 kb
Host smart-4b83f68e-1f43-45a0-bcb0-2d1bf583d5d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581203346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.581203346
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.3153248929
Short name T85
Test name
Test status
Simulation time 278458208 ps
CPU time 3.04 seconds
Started Aug 17 05:27:21 PM PDT 24
Finished Aug 17 05:27:24 PM PDT 24
Peak memory 198380 kb
Host smart-041b81b7-7987-47cb-99a6-dac863d531c5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153248929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.3153248929
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.1933331344
Short name T88
Test name
Test status
Simulation time 22143565 ps
CPU time 0.89 seconds
Started Aug 17 05:27:22 PM PDT 24
Finished Aug 17 05:27:23 PM PDT 24
Peak memory 198128 kb
Host smart-39d2658e-e91e-412b-b9da-6af11487f9b4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933331344 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.1933331344
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.1468880316
Short name T813
Test name
Test status
Simulation time 375394876 ps
CPU time 1.43 seconds
Started Aug 17 05:27:52 PM PDT 24
Finished Aug 17 05:27:53 PM PDT 24
Peak memory 198476 kb
Host smart-eb461298-74de-4708-ba64-3c06f10dc5a2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468880316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.1468880316
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.1408469022
Short name T46
Test name
Test status
Simulation time 46918757 ps
CPU time 0.91 seconds
Started Aug 17 05:27:18 PM PDT 24
Finished Aug 17 05:27:19 PM PDT 24
Peak memory 198244 kb
Host smart-f94ae7b1-4330-44dc-956f-50cc9d80cb31
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408469022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.1408469022
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.1713500591
Short name T69
Test name
Test status
Simulation time 24974881 ps
CPU time 0.73 seconds
Started Aug 17 05:27:19 PM PDT 24
Finished Aug 17 05:27:19 PM PDT 24
Peak memory 196004 kb
Host smart-23e1611d-c5f1-4c6c-aec3-c3257b6c2a92
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713500591 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.1713500591
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.4197045743
Short name T814
Test name
Test status
Simulation time 14263617 ps
CPU time 0.61 seconds
Started Aug 17 05:27:13 PM PDT 24
Finished Aug 17 05:27:14 PM PDT 24
Peak memory 194836 kb
Host smart-2a5f4b49-3c61-4c82-aec5-2a4b2cf29f98
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197045743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.4197045743
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.3778512923
Short name T785
Test name
Test status
Simulation time 191828332 ps
CPU time 0.96 seconds
Started Aug 17 05:27:15 PM PDT 24
Finished Aug 17 05:27:16 PM PDT 24
Peak memory 198400 kb
Host smart-ea483c3b-beef-4b41-83e6-8886b886e864
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778512923 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.3778512923
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.1622428194
Short name T83
Test name
Test status
Simulation time 43877699 ps
CPU time 0.59 seconds
Started Aug 17 05:27:15 PM PDT 24
Finished Aug 17 05:27:15 PM PDT 24
Peak memory 194848 kb
Host smart-3120b0c1-2b7d-4143-b066-61d4da56a8b8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622428194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio
_csr_rw.1622428194
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.4221921625
Short name T744
Test name
Test status
Simulation time 42472450 ps
CPU time 0.58 seconds
Started Aug 17 05:27:15 PM PDT 24
Finished Aug 17 05:27:15 PM PDT 24
Peak memory 194252 kb
Host smart-e726f76d-d892-4b1e-8e90-969657bb8cd8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221921625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.4221921625
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.2042287122
Short name T801
Test name
Test status
Simulation time 64071187 ps
CPU time 0.63 seconds
Started Aug 17 05:27:19 PM PDT 24
Finished Aug 17 05:27:19 PM PDT 24
Peak memory 195448 kb
Host smart-a0522461-24a6-4dd1-a297-1a208fd45af1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042287122 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.2042287122
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.4267692770
Short name T793
Test name
Test status
Simulation time 87885070 ps
CPU time 1.15 seconds
Started Aug 17 05:27:17 PM PDT 24
Finished Aug 17 05:27:18 PM PDT 24
Peak memory 198492 kb
Host smart-3c6971af-45bf-49e2-8fcf-9999c854cac3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267692770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.4267692770
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.1500315501
Short name T32
Test name
Test status
Simulation time 143339455 ps
CPU time 0.88 seconds
Started Aug 17 05:27:17 PM PDT 24
Finished Aug 17 05:27:18 PM PDT 24
Peak memory 197700 kb
Host smart-1405932e-d431-4762-9163-19a3000ba5e4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500315501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.1500315501
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.1004215458
Short name T75
Test name
Test status
Simulation time 20292190 ps
CPU time 0.66 seconds
Started Aug 17 05:27:33 PM PDT 24
Finished Aug 17 05:27:35 PM PDT 24
Peak memory 194548 kb
Host smart-6e041e83-e017-463f-8652-5b9e5bc2bb56
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004215458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.1004215458
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.2915624532
Short name T80
Test name
Test status
Simulation time 2165219828 ps
CPU time 2.45 seconds
Started Aug 17 05:27:32 PM PDT 24
Finished Aug 17 05:27:35 PM PDT 24
Peak memory 198460 kb
Host smart-a5db5313-ed36-416a-9edc-c13e0d11f1fc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915624532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.2915624532
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.1445573724
Short name T76
Test name
Test status
Simulation time 23854117 ps
CPU time 0.6 seconds
Started Aug 17 05:27:20 PM PDT 24
Finished Aug 17 05:27:20 PM PDT 24
Peak memory 195128 kb
Host smart-15232b4f-5d61-4f7e-ae85-3cdbb90c94e9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445573724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.1445573724
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.1458472524
Short name T763
Test name
Test status
Simulation time 68462109 ps
CPU time 0.95 seconds
Started Aug 17 05:27:18 PM PDT 24
Finished Aug 17 05:27:19 PM PDT 24
Peak memory 198340 kb
Host smart-7e8988cb-5cda-41e9-b4d9-e9ac7ecbd6ec
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458472524 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.1458472524
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.2187174830
Short name T770
Test name
Test status
Simulation time 114909018 ps
CPU time 0.61 seconds
Started Aug 17 05:27:17 PM PDT 24
Finished Aug 17 05:27:18 PM PDT 24
Peak memory 195128 kb
Host smart-d44197d6-fe0c-4243-ba40-b9a577998c5d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187174830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.2187174830
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.2317192696
Short name T724
Test name
Test status
Simulation time 19166890 ps
CPU time 0.6 seconds
Started Aug 17 05:27:30 PM PDT 24
Finished Aug 17 05:27:30 PM PDT 24
Peak memory 194272 kb
Host smart-7abc6ce7-751b-4d55-b360-850c424df732
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317192696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.2317192696
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.1707888675
Short name T716
Test name
Test status
Simulation time 55399982 ps
CPU time 2.87 seconds
Started Aug 17 05:27:23 PM PDT 24
Finished Aug 17 05:27:26 PM PDT 24
Peak memory 198580 kb
Host smart-2ff807d2-86c2-402d-9241-f6bb98f83321
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707888675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.1707888675
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.2442507613
Short name T728
Test name
Test status
Simulation time 79140624 ps
CPU time 1.1 seconds
Started Aug 17 05:27:31 PM PDT 24
Finished Aug 17 05:27:32 PM PDT 24
Peak memory 198556 kb
Host smart-aa82f559-962f-4830-b284-dfe39e2a4151
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442507613 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.2442507613
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.1129605083
Short name T79
Test name
Test status
Simulation time 28031521 ps
CPU time 0.63 seconds
Started Aug 17 05:27:35 PM PDT 24
Finished Aug 17 05:27:36 PM PDT 24
Peak memory 195816 kb
Host smart-c24649a6-543e-41c3-b127-c9b970577bc9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129605083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.1129605083
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.1801999035
Short name T826
Test name
Test status
Simulation time 43961275 ps
CPU time 0.6 seconds
Started Aug 17 05:27:24 PM PDT 24
Finished Aug 17 05:27:24 PM PDT 24
Peak memory 194316 kb
Host smart-713e8aa8-754c-48b1-a125-d0dfef3fa25e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801999035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.1801999035
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.2165501091
Short name T91
Test name
Test status
Simulation time 21969354 ps
CPU time 0.79 seconds
Started Aug 17 05:27:23 PM PDT 24
Finished Aug 17 05:27:23 PM PDT 24
Peak memory 197372 kb
Host smart-5d4ddffa-52dc-4649-8e0d-75aa9f2b011f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165501091 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.2165501091
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.317248262
Short name T740
Test name
Test status
Simulation time 65167737 ps
CPU time 1.09 seconds
Started Aug 17 05:27:32 PM PDT 24
Finished Aug 17 05:27:34 PM PDT 24
Peak memory 198384 kb
Host smart-71f4b418-a90a-42cf-9f7a-ae2cae140883
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317248262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.317248262
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.1706470584
Short name T44
Test name
Test status
Simulation time 74073995 ps
CPU time 1.16 seconds
Started Aug 17 05:27:29 PM PDT 24
Finished Aug 17 05:27:30 PM PDT 24
Peak memory 198180 kb
Host smart-8cad9e5f-d2e4-4a66-a4d8-e88fd759d1a8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706470584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.1706470584
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.1074589544
Short name T717
Test name
Test status
Simulation time 138929749 ps
CPU time 0.86 seconds
Started Aug 17 05:27:27 PM PDT 24
Finished Aug 17 05:27:28 PM PDT 24
Peak memory 198384 kb
Host smart-6371b8b9-767b-4e6c-a642-18d7ee90df28
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074589544 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.1074589544
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.2517459052
Short name T78
Test name
Test status
Simulation time 113172569 ps
CPU time 0.63 seconds
Started Aug 17 05:27:23 PM PDT 24
Finished Aug 17 05:27:24 PM PDT 24
Peak memory 195336 kb
Host smart-1adfc8b3-d277-48a6-a1ee-2b2cb5ae1a6f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517459052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.2517459052
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.153130473
Short name T742
Test name
Test status
Simulation time 15078974 ps
CPU time 0.63 seconds
Started Aug 17 05:27:27 PM PDT 24
Finished Aug 17 05:27:28 PM PDT 24
Peak memory 194800 kb
Host smart-8f19f12a-7745-414e-80ab-315aa94d9f7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153130473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.153130473
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.183226616
Short name T89
Test name
Test status
Simulation time 173086473 ps
CPU time 0.89 seconds
Started Aug 17 05:27:25 PM PDT 24
Finished Aug 17 05:27:26 PM PDT 24
Peak memory 197816 kb
Host smart-9aaa80c6-fcf6-4120-84d6-15760a5e1734
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183226616 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 11.gpio_same_csr_outstanding.183226616
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.1952775620
Short name T779
Test name
Test status
Simulation time 60708667 ps
CPU time 1.67 seconds
Started Aug 17 05:27:36 PM PDT 24
Finished Aug 17 05:27:38 PM PDT 24
Peak memory 198556 kb
Host smart-ee6adfc5-a303-4035-9dbc-3880dca0d975
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952775620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.1952775620
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.2987530881
Short name T33
Test name
Test status
Simulation time 297658250 ps
CPU time 0.88 seconds
Started Aug 17 05:27:33 PM PDT 24
Finished Aug 17 05:27:34 PM PDT 24
Peak memory 198004 kb
Host smart-7f75ffea-c8c8-48b2-9e81-92ad6bb8c6e4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987530881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.2987530881
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.2942003297
Short name T786
Test name
Test status
Simulation time 46080951 ps
CPU time 1.14 seconds
Started Aug 17 05:27:27 PM PDT 24
Finished Aug 17 05:27:28 PM PDT 24
Peak memory 198516 kb
Host smart-3234c4a9-c11e-4a58-90cc-4054866f3cf6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942003297 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.2942003297
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.3732713132
Short name T758
Test name
Test status
Simulation time 78558393 ps
CPU time 0.6 seconds
Started Aug 17 05:27:29 PM PDT 24
Finished Aug 17 05:27:30 PM PDT 24
Peak memory 195180 kb
Host smart-da559eac-2e07-48c5-b26c-8627c062f900
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732713132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.3732713132
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.162652875
Short name T834
Test name
Test status
Simulation time 20226256 ps
CPU time 0.61 seconds
Started Aug 17 05:27:35 PM PDT 24
Finished Aug 17 05:27:36 PM PDT 24
Peak memory 194912 kb
Host smart-de5195e4-2982-4ba1-9dab-15cc643ab413
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162652875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.162652875
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.1874354960
Short name T810
Test name
Test status
Simulation time 55123136 ps
CPU time 0.83 seconds
Started Aug 17 05:27:29 PM PDT 24
Finished Aug 17 05:27:30 PM PDT 24
Peak memory 196788 kb
Host smart-acd493ed-4135-42f4-9d0f-ea40b8b81063
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874354960 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.1874354960
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.3916716363
Short name T774
Test name
Test status
Simulation time 64183889 ps
CPU time 1.38 seconds
Started Aug 17 05:27:44 PM PDT 24
Finished Aug 17 05:27:46 PM PDT 24
Peak memory 198532 kb
Host smart-4b28a1a7-f808-433e-9b95-1d2881bf1f53
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916716363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.3916716363
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.2983412829
Short name T823
Test name
Test status
Simulation time 126891112 ps
CPU time 1.13 seconds
Started Aug 17 05:27:29 PM PDT 24
Finished Aug 17 05:27:31 PM PDT 24
Peak memory 198416 kb
Host smart-f4c418f8-e1a2-4620-bdf7-2c1869862ce6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983412829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.2983412829
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.578961811
Short name T806
Test name
Test status
Simulation time 43169917 ps
CPU time 0.85 seconds
Started Aug 17 05:27:27 PM PDT 24
Finished Aug 17 05:27:28 PM PDT 24
Peak memory 198388 kb
Host smart-f7dcac6a-d469-44c4-8ec2-00985f52dfa6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578961811 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.578961811
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.615277251
Short name T821
Test name
Test status
Simulation time 35714708 ps
CPU time 0.56 seconds
Started Aug 17 05:27:35 PM PDT 24
Finished Aug 17 05:27:36 PM PDT 24
Peak memory 194404 kb
Host smart-3d5abd82-99dd-4717-9c48-0cec45c24124
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615277251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio
_csr_rw.615277251
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.1772378900
Short name T771
Test name
Test status
Simulation time 17795795 ps
CPU time 0.58 seconds
Started Aug 17 05:27:37 PM PDT 24
Finished Aug 17 05:27:37 PM PDT 24
Peak memory 194868 kb
Host smart-ee3fc2f8-f759-406c-ad0a-db14adc56f19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772378900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.1772378900
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.3814499174
Short name T822
Test name
Test status
Simulation time 40423759 ps
CPU time 0.71 seconds
Started Aug 17 05:27:37 PM PDT 24
Finished Aug 17 05:27:38 PM PDT 24
Peak memory 195552 kb
Host smart-deef7348-40c5-473d-a6ed-c6a93a08de37
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814499174 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.3814499174
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.1184606225
Short name T792
Test name
Test status
Simulation time 54683372 ps
CPU time 1.26 seconds
Started Aug 17 05:27:27 PM PDT 24
Finished Aug 17 05:27:29 PM PDT 24
Peak memory 198552 kb
Host smart-19b08976-e852-4ccb-bae3-3a752df43940
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184606225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.1184606225
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.717394234
Short name T40
Test name
Test status
Simulation time 48952747 ps
CPU time 0.88 seconds
Started Aug 17 05:27:37 PM PDT 24
Finished Aug 17 05:27:38 PM PDT 24
Peak memory 197680 kb
Host smart-60cc814e-a4be-49e8-b5a1-a2507ad778bd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717394234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 13.gpio_tl_intg_err.717394234
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.1223033577
Short name T731
Test name
Test status
Simulation time 49008487 ps
CPU time 0.91 seconds
Started Aug 17 05:27:31 PM PDT 24
Finished Aug 17 05:27:32 PM PDT 24
Peak memory 198608 kb
Host smart-e1c3a1eb-db46-4417-aa1f-311d8fb334c0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223033577 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.1223033577
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.551840140
Short name T82
Test name
Test status
Simulation time 21901941 ps
CPU time 0.61 seconds
Started Aug 17 05:27:26 PM PDT 24
Finished Aug 17 05:27:27 PM PDT 24
Peak memory 195940 kb
Host smart-c0e58dc0-76b1-4c81-afc7-be05ad4b48fc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551840140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio
_csr_rw.551840140
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.2261259953
Short name T809
Test name
Test status
Simulation time 32174747 ps
CPU time 0.65 seconds
Started Aug 17 05:27:35 PM PDT 24
Finished Aug 17 05:27:36 PM PDT 24
Peak memory 194280 kb
Host smart-0878c9ac-ac87-4c06-9aa9-e24d1f4d5b07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261259953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.2261259953
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.4082058949
Short name T800
Test name
Test status
Simulation time 192941396 ps
CPU time 0.81 seconds
Started Aug 17 05:27:26 PM PDT 24
Finished Aug 17 05:27:27 PM PDT 24
Peak memory 197264 kb
Host smart-9be395ad-2399-4f02-96c4-3ac3023f47ae
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082058949 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.4082058949
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.755651616
Short name T815
Test name
Test status
Simulation time 132997875 ps
CPU time 1.91 seconds
Started Aug 17 05:27:27 PM PDT 24
Finished Aug 17 05:27:30 PM PDT 24
Peak memory 198512 kb
Host smart-cd065dac-612c-482f-8151-dd870756870f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755651616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.755651616
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.3504718417
Short name T745
Test name
Test status
Simulation time 334373334 ps
CPU time 0.99 seconds
Started Aug 17 05:27:27 PM PDT 24
Finished Aug 17 05:27:28 PM PDT 24
Peak memory 198360 kb
Host smart-a620dc24-87ea-4dd6-b3f6-3ac97a3ff92e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504718417 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.3504718417
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.4220505336
Short name T767
Test name
Test status
Simulation time 23501015 ps
CPU time 0.6 seconds
Started Aug 17 05:27:54 PM PDT 24
Finished Aug 17 05:27:55 PM PDT 24
Peak memory 195108 kb
Host smart-e8957adf-43be-446a-9d68-efe5fbba4a04
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220505336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.4220505336
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.3129355508
Short name T830
Test name
Test status
Simulation time 19054191 ps
CPU time 0.61 seconds
Started Aug 17 05:27:29 PM PDT 24
Finished Aug 17 05:27:30 PM PDT 24
Peak memory 194172 kb
Host smart-ff553514-a1de-40dd-a3ff-ea904424f13e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129355508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.3129355508
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.1646613068
Short name T73
Test name
Test status
Simulation time 40202843 ps
CPU time 0.8 seconds
Started Aug 17 05:27:31 PM PDT 24
Finished Aug 17 05:27:32 PM PDT 24
Peak memory 196576 kb
Host smart-4ea75759-9761-4790-a03f-7cae560ec5f1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646613068 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.1646613068
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.380083502
Short name T738
Test name
Test status
Simulation time 94123431 ps
CPU time 1.09 seconds
Started Aug 17 05:27:33 PM PDT 24
Finished Aug 17 05:27:34 PM PDT 24
Peak memory 198496 kb
Host smart-f79c4e49-3a50-4a55-b269-f84b8538fa48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380083502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.380083502
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.1845928781
Short name T47
Test name
Test status
Simulation time 99593822 ps
CPU time 1.15 seconds
Started Aug 17 05:27:33 PM PDT 24
Finished Aug 17 05:27:34 PM PDT 24
Peak memory 198564 kb
Host smart-d73835e3-91a5-4bc6-a24d-640f2461ed00
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845928781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.1845928781
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.2629291237
Short name T772
Test name
Test status
Simulation time 58349111 ps
CPU time 0.9 seconds
Started Aug 17 05:27:26 PM PDT 24
Finished Aug 17 05:27:27 PM PDT 24
Peak memory 198388 kb
Host smart-66095188-c074-43dc-8226-a89f94bc45c4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629291237 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.2629291237
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.3401642727
Short name T804
Test name
Test status
Simulation time 12690380 ps
CPU time 0.6 seconds
Started Aug 17 05:27:34 PM PDT 24
Finished Aug 17 05:27:36 PM PDT 24
Peak memory 195104 kb
Host smart-d0630007-b7c4-4bff-b636-2d784aeb40a5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401642727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.3401642727
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.876103906
Short name T760
Test name
Test status
Simulation time 33403604 ps
CPU time 0.57 seconds
Started Aug 17 05:27:30 PM PDT 24
Finished Aug 17 05:27:31 PM PDT 24
Peak memory 194748 kb
Host smart-eea1d797-5373-4b0f-9a8d-2f2445126b14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876103906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.876103906
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.1157553271
Short name T799
Test name
Test status
Simulation time 36082150 ps
CPU time 0.82 seconds
Started Aug 17 05:27:27 PM PDT 24
Finished Aug 17 05:27:27 PM PDT 24
Peak memory 196752 kb
Host smart-12782d97-aa8d-4142-b742-544ceca2741b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157553271 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.1157553271
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.137613261
Short name T714
Test name
Test status
Simulation time 247178974 ps
CPU time 1.61 seconds
Started Aug 17 05:27:37 PM PDT 24
Finished Aug 17 05:27:38 PM PDT 24
Peak memory 198528 kb
Host smart-535fa076-12ac-42bb-a533-2b1b6cff0f30
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137613261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.137613261
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.4240839139
Short name T827
Test name
Test status
Simulation time 75607957 ps
CPU time 1.01 seconds
Started Aug 17 05:27:42 PM PDT 24
Finished Aug 17 05:27:43 PM PDT 24
Peak memory 197752 kb
Host smart-f3cd6461-a8d6-4e7a-bfa7-e34f8b9f2cc4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240839139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.4240839139
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.3423362722
Short name T766
Test name
Test status
Simulation time 98312118 ps
CPU time 0.91 seconds
Started Aug 17 05:27:27 PM PDT 24
Finished Aug 17 05:27:29 PM PDT 24
Peak memory 198284 kb
Host smart-635002d1-9b7c-4458-a73c-1f012a2c036c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423362722 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.3423362722
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.2974050795
Short name T74
Test name
Test status
Simulation time 40389795 ps
CPU time 0.6 seconds
Started Aug 17 05:27:29 PM PDT 24
Finished Aug 17 05:27:30 PM PDT 24
Peak memory 195144 kb
Host smart-8aac18f2-c101-4b9f-8999-c9f5f9cb1b5d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974050795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi
o_csr_rw.2974050795
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.2876956329
Short name T739
Test name
Test status
Simulation time 27904413 ps
CPU time 0.58 seconds
Started Aug 17 05:27:27 PM PDT 24
Finished Aug 17 05:27:27 PM PDT 24
Peak memory 194844 kb
Host smart-7828c788-2434-4afd-891d-395a4fb8b152
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876956329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.2876956329
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.813498024
Short name T829
Test name
Test status
Simulation time 64308290 ps
CPU time 0.67 seconds
Started Aug 17 05:27:30 PM PDT 24
Finished Aug 17 05:27:31 PM PDT 24
Peak memory 195416 kb
Host smart-52b058df-5378-4e89-b1b4-b66b168546c0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813498024 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 17.gpio_same_csr_outstanding.813498024
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.3019394662
Short name T764
Test name
Test status
Simulation time 167446953 ps
CPU time 1.77 seconds
Started Aug 17 05:27:32 PM PDT 24
Finished Aug 17 05:27:34 PM PDT 24
Peak memory 198576 kb
Host smart-97bd6f6d-b626-40ab-b95b-b56d950e0b62
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019394662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.3019394662
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.2011922869
Short name T45
Test name
Test status
Simulation time 47894757 ps
CPU time 0.84 seconds
Started Aug 17 05:27:31 PM PDT 24
Finished Aug 17 05:27:32 PM PDT 24
Peak memory 198312 kb
Host smart-7e9242ea-8578-4938-9528-98c78156b9d1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011922869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.2011922869
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.644244347
Short name T824
Test name
Test status
Simulation time 131600433 ps
CPU time 0.85 seconds
Started Aug 17 05:27:29 PM PDT 24
Finished Aug 17 05:27:31 PM PDT 24
Peak memory 198352 kb
Host smart-89dc242f-1fab-48e1-9ef0-4d4c3a32f9b4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644244347 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.644244347
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.252521635
Short name T798
Test name
Test status
Simulation time 28923289 ps
CPU time 0.58 seconds
Started Aug 17 05:27:31 PM PDT 24
Finished Aug 17 05:27:31 PM PDT 24
Peak memory 195080 kb
Host smart-39f98bc7-5dcf-4c68-a3bb-1de24bddd0aa
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252521635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio
_csr_rw.252521635
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.3052864146
Short name T789
Test name
Test status
Simulation time 13528857 ps
CPU time 0.59 seconds
Started Aug 17 05:27:36 PM PDT 24
Finished Aug 17 05:27:37 PM PDT 24
Peak memory 194796 kb
Host smart-3cabd367-bc1d-4774-86fe-a65a34627ffb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052864146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.3052864146
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.2614336059
Short name T788
Test name
Test status
Simulation time 154070824 ps
CPU time 0.84 seconds
Started Aug 17 05:27:27 PM PDT 24
Finished Aug 17 05:27:28 PM PDT 24
Peak memory 196800 kb
Host smart-63902f32-99e4-4367-a931-388da23a77af
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614336059 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.2614336059
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.3894352622
Short name T790
Test name
Test status
Simulation time 52252758 ps
CPU time 2.43 seconds
Started Aug 17 05:27:28 PM PDT 24
Finished Aug 17 05:27:30 PM PDT 24
Peak memory 198560 kb
Host smart-3c092ec9-a89a-47d4-bc54-ebeb4463c1ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894352622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.3894352622
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.651035123
Short name T718
Test name
Test status
Simulation time 22102662 ps
CPU time 0.77 seconds
Started Aug 17 05:27:27 PM PDT 24
Finished Aug 17 05:27:28 PM PDT 24
Peak memory 198364 kb
Host smart-df849e4f-6c09-4539-a790-2ce858878725
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651035123 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.651035123
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.4039962636
Short name T803
Test name
Test status
Simulation time 22024672 ps
CPU time 0.6 seconds
Started Aug 17 05:27:31 PM PDT 24
Finished Aug 17 05:27:32 PM PDT 24
Peak memory 195508 kb
Host smart-21ccd7e4-8d79-4982-b0bb-4f9de331171b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039962636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.4039962636
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.2308306098
Short name T753
Test name
Test status
Simulation time 15862338 ps
CPU time 0.62 seconds
Started Aug 17 05:27:29 PM PDT 24
Finished Aug 17 05:27:30 PM PDT 24
Peak memory 194788 kb
Host smart-7fafc75f-51c7-4d68-830e-925cf1f2c755
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308306098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.2308306098
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.3397854677
Short name T93
Test name
Test status
Simulation time 276022731 ps
CPU time 0.68 seconds
Started Aug 17 05:27:30 PM PDT 24
Finished Aug 17 05:27:30 PM PDT 24
Peak memory 195284 kb
Host smart-a3a49697-8d49-43a7-89a4-4a1528ad83d3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397854677 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.3397854677
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.1046102929
Short name T759
Test name
Test status
Simulation time 222054465 ps
CPU time 2.17 seconds
Started Aug 17 05:27:34 PM PDT 24
Finished Aug 17 05:27:37 PM PDT 24
Peak memory 198592 kb
Host smart-ce887f87-b6f4-4272-a9e8-2c59a20b8c6d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046102929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.1046102929
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.3446683592
Short name T96
Test name
Test status
Simulation time 168197659 ps
CPU time 0.87 seconds
Started Aug 17 05:27:27 PM PDT 24
Finished Aug 17 05:27:28 PM PDT 24
Peak memory 197532 kb
Host smart-106f0227-5070-4acb-91cf-b6aab21e7806
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446683592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.3446683592
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.1344824414
Short name T777
Test name
Test status
Simulation time 34803026 ps
CPU time 0.66 seconds
Started Aug 17 05:27:17 PM PDT 24
Finished Aug 17 05:27:18 PM PDT 24
Peak memory 194956 kb
Host smart-63c52b0d-af41-404f-adbf-b15407f35975
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344824414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.1344824414
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.1862698198
Short name T762
Test name
Test status
Simulation time 266875532 ps
CPU time 2.54 seconds
Started Aug 17 05:27:20 PM PDT 24
Finished Aug 17 05:27:23 PM PDT 24
Peak memory 198452 kb
Host smart-bf3bff99-db58-4293-a6bf-5ad262912648
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862698198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.1862698198
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.2268420738
Short name T754
Test name
Test status
Simulation time 33527223 ps
CPU time 0.65 seconds
Started Aug 17 05:27:22 PM PDT 24
Finished Aug 17 05:27:22 PM PDT 24
Peak memory 196908 kb
Host smart-82155683-dbab-468c-bf2c-c22c4cefafdc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268420738 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.2268420738
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.3445471058
Short name T84
Test name
Test status
Simulation time 15164422 ps
CPU time 0.61 seconds
Started Aug 17 05:27:21 PM PDT 24
Finished Aug 17 05:27:22 PM PDT 24
Peak memory 195004 kb
Host smart-d7637b4f-3943-4350-b22e-275431355368
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445471058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.3445471058
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.200676537
Short name T750
Test name
Test status
Simulation time 12129912 ps
CPU time 0.63 seconds
Started Aug 17 05:27:36 PM PDT 24
Finished Aug 17 05:27:37 PM PDT 24
Peak memory 194216 kb
Host smart-db9f6e31-9fc0-445d-bb0b-00c8f20a74ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200676537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.200676537
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.780212542
Short name T94
Test name
Test status
Simulation time 67640822 ps
CPU time 0.85 seconds
Started Aug 17 05:27:33 PM PDT 24
Finished Aug 17 05:27:34 PM PDT 24
Peak memory 196692 kb
Host smart-206669e8-7834-4538-960d-feb6d4aaf288
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780212542 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.gpio_same_csr_outstanding.780212542
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.3469256286
Short name T734
Test name
Test status
Simulation time 54808770 ps
CPU time 2.69 seconds
Started Aug 17 05:27:20 PM PDT 24
Finished Aug 17 05:27:22 PM PDT 24
Peak memory 198596 kb
Host smart-99ae699e-8b5a-440c-8c81-062e9c9cb53e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469256286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.3469256286
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.4253220088
Short name T34
Test name
Test status
Simulation time 1016231629 ps
CPU time 1.41 seconds
Started Aug 17 05:27:17 PM PDT 24
Finished Aug 17 05:27:18 PM PDT 24
Peak memory 198496 kb
Host smart-5eee8566-1096-4493-8a35-4148166141f2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253220088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.4253220088
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.3678012454
Short name T733
Test name
Test status
Simulation time 14649336 ps
CPU time 0.65 seconds
Started Aug 17 05:27:27 PM PDT 24
Finished Aug 17 05:27:28 PM PDT 24
Peak memory 194208 kb
Host smart-691ef47a-2eaf-4878-896a-d941a619f1d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678012454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.3678012454
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.608307076
Short name T784
Test name
Test status
Simulation time 16823343 ps
CPU time 0.61 seconds
Started Aug 17 05:27:26 PM PDT 24
Finished Aug 17 05:27:27 PM PDT 24
Peak memory 194900 kb
Host smart-67eea1f6-d685-4473-baa2-345233b9fc35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608307076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.608307076
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.2554547280
Short name T727
Test name
Test status
Simulation time 18882116 ps
CPU time 0.62 seconds
Started Aug 17 05:27:31 PM PDT 24
Finished Aug 17 05:27:32 PM PDT 24
Peak memory 193688 kb
Host smart-3b4242b6-825d-4ba3-810f-08981d981a37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554547280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.2554547280
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.1294782938
Short name T746
Test name
Test status
Simulation time 19646793 ps
CPU time 0.56 seconds
Started Aug 17 05:27:33 PM PDT 24
Finished Aug 17 05:27:34 PM PDT 24
Peak memory 194200 kb
Host smart-0cc8ee74-7946-435f-8c29-6710fb1c83de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294782938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.1294782938
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.2897340477
Short name T802
Test name
Test status
Simulation time 12467552 ps
CPU time 0.61 seconds
Started Aug 17 05:27:42 PM PDT 24
Finished Aug 17 05:27:43 PM PDT 24
Peak memory 194232 kb
Host smart-b307691d-0563-4250-acee-371003ca3282
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897340477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.2897340477
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.699100696
Short name T749
Test name
Test status
Simulation time 19924148 ps
CPU time 0.65 seconds
Started Aug 17 05:27:35 PM PDT 24
Finished Aug 17 05:27:36 PM PDT 24
Peak memory 194908 kb
Host smart-d447d0f7-ae25-4e37-bdde-16824ffce76c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699100696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.699100696
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.3172444372
Short name T751
Test name
Test status
Simulation time 40494950 ps
CPU time 0.59 seconds
Started Aug 17 05:27:27 PM PDT 24
Finished Aug 17 05:27:28 PM PDT 24
Peak memory 194116 kb
Host smart-45b26796-91a6-46f6-af03-9b8a1b3f04e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172444372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.3172444372
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.1944807689
Short name T832
Test name
Test status
Simulation time 17478948 ps
CPU time 0.62 seconds
Started Aug 17 05:27:35 PM PDT 24
Finished Aug 17 05:27:36 PM PDT 24
Peak memory 194188 kb
Host smart-a2906b0d-05c1-400e-a37e-64d965ec7129
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944807689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.1944807689
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.4169113279
Short name T736
Test name
Test status
Simulation time 57839757 ps
CPU time 0.61 seconds
Started Aug 17 05:27:43 PM PDT 24
Finished Aug 17 05:27:44 PM PDT 24
Peak memory 194284 kb
Host smart-c5bf75d9-62ff-43ce-b0af-8ac6a229e238
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169113279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.4169113279
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.2467358411
Short name T735
Test name
Test status
Simulation time 14023675 ps
CPU time 0.62 seconds
Started Aug 17 05:27:31 PM PDT 24
Finished Aug 17 05:27:32 PM PDT 24
Peak memory 193792 kb
Host smart-b9cfd4e2-f9d3-42bb-9a1b-a4d98e01099d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467358411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.2467358411
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.3182293384
Short name T95
Test name
Test status
Simulation time 32907763 ps
CPU time 0.86 seconds
Started Aug 17 05:27:19 PM PDT 24
Finished Aug 17 05:27:20 PM PDT 24
Peak memory 196376 kb
Host smart-927805b5-7929-4005-a459-4b7a56a6ce45
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182293384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.3182293384
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.1820177361
Short name T86
Test name
Test status
Simulation time 79984326 ps
CPU time 3.05 seconds
Started Aug 17 05:27:24 PM PDT 24
Finished Aug 17 05:27:28 PM PDT 24
Peak memory 197652 kb
Host smart-dde16d07-d7db-48f2-abeb-a0a20b842abc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820177361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.1820177361
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.962134773
Short name T81
Test name
Test status
Simulation time 22906947 ps
CPU time 0.61 seconds
Started Aug 17 05:27:16 PM PDT 24
Finished Aug 17 05:27:17 PM PDT 24
Peak memory 194848 kb
Host smart-c5b4cfa3-7a77-4fb2-b746-3c354521f02d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962134773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.962134773
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.837952097
Short name T719
Test name
Test status
Simulation time 21252775 ps
CPU time 0.95 seconds
Started Aug 17 05:27:18 PM PDT 24
Finished Aug 17 05:27:19 PM PDT 24
Peak memory 198392 kb
Host smart-4e766ac4-4dd0-4b92-b053-c7eba65ba3e9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837952097 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.837952097
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.2711934480
Short name T825
Test name
Test status
Simulation time 43353410 ps
CPU time 0.62 seconds
Started Aug 17 05:27:18 PM PDT 24
Finished Aug 17 05:27:19 PM PDT 24
Peak memory 195104 kb
Host smart-ea6a893b-fb8d-4f7f-9a1e-db092fef46ac
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711934480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.2711934480
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.2879371123
Short name T713
Test name
Test status
Simulation time 12853978 ps
CPU time 0.58 seconds
Started Aug 17 05:27:29 PM PDT 24
Finished Aug 17 05:27:30 PM PDT 24
Peak memory 194164 kb
Host smart-e2de4ec5-d1ad-4e07-b611-5c851cabe690
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879371123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.2879371123
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.574722060
Short name T778
Test name
Test status
Simulation time 137692642 ps
CPU time 0.85 seconds
Started Aug 17 05:27:23 PM PDT 24
Finished Aug 17 05:27:24 PM PDT 24
Peak memory 197284 kb
Host smart-4ee1a33c-7f44-48d2-b875-38d4b415723e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574722060 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.gpio_same_csr_outstanding.574722060
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.33401375
Short name T819
Test name
Test status
Simulation time 101383736 ps
CPU time 1.35 seconds
Started Aug 17 05:27:19 PM PDT 24
Finished Aug 17 05:27:21 PM PDT 24
Peak memory 198496 kb
Host smart-501357f2-11f1-4193-899a-5362248195ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33401375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.33401375
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.368582506
Short name T757
Test name
Test status
Simulation time 176837740 ps
CPU time 0.84 seconds
Started Aug 17 05:27:32 PM PDT 24
Finished Aug 17 05:27:33 PM PDT 24
Peak memory 197616 kb
Host smart-e8567da3-4af7-4524-a924-e055eab305d6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368582506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 3.gpio_tl_intg_err.368582506
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.1624435005
Short name T811
Test name
Test status
Simulation time 43668783 ps
CPU time 0.56 seconds
Started Aug 17 05:27:26 PM PDT 24
Finished Aug 17 05:27:26 PM PDT 24
Peak memory 195036 kb
Host smart-7b7f4ec1-4c9e-4303-b92f-588da1da689f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624435005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.1624435005
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.13789317
Short name T787
Test name
Test status
Simulation time 22963287 ps
CPU time 0.59 seconds
Started Aug 17 05:27:34 PM PDT 24
Finished Aug 17 05:27:35 PM PDT 24
Peak memory 194884 kb
Host smart-f9d75650-0522-45aa-8c07-5c88ca1eff2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13789317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.13789317
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.1553709932
Short name T794
Test name
Test status
Simulation time 30587955 ps
CPU time 0.56 seconds
Started Aug 17 05:27:34 PM PDT 24
Finished Aug 17 05:27:35 PM PDT 24
Peak memory 194180 kb
Host smart-310fe0b1-0983-418d-baf6-8fde192b307e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553709932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.1553709932
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.3140774558
Short name T818
Test name
Test status
Simulation time 61118508 ps
CPU time 0.6 seconds
Started Aug 17 05:27:33 PM PDT 24
Finished Aug 17 05:27:33 PM PDT 24
Peak memory 194232 kb
Host smart-e5892504-b2c2-47d2-bbab-8cea1be885d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140774558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.3140774558
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.4234823402
Short name T808
Test name
Test status
Simulation time 48928683 ps
CPU time 0.61 seconds
Started Aug 17 05:27:36 PM PDT 24
Finished Aug 17 05:27:37 PM PDT 24
Peak memory 194284 kb
Host smart-c375ec49-14b4-49af-82b0-f3d5ede00371
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234823402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.4234823402
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.1492540691
Short name T768
Test name
Test status
Simulation time 14970369 ps
CPU time 0.61 seconds
Started Aug 17 05:27:37 PM PDT 24
Finished Aug 17 05:27:37 PM PDT 24
Peak memory 194160 kb
Host smart-d2ce571f-c750-4730-aea2-f2b96b7119ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492540691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.1492540691
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.4231938556
Short name T776
Test name
Test status
Simulation time 16834715 ps
CPU time 0.61 seconds
Started Aug 17 05:27:30 PM PDT 24
Finished Aug 17 05:27:31 PM PDT 24
Peak memory 194276 kb
Host smart-0f177838-8d33-4e7b-b184-5998a526951f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231938556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.4231938556
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.4084342689
Short name T726
Test name
Test status
Simulation time 35458040 ps
CPU time 0.6 seconds
Started Aug 17 05:27:36 PM PDT 24
Finished Aug 17 05:27:37 PM PDT 24
Peak memory 194284 kb
Host smart-d00b38df-99a6-45bc-8043-5dd9848b57bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084342689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.4084342689
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.516552338
Short name T782
Test name
Test status
Simulation time 21567773 ps
CPU time 0.62 seconds
Started Aug 17 05:27:42 PM PDT 24
Finished Aug 17 05:27:42 PM PDT 24
Peak memory 194852 kb
Host smart-65035ff5-badb-4a3d-9234-925d90e8ae0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516552338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.516552338
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.3736135206
Short name T756
Test name
Test status
Simulation time 36470064 ps
CPU time 0.56 seconds
Started Aug 17 05:28:00 PM PDT 24
Finished Aug 17 05:28:01 PM PDT 24
Peak memory 194200 kb
Host smart-0ed499ba-4e4b-482c-bc6d-a97bbec6ac54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736135206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.3736135206
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.2693952518
Short name T761
Test name
Test status
Simulation time 33038903 ps
CPU time 0.64 seconds
Started Aug 17 05:27:32 PM PDT 24
Finished Aug 17 05:27:33 PM PDT 24
Peak memory 194924 kb
Host smart-83d6385c-542f-4b96-9123-d2ce8d130d76
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693952518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.2693952518
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.3569610810
Short name T729
Test name
Test status
Simulation time 177427872 ps
CPU time 2.48 seconds
Started Aug 17 05:27:24 PM PDT 24
Finished Aug 17 05:27:27 PM PDT 24
Peak memory 198056 kb
Host smart-e2a63ed2-086e-4bf0-8984-a0251f948ef7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569610810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.3569610810
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.3335576102
Short name T743
Test name
Test status
Simulation time 14793387 ps
CPU time 0.64 seconds
Started Aug 17 05:27:18 PM PDT 24
Finished Aug 17 05:27:19 PM PDT 24
Peak memory 195044 kb
Host smart-3872ce25-f8d1-4986-893b-21b7ed4b4b00
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335576102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.3335576102
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.1292089214
Short name T755
Test name
Test status
Simulation time 30603896 ps
CPU time 1.38 seconds
Started Aug 17 05:27:35 PM PDT 24
Finished Aug 17 05:27:37 PM PDT 24
Peak memory 198152 kb
Host smart-2a9841f4-cb0a-475c-8900-374b12e88bac
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292089214 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.1292089214
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.2125746728
Short name T765
Test name
Test status
Simulation time 16379128 ps
CPU time 0.6 seconds
Started Aug 17 05:27:34 PM PDT 24
Finished Aug 17 05:27:35 PM PDT 24
Peak memory 195048 kb
Host smart-d7b55c0a-b1a7-43d8-974b-8c05730874b7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125746728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.2125746728
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.2363487764
Short name T720
Test name
Test status
Simulation time 22462830 ps
CPU time 0.65 seconds
Started Aug 17 05:27:35 PM PDT 24
Finished Aug 17 05:27:36 PM PDT 24
Peak memory 194212 kb
Host smart-a32d9fc8-b977-4f26-aff0-a42219c1f318
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363487764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.2363487764
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.491146494
Short name T92
Test name
Test status
Simulation time 36597023 ps
CPU time 0.82 seconds
Started Aug 17 05:27:23 PM PDT 24
Finished Aug 17 05:27:24 PM PDT 24
Peak memory 196728 kb
Host smart-f35f4e52-02f8-4d13-9754-e2ee73e94d08
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491146494 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.gpio_same_csr_outstanding.491146494
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.3030940567
Short name T828
Test name
Test status
Simulation time 497922121 ps
CPU time 2.5 seconds
Started Aug 17 05:27:24 PM PDT 24
Finished Aug 17 05:27:26 PM PDT 24
Peak memory 198572 kb
Host smart-62d5571c-8cca-4bb2-869c-b4638398c95b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030940567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.3030940567
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.2675551088
Short name T43
Test name
Test status
Simulation time 271561273 ps
CPU time 1.13 seconds
Started Aug 17 05:27:31 PM PDT 24
Finished Aug 17 05:27:32 PM PDT 24
Peak memory 198564 kb
Host smart-939d7da1-6083-4652-987a-f3e58b223f9c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675551088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.2675551088
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.3744209189
Short name T781
Test name
Test status
Simulation time 13206754 ps
CPU time 0.6 seconds
Started Aug 17 05:27:34 PM PDT 24
Finished Aug 17 05:27:35 PM PDT 24
Peak memory 194240 kb
Host smart-55d3cc2d-07e0-49b7-bdbf-7e4cef19fa1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744209189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.3744209189
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.2721784565
Short name T732
Test name
Test status
Simulation time 66212433 ps
CPU time 0.61 seconds
Started Aug 17 05:28:03 PM PDT 24
Finished Aug 17 05:28:04 PM PDT 24
Peak memory 194828 kb
Host smart-f9c61dcb-9866-4939-9b18-3e129e7bb0ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721784565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.2721784565
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.1414462251
Short name T715
Test name
Test status
Simulation time 13744311 ps
CPU time 0.62 seconds
Started Aug 17 05:27:59 PM PDT 24
Finished Aug 17 05:28:00 PM PDT 24
Peak memory 194268 kb
Host smart-e49759f8-f12f-44ea-86c7-1abc6d13ca70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414462251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.1414462251
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.3334449051
Short name T807
Test name
Test status
Simulation time 26007431 ps
CPU time 0.59 seconds
Started Aug 17 05:27:43 PM PDT 24
Finished Aug 17 05:27:44 PM PDT 24
Peak memory 194824 kb
Host smart-ab604d63-57c3-42a9-94ad-c6d71333ac51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334449051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.3334449051
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.3122871711
Short name T722
Test name
Test status
Simulation time 58750927 ps
CPU time 0.61 seconds
Started Aug 17 05:27:35 PM PDT 24
Finished Aug 17 05:27:36 PM PDT 24
Peak memory 194976 kb
Host smart-f5e84dc7-ac56-485b-a82f-298e8872efd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122871711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.3122871711
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.3930418997
Short name T817
Test name
Test status
Simulation time 20941788 ps
CPU time 0.57 seconds
Started Aug 17 05:27:55 PM PDT 24
Finished Aug 17 05:27:56 PM PDT 24
Peak memory 194180 kb
Host smart-2e0ad075-672d-424f-88bd-d6ffa7f3e777
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930418997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.3930418997
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.281601992
Short name T725
Test name
Test status
Simulation time 13971457 ps
CPU time 0.59 seconds
Started Aug 17 05:27:52 PM PDT 24
Finished Aug 17 05:27:52 PM PDT 24
Peak memory 194140 kb
Host smart-7f2c795d-dca1-49ff-b42d-3a388ceb1124
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281601992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.281601992
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.824911273
Short name T737
Test name
Test status
Simulation time 18149200 ps
CPU time 0.6 seconds
Started Aug 17 05:27:59 PM PDT 24
Finished Aug 17 05:28:00 PM PDT 24
Peak memory 194864 kb
Host smart-c0335936-78b4-4f26-912f-c8c8926f4666
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824911273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.824911273
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.4261926679
Short name T721
Test name
Test status
Simulation time 19078021 ps
CPU time 0.57 seconds
Started Aug 17 05:27:36 PM PDT 24
Finished Aug 17 05:27:36 PM PDT 24
Peak memory 194176 kb
Host smart-f898bac1-a6de-4010-9c82-1ed0b03b5cb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261926679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.4261926679
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.2605328896
Short name T723
Test name
Test status
Simulation time 25049101 ps
CPU time 0.6 seconds
Started Aug 17 05:27:53 PM PDT 24
Finished Aug 17 05:27:53 PM PDT 24
Peak memory 194160 kb
Host smart-7f3cedd4-0d01-43f9-adb9-7c0d39e52ac5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605328896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.2605328896
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.3838109257
Short name T730
Test name
Test status
Simulation time 25473865 ps
CPU time 0.73 seconds
Started Aug 17 05:27:33 PM PDT 24
Finished Aug 17 05:27:34 PM PDT 24
Peak memory 197868 kb
Host smart-abadc39b-7499-491c-806c-c24639a10b4b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838109257 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.3838109257
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.475403286
Short name T752
Test name
Test status
Simulation time 14348538 ps
CPU time 0.61 seconds
Started Aug 17 05:27:19 PM PDT 24
Finished Aug 17 05:27:20 PM PDT 24
Peak memory 195820 kb
Host smart-bdccc20f-7b38-40fa-9713-51a777639809
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475403286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_
csr_rw.475403286
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.3978962741
Short name T748
Test name
Test status
Simulation time 41202043 ps
CPU time 0.6 seconds
Started Aug 17 05:27:21 PM PDT 24
Finished Aug 17 05:27:22 PM PDT 24
Peak memory 194776 kb
Host smart-49282f77-f8ff-4cec-a561-bc9f4af9c506
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978962741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.3978962741
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.80141921
Short name T833
Test name
Test status
Simulation time 68449679 ps
CPU time 0.78 seconds
Started Aug 17 05:27:19 PM PDT 24
Finished Aug 17 05:27:20 PM PDT 24
Peak memory 196276 kb
Host smart-0edf9557-a51d-499b-97fb-ae1da932a31f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80141921 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.gpio_same_csr_outstanding.80141921
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.3416889998
Short name T795
Test name
Test status
Simulation time 152149015 ps
CPU time 2.42 seconds
Started Aug 17 05:27:19 PM PDT 24
Finished Aug 17 05:27:22 PM PDT 24
Peak memory 198628 kb
Host smart-901b4074-2fcf-477b-933b-1caa2e645bef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416889998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.3416889998
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.752524167
Short name T42
Test name
Test status
Simulation time 489777357 ps
CPU time 1.2 seconds
Started Aug 17 05:27:22 PM PDT 24
Finished Aug 17 05:27:23 PM PDT 24
Peak memory 198500 kb
Host smart-10db29fe-0e6a-4393-80c4-41fb07f0f4a0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752524167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 5.gpio_tl_intg_err.752524167
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.1859357746
Short name T712
Test name
Test status
Simulation time 21323832 ps
CPU time 0.76 seconds
Started Aug 17 05:27:17 PM PDT 24
Finished Aug 17 05:27:18 PM PDT 24
Peak memory 197828 kb
Host smart-c6266d3e-b370-4de1-910b-d5d5967eccc9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859357746 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.1859357746
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.3891415903
Short name T769
Test name
Test status
Simulation time 13788583 ps
CPU time 0.6 seconds
Started Aug 17 05:27:19 PM PDT 24
Finished Aug 17 05:27:20 PM PDT 24
Peak memory 194972 kb
Host smart-1e8d6cbd-ef37-4df0-a3de-0e505dcbbcb7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891415903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.3891415903
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.4177033216
Short name T741
Test name
Test status
Simulation time 19406722 ps
CPU time 0.58 seconds
Started Aug 17 05:27:32 PM PDT 24
Finished Aug 17 05:27:33 PM PDT 24
Peak memory 194204 kb
Host smart-3ed7e859-b0c0-42e0-b556-c6cb21766493
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177033216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.4177033216
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.65047996
Short name T77
Test name
Test status
Simulation time 28599880 ps
CPU time 0.79 seconds
Started Aug 17 05:27:26 PM PDT 24
Finished Aug 17 05:27:27 PM PDT 24
Peak memory 196604 kb
Host smart-ad2eee51-6323-4a43-8f58-9c8d3217b115
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65047996 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.gpio_same_csr_outstanding.65047996
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.2621246218
Short name T747
Test name
Test status
Simulation time 309108921 ps
CPU time 3.29 seconds
Started Aug 17 05:27:17 PM PDT 24
Finished Aug 17 05:27:21 PM PDT 24
Peak memory 198588 kb
Host smart-5e2fc6f6-b2b0-4a98-87d3-cb22d151f039
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621246218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.2621246218
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.2224444812
Short name T820
Test name
Test status
Simulation time 640887123 ps
CPU time 1.16 seconds
Started Aug 17 05:27:31 PM PDT 24
Finished Aug 17 05:27:33 PM PDT 24
Peak memory 198552 kb
Host smart-594a614d-f908-4ac6-a610-2fdb4ed05cb4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224444812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.2224444812
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.3288757430
Short name T816
Test name
Test status
Simulation time 46314189 ps
CPU time 1.31 seconds
Started Aug 17 05:27:34 PM PDT 24
Finished Aug 17 05:27:36 PM PDT 24
Peak memory 198636 kb
Host smart-c4ab5bfe-f72a-42b3-bba1-2fcb29da0061
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288757430 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.3288757430
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.3080394528
Short name T780
Test name
Test status
Simulation time 55965811 ps
CPU time 0.6 seconds
Started Aug 17 05:27:24 PM PDT 24
Finished Aug 17 05:27:24 PM PDT 24
Peak memory 195480 kb
Host smart-de32cd92-16ab-4586-991d-1e81e739c34a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080394528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.3080394528
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.264845254
Short name T797
Test name
Test status
Simulation time 29010132 ps
CPU time 0.59 seconds
Started Aug 17 05:27:20 PM PDT 24
Finished Aug 17 05:27:21 PM PDT 24
Peak memory 194856 kb
Host smart-7e86083a-cb9e-4c5c-8473-fc8e43397c8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264845254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.264845254
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.1604943234
Short name T70
Test name
Test status
Simulation time 40504056 ps
CPU time 0.86 seconds
Started Aug 17 05:27:32 PM PDT 24
Finished Aug 17 05:27:33 PM PDT 24
Peak memory 197396 kb
Host smart-f91d51d1-2315-41b9-ac0b-cb87971177f9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604943234 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.1604943234
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.3717051827
Short name T805
Test name
Test status
Simulation time 75138095 ps
CPU time 1.06 seconds
Started Aug 17 05:27:34 PM PDT 24
Finished Aug 17 05:27:36 PM PDT 24
Peak memory 198276 kb
Host smart-fef01538-895d-405b-9135-3585aa58ff69
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717051827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.3717051827
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.594279740
Short name T31
Test name
Test status
Simulation time 187624000 ps
CPU time 1.45 seconds
Started Aug 17 05:27:18 PM PDT 24
Finished Aug 17 05:27:19 PM PDT 24
Peak memory 198520 kb
Host smart-9fadd7ed-0ac8-4e9d-96f6-8fd87fc209ba
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594279740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 7.gpio_tl_intg_err.594279740
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.3154276454
Short name T775
Test name
Test status
Simulation time 18171469 ps
CPU time 0.87 seconds
Started Aug 17 05:27:31 PM PDT 24
Finished Aug 17 05:27:32 PM PDT 24
Peak memory 198436 kb
Host smart-e1b6fde8-c0e2-461a-81d8-927f2157efdd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154276454 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.3154276454
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.3888691316
Short name T71
Test name
Test status
Simulation time 39145713 ps
CPU time 0.57 seconds
Started Aug 17 05:27:19 PM PDT 24
Finished Aug 17 05:27:20 PM PDT 24
Peak memory 193992 kb
Host smart-9213811a-ab01-4c1a-a12a-b9c9e370a462
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888691316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.3888691316
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.959846137
Short name T791
Test name
Test status
Simulation time 25133854 ps
CPU time 0.59 seconds
Started Aug 17 05:27:19 PM PDT 24
Finished Aug 17 05:27:20 PM PDT 24
Peak memory 194780 kb
Host smart-ece3d488-3854-46b9-a31b-974d5e189c47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959846137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.959846137
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.1948452618
Short name T796
Test name
Test status
Simulation time 48480122 ps
CPU time 0.79 seconds
Started Aug 17 05:27:34 PM PDT 24
Finished Aug 17 05:27:35 PM PDT 24
Peak memory 197256 kb
Host smart-65ee95c8-091d-4372-8591-b94db190d69d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948452618 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.1948452618
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.2122788454
Short name T831
Test name
Test status
Simulation time 47455489 ps
CPU time 2.29 seconds
Started Aug 17 05:27:33 PM PDT 24
Finished Aug 17 05:27:35 PM PDT 24
Peak memory 198676 kb
Host smart-0ee6faee-7431-4960-81e3-95c4b01306d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122788454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.2122788454
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.224510255
Short name T97
Test name
Test status
Simulation time 183958211 ps
CPU time 0.9 seconds
Started Aug 17 05:27:20 PM PDT 24
Finished Aug 17 05:27:21 PM PDT 24
Peak memory 198268 kb
Host smart-af811b0b-a5c7-4a56-9f7e-da486a4c0f61
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224510255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 8.gpio_tl_intg_err.224510255
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.3253987199
Short name T783
Test name
Test status
Simulation time 28251287 ps
CPU time 0.71 seconds
Started Aug 17 05:27:34 PM PDT 24
Finished Aug 17 05:27:35 PM PDT 24
Peak memory 197496 kb
Host smart-2ff4c081-dc75-4571-a392-d6df1dee4a83
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253987199 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.3253987199
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.319308620
Short name T87
Test name
Test status
Simulation time 12572227 ps
CPU time 0.62 seconds
Started Aug 17 05:27:19 PM PDT 24
Finished Aug 17 05:27:20 PM PDT 24
Peak memory 194784 kb
Host smart-5a89f087-d5fe-47cb-b727-6d1897d6120d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319308620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_
csr_rw.319308620
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.3510749388
Short name T773
Test name
Test status
Simulation time 18506563 ps
CPU time 0.62 seconds
Started Aug 17 05:27:30 PM PDT 24
Finished Aug 17 05:27:31 PM PDT 24
Peak memory 194912 kb
Host smart-d20fc581-0c70-4627-92f0-101f2c7fff96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510749388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.3510749388
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.3946066118
Short name T90
Test name
Test status
Simulation time 80293870 ps
CPU time 0.78 seconds
Started Aug 17 05:27:20 PM PDT 24
Finished Aug 17 05:27:21 PM PDT 24
Peak memory 196372 kb
Host smart-282c5a47-0f80-4fd0-b6f5-596280303e1d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946066118 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.3946066118
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.3087083210
Short name T812
Test name
Test status
Simulation time 111448569 ps
CPU time 0.89 seconds
Started Aug 17 05:27:22 PM PDT 24
Finished Aug 17 05:27:23 PM PDT 24
Peak memory 198304 kb
Host smart-f2e3a0d8-3c04-48ed-95bc-4a5f9ec6fb0f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087083210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.3087083210
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.4122929923
Short name T41
Test name
Test status
Simulation time 47776931 ps
CPU time 0.87 seconds
Started Aug 17 05:27:28 PM PDT 24
Finished Aug 17 05:27:29 PM PDT 24
Peak memory 197588 kb
Host smart-6f069271-418c-431b-acb7-fd0e785f303e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122929923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.4122929923
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.2106293163
Short name T300
Test name
Test status
Simulation time 169893709 ps
CPU time 0.54 seconds
Started Aug 17 05:32:17 PM PDT 24
Finished Aug 17 05:32:18 PM PDT 24
Peak memory 195004 kb
Host smart-1022b196-02ca-4a3e-9907-2b0c6e3cabb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106293163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.2106293163
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.2653584735
Short name T642
Test name
Test status
Simulation time 41488485 ps
CPU time 0.9 seconds
Started Aug 17 05:32:12 PM PDT 24
Finished Aug 17 05:32:13 PM PDT 24
Peak memory 196556 kb
Host smart-7e4149fc-26e4-4baf-9903-281fa00e2a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653584735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.2653584735
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.2884578987
Short name T360
Test name
Test status
Simulation time 2699399597 ps
CPU time 22.88 seconds
Started Aug 17 05:32:10 PM PDT 24
Finished Aug 17 05:32:33 PM PDT 24
Peak memory 197032 kb
Host smart-118045b9-1f79-4b89-9879-353bee0c5c1e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884578987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.2884578987
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.3382811145
Short name T361
Test name
Test status
Simulation time 112377399 ps
CPU time 0.64 seconds
Started Aug 17 05:32:10 PM PDT 24
Finished Aug 17 05:32:11 PM PDT 24
Peak memory 194416 kb
Host smart-c12ab311-d092-4ff7-b89c-9ccb4dff7133
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382811145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.3382811145
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.1749080239
Short name T67
Test name
Test status
Simulation time 28377918 ps
CPU time 0.66 seconds
Started Aug 17 05:32:11 PM PDT 24
Finished Aug 17 05:32:12 PM PDT 24
Peak memory 195132 kb
Host smart-aecd244f-139a-46ed-ba8c-99302149a3af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749080239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.1749080239
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.1814197515
Short name T595
Test name
Test status
Simulation time 118812656 ps
CPU time 3.54 seconds
Started Aug 17 05:32:11 PM PDT 24
Finished Aug 17 05:32:15 PM PDT 24
Peak memory 198152 kb
Host smart-211c2a73-200c-4ead-95cf-73970772d137
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814197515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.1814197515
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.1693357079
Short name T570
Test name
Test status
Simulation time 417379707 ps
CPU time 3.59 seconds
Started Aug 17 05:32:09 PM PDT 24
Finished Aug 17 05:32:13 PM PDT 24
Peak memory 198168 kb
Host smart-b043e47a-58e6-4d6f-91db-656851e9a7cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693357079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
1693357079
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.1693971949
Short name T670
Test name
Test status
Simulation time 98336500 ps
CPU time 0.83 seconds
Started Aug 17 05:32:03 PM PDT 24
Finished Aug 17 05:32:04 PM PDT 24
Peak memory 196704 kb
Host smart-5fab84c7-f485-408c-8586-8d586d024974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693971949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.1693971949
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.796157552
Short name T208
Test name
Test status
Simulation time 70430034 ps
CPU time 0.71 seconds
Started Aug 17 05:32:05 PM PDT 24
Finished Aug 17 05:32:05 PM PDT 24
Peak memory 195512 kb
Host smart-64245681-3ce9-4f04-a55e-59758ebd4688
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796157552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup_
pulldown.796157552
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.2290974574
Short name T359
Test name
Test status
Simulation time 62936588 ps
CPU time 1.58 seconds
Started Aug 17 05:32:13 PM PDT 24
Finished Aug 17 05:32:15 PM PDT 24
Peak memory 198232 kb
Host smart-834e7912-f594-40aa-9382-6e856a6e2194
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290974574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.2290974574
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.3166990524
Short name T49
Test name
Test status
Simulation time 382725017 ps
CPU time 0.85 seconds
Started Aug 17 05:32:18 PM PDT 24
Finished Aug 17 05:32:19 PM PDT 24
Peak memory 214052 kb
Host smart-e9b2558c-a7de-4b72-98ed-ddef39956ef5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166990524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.3166990524
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/default/0.gpio_smoke.4028144090
Short name T335
Test name
Test status
Simulation time 242111664 ps
CPU time 1.28 seconds
Started Aug 17 05:32:05 PM PDT 24
Finished Aug 17 05:32:06 PM PDT 24
Peak memory 196724 kb
Host smart-3689505a-6fad-421d-b66c-7e25f7adc0df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028144090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.4028144090
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.4153735589
Short name T209
Test name
Test status
Simulation time 128324256 ps
CPU time 1.01 seconds
Started Aug 17 05:32:06 PM PDT 24
Finished Aug 17 05:32:07 PM PDT 24
Peak memory 196380 kb
Host smart-dec78484-9f75-462a-89e2-06ea1b5d2d1d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153735589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.4153735589
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.3361735244
Short name T433
Test name
Test status
Simulation time 10513187898 ps
CPU time 111.61 seconds
Started Aug 17 05:32:13 PM PDT 24
Finished Aug 17 05:34:05 PM PDT 24
Peak memory 198408 kb
Host smart-c1ed86c6-a7d4-4a18-b25a-951a419924f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361735244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.3361735244
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_alert_test.2017597911
Short name T438
Test name
Test status
Simulation time 55371676 ps
CPU time 0.57 seconds
Started Aug 17 05:32:27 PM PDT 24
Finished Aug 17 05:32:28 PM PDT 24
Peak memory 194676 kb
Host smart-5a9f5f26-a3d2-451b-8be7-bac43b835f0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017597911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.2017597911
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.375749435
Short name T358
Test name
Test status
Simulation time 41845090 ps
CPU time 0.9 seconds
Started Aug 17 05:32:19 PM PDT 24
Finished Aug 17 05:32:20 PM PDT 24
Peak memory 196228 kb
Host smart-9a67ed79-793d-4770-8e64-2255162f54b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375749435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.375749435
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.4044893865
Short name T644
Test name
Test status
Simulation time 391972841 ps
CPU time 16.79 seconds
Started Aug 17 05:32:17 PM PDT 24
Finished Aug 17 05:32:34 PM PDT 24
Peak memory 197212 kb
Host smart-df13f504-7ee2-4d24-af73-0f5f55881e09
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044893865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.4044893865
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.2915876429
Short name T515
Test name
Test status
Simulation time 254092139 ps
CPU time 1.24 seconds
Started Aug 17 05:32:19 PM PDT 24
Finished Aug 17 05:32:20 PM PDT 24
Peak memory 197160 kb
Host smart-31d45789-456a-4c70-9397-391ede2eb776
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915876429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.2915876429
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.1259563803
Short name T307
Test name
Test status
Simulation time 83565269 ps
CPU time 3.11 seconds
Started Aug 17 05:32:18 PM PDT 24
Finished Aug 17 05:32:21 PM PDT 24
Peak memory 198092 kb
Host smart-a757f47d-1694-45a3-a9a9-98fa1937be45
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259563803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.1259563803
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.1676307326
Short name T255
Test name
Test status
Simulation time 566504414 ps
CPU time 3 seconds
Started Aug 17 05:32:16 PM PDT 24
Finished Aug 17 05:32:20 PM PDT 24
Peak memory 197180 kb
Host smart-2fe68bd3-8e04-4334-8e2d-76f5ef7721c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676307326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
1676307326
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.3024627052
Short name T169
Test name
Test status
Simulation time 60868930 ps
CPU time 1.26 seconds
Started Aug 17 05:32:18 PM PDT 24
Finished Aug 17 05:32:19 PM PDT 24
Peak memory 197172 kb
Host smart-7d2528e9-57dc-464f-a256-3b57bc3a062a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024627052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.3024627052
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.2270639457
Short name T516
Test name
Test status
Simulation time 52051797 ps
CPU time 1.03 seconds
Started Aug 17 05:32:19 PM PDT 24
Finished Aug 17 05:32:20 PM PDT 24
Peak memory 196100 kb
Host smart-3ebdc721-02ca-49ce-8e7d-4eac61cdff74
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270639457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.2270639457
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.376104538
Short name T441
Test name
Test status
Simulation time 139254211 ps
CPU time 4.7 seconds
Started Aug 17 05:32:17 PM PDT 24
Finished Aug 17 05:32:22 PM PDT 24
Peak memory 198168 kb
Host smart-4b534e2f-a7c3-41c6-9f88-4c8cbc0aeb5f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376104538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand
om_long_reg_writes_reg_reads.376104538
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.682877269
Short name T50
Test name
Test status
Simulation time 323258520 ps
CPU time 0.94 seconds
Started Aug 17 05:32:27 PM PDT 24
Finished Aug 17 05:32:28 PM PDT 24
Peak memory 214096 kb
Host smart-d2071820-2f38-4340-b8df-fac53626bd4f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682877269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.682877269
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.3445103070
Short name T207
Test name
Test status
Simulation time 70371775 ps
CPU time 0.93 seconds
Started Aug 17 05:32:19 PM PDT 24
Finished Aug 17 05:32:20 PM PDT 24
Peak memory 196544 kb
Host smart-496f6712-82d1-4eae-a101-605a98b5d5c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445103070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.3445103070
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.3374646973
Short name T142
Test name
Test status
Simulation time 155895256 ps
CPU time 1.35 seconds
Started Aug 17 05:32:16 PM PDT 24
Finished Aug 17 05:32:18 PM PDT 24
Peak memory 196448 kb
Host smart-73544db7-bee6-47bc-972c-c5e9e4a9ff92
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374646973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.3374646973
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.1349363078
Short name T153
Test name
Test status
Simulation time 3010781701 ps
CPU time 84.14 seconds
Started Aug 17 05:32:26 PM PDT 24
Finished Aug 17 05:33:50 PM PDT 24
Peak memory 198232 kb
Host smart-976480a4-f328-4717-b501-ab6446adf480
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349363078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g
pio_stress_all.1349363078
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_stress_all_with_rand_reset.2773612542
Short name T60
Test name
Test status
Simulation time 2060302614 ps
CPU time 66.57 seconds
Started Aug 17 05:32:24 PM PDT 24
Finished Aug 17 05:33:30 PM PDT 24
Peak memory 198424 kb
Host smart-394a840a-529d-47b5-8b1c-820ecdc76e94
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2773612542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_stress_all_with_rand_reset.2773612542
Directory /workspace/1.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.gpio_alert_test.3063088333
Short name T435
Test name
Test status
Simulation time 21214648 ps
CPU time 0.57 seconds
Started Aug 17 05:33:23 PM PDT 24
Finished Aug 17 05:33:24 PM PDT 24
Peak memory 194796 kb
Host smart-d2b6aff8-0d94-42f5-99f2-aec916dbbb90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063088333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.3063088333
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.347201548
Short name T572
Test name
Test status
Simulation time 66495482 ps
CPU time 0.71 seconds
Started Aug 17 05:33:21 PM PDT 24
Finished Aug 17 05:33:22 PM PDT 24
Peak memory 195440 kb
Host smart-b99bee39-b668-4fda-bad5-67f83ec69e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347201548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.347201548
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.3275392389
Short name T665
Test name
Test status
Simulation time 429620231 ps
CPU time 20.64 seconds
Started Aug 17 05:33:24 PM PDT 24
Finished Aug 17 05:33:45 PM PDT 24
Peak memory 196760 kb
Host smart-526aa8b6-3011-4630-bffe-8c59e4b7afb4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275392389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.3275392389
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.2826842282
Short name T698
Test name
Test status
Simulation time 137701400 ps
CPU time 0.73 seconds
Started Aug 17 05:33:22 PM PDT 24
Finished Aug 17 05:33:23 PM PDT 24
Peak memory 196688 kb
Host smart-84b4e71b-8bb7-42fb-8fa5-014b6dbc8a63
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826842282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.2826842282
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.3603173827
Short name T134
Test name
Test status
Simulation time 68408741 ps
CPU time 1.12 seconds
Started Aug 17 05:33:23 PM PDT 24
Finished Aug 17 05:33:24 PM PDT 24
Peak memory 195884 kb
Host smart-9ed5c35a-ade9-46ca-862f-9fdc5844d214
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603173827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.3603173827
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.47882323
Short name T651
Test name
Test status
Simulation time 226966992 ps
CPU time 2.12 seconds
Started Aug 17 05:33:21 PM PDT 24
Finished Aug 17 05:33:24 PM PDT 24
Peak memory 196604 kb
Host smart-45190d38-ba53-4cd8-98f5-71b93683a73f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47882323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 10.gpio_intr_with_filter_rand_intr_event.47882323
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.1277718170
Short name T478
Test name
Test status
Simulation time 49907607 ps
CPU time 1.46 seconds
Started Aug 17 05:33:22 PM PDT 24
Finished Aug 17 05:33:24 PM PDT 24
Peak memory 196532 kb
Host smart-3707f507-b82b-4be2-9a8c-1fb806897463
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277718170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.1277718170
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.988350499
Short name T172
Test name
Test status
Simulation time 100469527 ps
CPU time 1.02 seconds
Started Aug 17 05:33:23 PM PDT 24
Finished Aug 17 05:33:24 PM PDT 24
Peak memory 196188 kb
Host smart-ab942c4e-8053-4d89-9709-ec97bd61d6c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988350499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.988350499
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.3905482144
Short name T703
Test name
Test status
Simulation time 28420551 ps
CPU time 1.02 seconds
Started Aug 17 05:33:24 PM PDT 24
Finished Aug 17 05:33:25 PM PDT 24
Peak memory 195972 kb
Host smart-4e4b1ee7-83a5-416e-8223-6256a8a3ea07
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905482144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.3905482144
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.1985006317
Short name T585
Test name
Test status
Simulation time 381704593 ps
CPU time 6.11 seconds
Started Aug 17 05:33:24 PM PDT 24
Finished Aug 17 05:33:30 PM PDT 24
Peak memory 197988 kb
Host smart-9616b0d5-890c-4ba3-9ef9-714bf25f5f00
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985006317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.1985006317
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.327463095
Short name T474
Test name
Test status
Simulation time 591532934 ps
CPU time 1.13 seconds
Started Aug 17 05:33:25 PM PDT 24
Finished Aug 17 05:33:27 PM PDT 24
Peak memory 195688 kb
Host smart-c937a959-211d-4bb0-8f15-6f32120e2137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327463095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.327463095
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.1586381775
Short name T140
Test name
Test status
Simulation time 103711120 ps
CPU time 1 seconds
Started Aug 17 05:33:23 PM PDT 24
Finished Aug 17 05:33:24 PM PDT 24
Peak memory 196612 kb
Host smart-03b13aab-4fd5-495c-aea7-5260ea4f08ea
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586381775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.1586381775
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.4288995051
Short name T65
Test name
Test status
Simulation time 3632065917 ps
CPU time 81.55 seconds
Started Aug 17 05:33:21 PM PDT 24
Finished Aug 17 05:34:43 PM PDT 24
Peak memory 198324 kb
Host smart-78bda08c-9785-49c6-a8a7-38fc62fe6c11
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288995051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.4288995051
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_alert_test.769196615
Short name T470
Test name
Test status
Simulation time 47883106 ps
CPU time 0.55 seconds
Started Aug 17 05:33:30 PM PDT 24
Finished Aug 17 05:33:31 PM PDT 24
Peak memory 194200 kb
Host smart-92926c69-a168-43bb-8b5f-1d4a67404008
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769196615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.769196615
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.3596795656
Short name T504
Test name
Test status
Simulation time 16267593 ps
CPU time 0.63 seconds
Started Aug 17 05:33:30 PM PDT 24
Finished Aug 17 05:33:31 PM PDT 24
Peak memory 193924 kb
Host smart-5c19a8ee-5ec3-4ff0-a760-3a81521d6b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596795656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.3596795656
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.4068478907
Short name T322
Test name
Test status
Simulation time 297994381 ps
CPU time 3.75 seconds
Started Aug 17 05:33:30 PM PDT 24
Finished Aug 17 05:33:34 PM PDT 24
Peak memory 196116 kb
Host smart-cf0a60fb-4f28-41b0-b9e1-122f8d3eac88
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068478907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.4068478907
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.1348787265
Short name T701
Test name
Test status
Simulation time 32437625 ps
CPU time 0.71 seconds
Started Aug 17 05:33:28 PM PDT 24
Finished Aug 17 05:33:29 PM PDT 24
Peak memory 194688 kb
Host smart-1b94b946-d4aa-48a6-9d2a-ccc4d9e735d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348787265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.1348787265
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.3478973052
Short name T453
Test name
Test status
Simulation time 591413329 ps
CPU time 1.16 seconds
Started Aug 17 05:33:30 PM PDT 24
Finished Aug 17 05:33:31 PM PDT 24
Peak memory 195940 kb
Host smart-258d4bcb-17c0-43c2-bf5f-8f93a64ed564
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478973052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.3478973052
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.2260079675
Short name T253
Test name
Test status
Simulation time 44565690 ps
CPU time 1.06 seconds
Started Aug 17 05:33:31 PM PDT 24
Finished Aug 17 05:33:33 PM PDT 24
Peak memory 197148 kb
Host smart-0f572ef1-960f-4035-ace3-487bd39054f3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260079675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.2260079675
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.2031853805
Short name T511
Test name
Test status
Simulation time 289522326 ps
CPU time 2.92 seconds
Started Aug 17 05:33:31 PM PDT 24
Finished Aug 17 05:33:34 PM PDT 24
Peak memory 198232 kb
Host smart-11f556cc-8a61-44d6-b3ab-8bef1d172986
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031853805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.2031853805
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.126415340
Short name T217
Test name
Test status
Simulation time 185803764 ps
CPU time 1 seconds
Started Aug 17 05:33:23 PM PDT 24
Finished Aug 17 05:33:24 PM PDT 24
Peak memory 196664 kb
Host smart-3c5af501-669b-4c1a-b0dc-681c69919176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126415340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.126415340
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.577722299
Short name T354
Test name
Test status
Simulation time 35448966 ps
CPU time 1.14 seconds
Started Aug 17 05:33:24 PM PDT 24
Finished Aug 17 05:33:26 PM PDT 24
Peak memory 196740 kb
Host smart-c9e6c224-ae8f-4d9d-899b-1378c1a53dc4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577722299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullup
_pulldown.577722299
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.2142282085
Short name T637
Test name
Test status
Simulation time 62577060 ps
CPU time 2.93 seconds
Started Aug 17 05:33:32 PM PDT 24
Finished Aug 17 05:33:35 PM PDT 24
Peak memory 198200 kb
Host smart-da7e6b97-8c05-486b-a3cf-fafde313a044
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142282085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.2142282085
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.3224631360
Short name T340
Test name
Test status
Simulation time 51655339 ps
CPU time 1.03 seconds
Started Aug 17 05:33:21 PM PDT 24
Finished Aug 17 05:33:22 PM PDT 24
Peak memory 195864 kb
Host smart-e0cdc0c4-164f-48db-82ae-00a79d208075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224631360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.3224631360
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.1494248059
Short name T223
Test name
Test status
Simulation time 48785733 ps
CPU time 1.32 seconds
Started Aug 17 05:33:23 PM PDT 24
Finished Aug 17 05:33:25 PM PDT 24
Peak memory 195636 kb
Host smart-377b73fe-3fc0-4784-852e-efdd4a12397b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494248059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.1494248059
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.4146357179
Short name T445
Test name
Test status
Simulation time 5730444842 ps
CPU time 66.07 seconds
Started Aug 17 05:33:32 PM PDT 24
Finished Aug 17 05:34:39 PM PDT 24
Peak memory 198288 kb
Host smart-a04db607-fd27-47fd-b1e6-4fe9c6742186
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146357179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.4146357179
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_alert_test.3330100628
Short name T227
Test name
Test status
Simulation time 34674416 ps
CPU time 0.58 seconds
Started Aug 17 05:33:39 PM PDT 24
Finished Aug 17 05:33:40 PM PDT 24
Peak memory 194284 kb
Host smart-56141623-52a4-47d6-9e15-2c822918f84f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330100628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.3330100628
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.3846436225
Short name T336
Test name
Test status
Simulation time 63339088 ps
CPU time 0.63 seconds
Started Aug 17 05:33:29 PM PDT 24
Finished Aug 17 05:33:30 PM PDT 24
Peak memory 194940 kb
Host smart-b38fccd5-e783-4ab6-953c-3f2ea08d5eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846436225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.3846436225
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.2875700506
Short name T693
Test name
Test status
Simulation time 468618689 ps
CPU time 7.14 seconds
Started Aug 17 05:33:31 PM PDT 24
Finished Aug 17 05:33:39 PM PDT 24
Peak memory 198112 kb
Host smart-45366faf-58ef-4ee2-b09b-b047f28d99a6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875700506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.2875700506
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.3322923048
Short name T551
Test name
Test status
Simulation time 98273785 ps
CPU time 0.7 seconds
Started Aug 17 05:33:34 PM PDT 24
Finished Aug 17 05:33:35 PM PDT 24
Peak memory 194804 kb
Host smart-985f4885-769f-475f-95da-ce80154fb34b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322923048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.3322923048
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.847405924
Short name T22
Test name
Test status
Simulation time 59231432 ps
CPU time 1.07 seconds
Started Aug 17 05:33:32 PM PDT 24
Finished Aug 17 05:33:33 PM PDT 24
Peak memory 196200 kb
Host smart-2ccfe3db-e28b-4724-be13-68d3a57a7315
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847405924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.847405924
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.2360470320
Short name T305
Test name
Test status
Simulation time 48169589 ps
CPU time 1.01 seconds
Started Aug 17 05:33:30 PM PDT 24
Finished Aug 17 05:33:31 PM PDT 24
Peak memory 196272 kb
Host smart-e5b76b90-a0b7-4e32-9605-1f38f39d2509
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360470320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.2360470320
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.4092324943
Short name T133
Test name
Test status
Simulation time 135769911 ps
CPU time 1.12 seconds
Started Aug 17 05:33:33 PM PDT 24
Finished Aug 17 05:33:34 PM PDT 24
Peak memory 195752 kb
Host smart-8e62a337-c6f2-45ef-a052-199e3ef7e857
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092324943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.4092324943
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.18393107
Short name T425
Test name
Test status
Simulation time 127864045 ps
CPU time 1.27 seconds
Started Aug 17 05:33:30 PM PDT 24
Finished Aug 17 05:33:31 PM PDT 24
Peak memory 196740 kb
Host smart-78f22217-8cc5-4471-a9de-ee5fa2b67b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18393107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.18393107
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.3872501526
Short name T214
Test name
Test status
Simulation time 168328023 ps
CPU time 1.09 seconds
Started Aug 17 05:33:30 PM PDT 24
Finished Aug 17 05:33:31 PM PDT 24
Peak memory 197180 kb
Host smart-3ae78ad4-f694-4306-a7a7-33c3bbf4b36a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872501526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.3872501526
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.2936458710
Short name T628
Test name
Test status
Simulation time 80310961 ps
CPU time 3.79 seconds
Started Aug 17 05:33:30 PM PDT 24
Finished Aug 17 05:33:33 PM PDT 24
Peak memory 198156 kb
Host smart-4d7a3747-436a-4937-b13e-a313da7a7dfa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936458710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.2936458710
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.469951549
Short name T655
Test name
Test status
Simulation time 40888554 ps
CPU time 1.14 seconds
Started Aug 17 05:33:31 PM PDT 24
Finished Aug 17 05:33:32 PM PDT 24
Peak memory 196432 kb
Host smart-5d17e30b-c527-4577-85a0-9f81e2ba8771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469951549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.469951549
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.2015466180
Short name T614
Test name
Test status
Simulation time 27881561 ps
CPU time 0.82 seconds
Started Aug 17 05:33:30 PM PDT 24
Finished Aug 17 05:33:31 PM PDT 24
Peak memory 196488 kb
Host smart-ef6e203a-f0d2-4969-b075-eb5b5c17e8c6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015466180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.2015466180
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.2190733451
Short name T348
Test name
Test status
Simulation time 7131020762 ps
CPU time 99.7 seconds
Started Aug 17 05:33:31 PM PDT 24
Finished Aug 17 05:35:11 PM PDT 24
Peak memory 198272 kb
Host smart-935d981d-de93-438d-a56c-24f03dcc036a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190733451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.2190733451
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_stress_all_with_rand_reset.3788741
Short name T673
Test name
Test status
Simulation time 39417964743 ps
CPU time 234.3 seconds
Started Aug 17 05:33:29 PM PDT 24
Finished Aug 17 05:37:24 PM PDT 24
Peak memory 198552 kb
Host smart-b8606d1a-18bf-4d09-9872-20b0e6d73fa2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3788741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_stress_all_with_rand_reset.3788741
Directory /workspace/12.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.gpio_alert_test.2628723109
Short name T690
Test name
Test status
Simulation time 15136652 ps
CPU time 0.59 seconds
Started Aug 17 05:33:36 PM PDT 24
Finished Aug 17 05:33:37 PM PDT 24
Peak memory 195784 kb
Host smart-be78171e-c2da-4ceb-975f-cee51dc91d54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628723109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.2628723109
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.1902648314
Short name T503
Test name
Test status
Simulation time 53904778 ps
CPU time 0.74 seconds
Started Aug 17 05:33:38 PM PDT 24
Finished Aug 17 05:33:39 PM PDT 24
Peak memory 195312 kb
Host smart-b03a4dcb-5e87-456f-83f5-0c82868d61d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902648314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.1902648314
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.4149272338
Short name T562
Test name
Test status
Simulation time 3868845394 ps
CPU time 21.97 seconds
Started Aug 17 05:33:38 PM PDT 24
Finished Aug 17 05:34:00 PM PDT 24
Peak memory 197224 kb
Host smart-f72c26d8-e7b7-4ac0-b499-5cab24b36d5a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149272338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.4149272338
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.1472935417
Short name T417
Test name
Test status
Simulation time 30778825 ps
CPU time 0.64 seconds
Started Aug 17 05:33:36 PM PDT 24
Finished Aug 17 05:33:37 PM PDT 24
Peak memory 195296 kb
Host smart-c4ad31ef-692a-4d49-ab75-cbf2eb9ab4f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472935417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.1472935417
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.974221722
Short name T559
Test name
Test status
Simulation time 62241897 ps
CPU time 1.19 seconds
Started Aug 17 05:33:38 PM PDT 24
Finished Aug 17 05:33:39 PM PDT 24
Peak memory 196924 kb
Host smart-e67caeb6-5051-4db1-8ca4-3564e294db4c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974221722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.974221722
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.2896890824
Short name T602
Test name
Test status
Simulation time 312551440 ps
CPU time 2.93 seconds
Started Aug 17 05:33:36 PM PDT 24
Finished Aug 17 05:33:39 PM PDT 24
Peak memory 198148 kb
Host smart-e0b7eb3a-dc66-4853-aa18-0c45e9970080
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896890824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.2896890824
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.508583980
Short name T569
Test name
Test status
Simulation time 538449101 ps
CPU time 2.8 seconds
Started Aug 17 05:33:37 PM PDT 24
Finished Aug 17 05:33:40 PM PDT 24
Peak memory 196864 kb
Host smart-ac617e11-1b25-4e18-9d65-27a992e04ab2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508583980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger.
508583980
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.2528843964
Short name T422
Test name
Test status
Simulation time 104745974 ps
CPU time 0.8 seconds
Started Aug 17 05:33:36 PM PDT 24
Finished Aug 17 05:33:37 PM PDT 24
Peak memory 197344 kb
Host smart-5f8b2fb4-8ddd-45d1-a718-818badd682c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528843964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.2528843964
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.1280454073
Short name T374
Test name
Test status
Simulation time 55007265 ps
CPU time 1.14 seconds
Started Aug 17 05:33:39 PM PDT 24
Finished Aug 17 05:33:41 PM PDT 24
Peak memory 196096 kb
Host smart-d191bee4-22f7-470f-afff-6af1a1e818a9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280454073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.1280454073
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.1648488623
Short name T115
Test name
Test status
Simulation time 288920086 ps
CPU time 3.29 seconds
Started Aug 17 05:33:37 PM PDT 24
Finished Aug 17 05:33:40 PM PDT 24
Peak memory 198164 kb
Host smart-5a69190a-3b6c-4cb8-95a0-9d29ccbe1745
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648488623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.1648488623
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.3859608122
Short name T25
Test name
Test status
Simulation time 170860561 ps
CPU time 1.07 seconds
Started Aug 17 05:33:39 PM PDT 24
Finished Aug 17 05:33:40 PM PDT 24
Peak memory 195784 kb
Host smart-65f49244-d7b3-4227-92c4-b3838b76eb8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859608122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.3859608122
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.3489482082
Short name T167
Test name
Test status
Simulation time 72266763 ps
CPU time 1.16 seconds
Started Aug 17 05:33:39 PM PDT 24
Finished Aug 17 05:33:40 PM PDT 24
Peak memory 195640 kb
Host smart-91938bf0-8415-4805-9587-6d11b1c2b1fe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489482082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.3489482082
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.473327511
Short name T306
Test name
Test status
Simulation time 27973388701 ps
CPU time 199.01 seconds
Started Aug 17 05:33:39 PM PDT 24
Finished Aug 17 05:36:58 PM PDT 24
Peak memory 198320 kb
Host smart-29292b22-5411-4dd1-ba02-8da42322b58d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473327511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.g
pio_stress_all.473327511
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_alert_test.1244100512
Short name T321
Test name
Test status
Simulation time 18081668 ps
CPU time 0.57 seconds
Started Aug 17 05:33:45 PM PDT 24
Finished Aug 17 05:33:45 PM PDT 24
Peak memory 194020 kb
Host smart-9166637a-b98d-423d-8fa2-31e57b3b3224
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244100512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.1244100512
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.4168160112
Short name T548
Test name
Test status
Simulation time 15174010 ps
CPU time 0.64 seconds
Started Aug 17 05:33:37 PM PDT 24
Finished Aug 17 05:33:37 PM PDT 24
Peak memory 194120 kb
Host smart-7ca44350-64fb-4177-ae9d-3d6abe7d7a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168160112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.4168160112
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.2474513082
Short name T366
Test name
Test status
Simulation time 1649674880 ps
CPU time 21.17 seconds
Started Aug 17 05:33:46 PM PDT 24
Finished Aug 17 05:34:07 PM PDT 24
Peak memory 196704 kb
Host smart-67b02f38-9311-48b7-8ff6-1d27f2975feb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474513082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.2474513082
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.3263510705
Short name T700
Test name
Test status
Simulation time 126308285 ps
CPU time 0.73 seconds
Started Aug 17 05:33:49 PM PDT 24
Finished Aug 17 05:33:50 PM PDT 24
Peak memory 196532 kb
Host smart-129d06df-57e3-4f04-806a-09c4c48c2f6e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263510705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.3263510705
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.227103355
Short name T220
Test name
Test status
Simulation time 49591661 ps
CPU time 0.85 seconds
Started Aug 17 05:33:45 PM PDT 24
Finished Aug 17 05:33:46 PM PDT 24
Peak memory 196812 kb
Host smart-916b6f51-912b-4960-90ec-af77d4aaca02
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227103355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.227103355
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.1439862128
Short name T459
Test name
Test status
Simulation time 131998825 ps
CPU time 3.4 seconds
Started Aug 17 05:33:45 PM PDT 24
Finished Aug 17 05:33:49 PM PDT 24
Peak memory 198236 kb
Host smart-b8eda682-30d6-4c5e-8a6a-c350fa3f1bd9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439862128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.1439862128
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.741897290
Short name T430
Test name
Test status
Simulation time 249660310 ps
CPU time 1.19 seconds
Started Aug 17 05:33:46 PM PDT 24
Finished Aug 17 05:33:48 PM PDT 24
Peak memory 196480 kb
Host smart-123e7b25-b65d-48b9-afe5-135e0414148f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741897290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger.
741897290
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.2499494255
Short name T177
Test name
Test status
Simulation time 52438889 ps
CPU time 1.16 seconds
Started Aug 17 05:33:36 PM PDT 24
Finished Aug 17 05:33:38 PM PDT 24
Peak memory 196116 kb
Host smart-29442e44-84a2-40b9-88b2-c15331b9df10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499494255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.2499494255
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.3461244368
Short name T671
Test name
Test status
Simulation time 39989832 ps
CPU time 1.02 seconds
Started Aug 17 05:33:40 PM PDT 24
Finished Aug 17 05:33:41 PM PDT 24
Peak memory 196668 kb
Host smart-b8237617-4b79-4087-935d-75a57fc677c4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461244368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.3461244368
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.3657121940
Short name T7
Test name
Test status
Simulation time 2207642994 ps
CPU time 5.88 seconds
Started Aug 17 05:33:45 PM PDT 24
Finished Aug 17 05:33:51 PM PDT 24
Peak memory 198264 kb
Host smart-e1579726-96db-4bb6-a65f-e4bb05abce07
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657121940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.3657121940
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.151400231
Short name T267
Test name
Test status
Simulation time 70173654 ps
CPU time 1.09 seconds
Started Aug 17 05:33:38 PM PDT 24
Finished Aug 17 05:33:39 PM PDT 24
Peak memory 195692 kb
Host smart-70391e6c-9b93-4597-ac69-7ea1fe0634ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151400231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.151400231
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.3789710617
Short name T103
Test name
Test status
Simulation time 55874438 ps
CPU time 1.34 seconds
Started Aug 17 05:33:36 PM PDT 24
Finished Aug 17 05:33:37 PM PDT 24
Peak memory 198120 kb
Host smart-c2823bb0-9e7b-4970-a648-1692dde45136
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789710617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.3789710617
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.2994987061
Short name T245
Test name
Test status
Simulation time 9605851301 ps
CPU time 49.29 seconds
Started Aug 17 05:33:47 PM PDT 24
Finished Aug 17 05:34:36 PM PDT 24
Peak memory 198256 kb
Host smart-7e473865-96af-437a-bece-dd1476277bce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994987061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.2994987061
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_alert_test.1309098092
Short name T649
Test name
Test status
Simulation time 37948788 ps
CPU time 0.55 seconds
Started Aug 17 05:33:45 PM PDT 24
Finished Aug 17 05:33:45 PM PDT 24
Peak memory 193996 kb
Host smart-5eea6b0a-906c-4536-97a4-b8969c60fc1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309098092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.1309098092
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.347143887
Short name T469
Test name
Test status
Simulation time 21124212 ps
CPU time 0.68 seconds
Started Aug 17 05:33:47 PM PDT 24
Finished Aug 17 05:33:48 PM PDT 24
Peak memory 194184 kb
Host smart-106a99d0-a2e0-474f-ad8d-2d88b7d2262f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347143887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.347143887
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.3519209199
Short name T448
Test name
Test status
Simulation time 82215040 ps
CPU time 4.16 seconds
Started Aug 17 05:33:45 PM PDT 24
Finished Aug 17 05:33:49 PM PDT 24
Peak memory 196040 kb
Host smart-3f147d73-de26-4b16-8f3a-ce729257b761
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519209199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.3519209199
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.969100348
Short name T475
Test name
Test status
Simulation time 469687950 ps
CPU time 0.86 seconds
Started Aug 17 05:33:45 PM PDT 24
Finished Aug 17 05:33:46 PM PDT 24
Peak memory 197120 kb
Host smart-e299fab1-271e-45d0-a8cc-1a498be42c12
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969100348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.969100348
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.1189970786
Short name T409
Test name
Test status
Simulation time 264227468 ps
CPU time 0.94 seconds
Started Aug 17 05:33:45 PM PDT 24
Finished Aug 17 05:33:46 PM PDT 24
Peak memory 196168 kb
Host smart-ad7ff6de-bdcd-45c3-be76-dd61faecc376
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189970786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.1189970786
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.1212815640
Short name T251
Test name
Test status
Simulation time 672032392 ps
CPU time 2.93 seconds
Started Aug 17 05:33:45 PM PDT 24
Finished Aug 17 05:33:48 PM PDT 24
Peak memory 198104 kb
Host smart-3b55fac9-7722-4924-a0e4-912063132ec2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212815640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.1212815640
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.2978561419
Short name T375
Test name
Test status
Simulation time 28556866 ps
CPU time 1 seconds
Started Aug 17 05:33:47 PM PDT 24
Finished Aug 17 05:33:48 PM PDT 24
Peak memory 195208 kb
Host smart-cf8aea99-e477-4c42-9870-8068e2c9275c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978561419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.2978561419
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.1075551204
Short name T190
Test name
Test status
Simulation time 46184651 ps
CPU time 0.67 seconds
Started Aug 17 05:33:47 PM PDT 24
Finished Aug 17 05:33:48 PM PDT 24
Peak memory 194368 kb
Host smart-aaf51847-f7ce-45d9-84da-ac7d9040b43d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075551204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.1075551204
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.3507301257
Short name T534
Test name
Test status
Simulation time 123502873 ps
CPU time 0.87 seconds
Started Aug 17 05:33:46 PM PDT 24
Finished Aug 17 05:33:47 PM PDT 24
Peak memory 195940 kb
Host smart-8382bfae-f51c-411f-ac03-2b8641fd1a2b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507301257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.3507301257
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.2843333954
Short name T27
Test name
Test status
Simulation time 286039385 ps
CPU time 1.16 seconds
Started Aug 17 05:33:46 PM PDT 24
Finished Aug 17 05:33:47 PM PDT 24
Peak memory 198076 kb
Host smart-06bc619c-d252-41f5-a767-3acedb8480fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843333954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.2843333954
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.1491159860
Short name T254
Test name
Test status
Simulation time 198158871 ps
CPU time 0.98 seconds
Started Aug 17 05:33:50 PM PDT 24
Finished Aug 17 05:33:51 PM PDT 24
Peak memory 195960 kb
Host smart-17b135e6-02c2-4112-91e9-595c4664e1a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491159860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.1491159860
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.2452888664
Short name T99
Test name
Test status
Simulation time 165794403 ps
CPU time 1.15 seconds
Started Aug 17 05:33:47 PM PDT 24
Finished Aug 17 05:33:49 PM PDT 24
Peak memory 196716 kb
Host smart-757a6e8f-9313-4d2d-8a21-b062d9a600c9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452888664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.2452888664
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.3868191577
Short name T663
Test name
Test status
Simulation time 24713038664 ps
CPU time 85.85 seconds
Started Aug 17 05:33:46 PM PDT 24
Finished Aug 17 05:35:12 PM PDT 24
Peak memory 198392 kb
Host smart-e74165a0-9373-49e3-8102-d19f6dc8e67f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868191577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.3868191577
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_alert_test.963399492
Short name T385
Test name
Test status
Simulation time 13758589 ps
CPU time 0.61 seconds
Started Aug 17 05:33:53 PM PDT 24
Finished Aug 17 05:33:54 PM PDT 24
Peak memory 194024 kb
Host smart-5961d14a-f647-43bb-90aa-ee93e5c632db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963399492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.963399492
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.8230760
Short name T215
Test name
Test status
Simulation time 361178496 ps
CPU time 0.88 seconds
Started Aug 17 05:33:46 PM PDT 24
Finished Aug 17 05:33:47 PM PDT 24
Peak memory 195996 kb
Host smart-b54867de-10e9-4ec6-ba05-738f36b59872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8230760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.8230760
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.2353420430
Short name T389
Test name
Test status
Simulation time 1562397403 ps
CPU time 12.49 seconds
Started Aug 17 05:33:46 PM PDT 24
Finished Aug 17 05:33:59 PM PDT 24
Peak memory 198208 kb
Host smart-9443b313-132d-47c7-989a-3f010b94406f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353420430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.2353420430
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.2216725345
Short name T370
Test name
Test status
Simulation time 72304788 ps
CPU time 0.94 seconds
Started Aug 17 05:33:45 PM PDT 24
Finished Aug 17 05:33:46 PM PDT 24
Peak memory 196660 kb
Host smart-9e2fba98-e6f2-457e-a17f-9df4a18917c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216725345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.2216725345
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.337958846
Short name T319
Test name
Test status
Simulation time 165650899 ps
CPU time 0.94 seconds
Started Aug 17 05:33:47 PM PDT 24
Finished Aug 17 05:33:48 PM PDT 24
Peak memory 195764 kb
Host smart-b62d1ec9-51e3-478b-82dd-5c23c063ffb7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337958846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.337958846
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.3137934719
Short name T493
Test name
Test status
Simulation time 178419087 ps
CPU time 3.47 seconds
Started Aug 17 05:33:46 PM PDT 24
Finished Aug 17 05:33:50 PM PDT 24
Peak memory 198244 kb
Host smart-51ccbfbe-e5c0-4486-a9e4-dd12b3203235
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137934719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.3137934719
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.1846446367
Short name T598
Test name
Test status
Simulation time 349539405 ps
CPU time 1.97 seconds
Started Aug 17 05:33:45 PM PDT 24
Finished Aug 17 05:33:47 PM PDT 24
Peak memory 196404 kb
Host smart-fbe65022-1f37-4b9e-8aa9-962b3f51a144
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846446367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.1846446367
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.2809698854
Short name T399
Test name
Test status
Simulation time 727208024 ps
CPU time 1.16 seconds
Started Aug 17 05:33:45 PM PDT 24
Finished Aug 17 05:33:47 PM PDT 24
Peak memory 198224 kb
Host smart-a6e59fdf-40c1-436d-a9fe-207e72fc1c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809698854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.2809698854
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.2500994980
Short name T276
Test name
Test status
Simulation time 83555313 ps
CPU time 1.01 seconds
Started Aug 17 05:33:46 PM PDT 24
Finished Aug 17 05:33:47 PM PDT 24
Peak memory 196044 kb
Host smart-eb0b91c2-6126-4103-a9dc-a29fe3a75142
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500994980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.2500994980
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.3573360852
Short name T326
Test name
Test status
Simulation time 196730069 ps
CPU time 2.74 seconds
Started Aug 17 05:33:45 PM PDT 24
Finished Aug 17 05:33:47 PM PDT 24
Peak memory 198060 kb
Host smart-fdbb3f4e-ca5a-474f-9855-f20ca5002360
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573360852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.3573360852
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.2758729502
Short name T697
Test name
Test status
Simulation time 64741712 ps
CPU time 1.14 seconds
Started Aug 17 05:33:47 PM PDT 24
Finished Aug 17 05:33:48 PM PDT 24
Peak memory 196696 kb
Host smart-eb4b2444-2125-41e5-b36f-9d2e40e45bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758729502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.2758729502
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.853161630
Short name T62
Test name
Test status
Simulation time 69176720 ps
CPU time 1.09 seconds
Started Aug 17 05:33:46 PM PDT 24
Finished Aug 17 05:33:47 PM PDT 24
Peak memory 195676 kb
Host smart-1212d0bd-8cd1-42de-a7f1-45ce38cd03cd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853161630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.853161630
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.3566498482
Short name T200
Test name
Test status
Simulation time 3010025215 ps
CPU time 80.81 seconds
Started Aug 17 05:33:45 PM PDT 24
Finished Aug 17 05:35:06 PM PDT 24
Peak memory 198360 kb
Host smart-a7f66f58-d6f4-466c-b1b7-4f6255ff8314
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566498482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.3566498482
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.3251034347
Short name T188
Test name
Test status
Simulation time 44831013 ps
CPU time 0.67 seconds
Started Aug 17 05:33:54 PM PDT 24
Finished Aug 17 05:33:55 PM PDT 24
Peak memory 194984 kb
Host smart-fe2f5d5e-9a32-4d1e-8561-ed0a303c7485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251034347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.3251034347
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.700232002
Short name T561
Test name
Test status
Simulation time 4013586277 ps
CPU time 16.73 seconds
Started Aug 17 05:33:54 PM PDT 24
Finished Aug 17 05:34:11 PM PDT 24
Peak memory 197848 kb
Host smart-4b3488fe-f3fc-4bae-a628-cef61828f1a7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700232002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stres
s.700232002
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.3793382861
Short name T553
Test name
Test status
Simulation time 344389104 ps
CPU time 0.99 seconds
Started Aug 17 05:33:51 PM PDT 24
Finished Aug 17 05:33:52 PM PDT 24
Peak memory 196640 kb
Host smart-378d3d50-f0cb-4f2e-9401-ec8e7fc67578
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793382861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.3793382861
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.1443935525
Short name T229
Test name
Test status
Simulation time 52658602 ps
CPU time 0.95 seconds
Started Aug 17 05:33:54 PM PDT 24
Finished Aug 17 05:33:55 PM PDT 24
Peak memory 195900 kb
Host smart-99390df7-49b6-434a-96de-2b96f83b9956
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443935525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.1443935525
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.1123437097
Short name T687
Test name
Test status
Simulation time 314743358 ps
CPU time 3.12 seconds
Started Aug 17 05:33:52 PM PDT 24
Finished Aug 17 05:33:56 PM PDT 24
Peak memory 198112 kb
Host smart-8269a6f4-2d68-43dd-a7f1-790fefcd8b61
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123437097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.1123437097
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.1249118187
Short name T487
Test name
Test status
Simulation time 490976006 ps
CPU time 2.82 seconds
Started Aug 17 05:33:54 PM PDT 24
Finished Aug 17 05:33:56 PM PDT 24
Peak memory 198224 kb
Host smart-21fcfa1d-43d3-4ef0-b45d-4f1d2d13607c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249118187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger
.1249118187
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.2564620208
Short name T110
Test name
Test status
Simulation time 204160573 ps
CPU time 1.32 seconds
Started Aug 17 05:33:52 PM PDT 24
Finished Aug 17 05:33:54 PM PDT 24
Peak memory 197180 kb
Host smart-90280310-131e-4a48-b98a-a57154a1c8ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564620208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.2564620208
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.3047650721
Short name T596
Test name
Test status
Simulation time 72588300 ps
CPU time 1.27 seconds
Started Aug 17 05:33:54 PM PDT 24
Finished Aug 17 05:33:55 PM PDT 24
Peak memory 197204 kb
Host smart-be982e16-bd57-4616-bd04-29e58061dbdc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047650721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.3047650721
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.1875471750
Short name T675
Test name
Test status
Simulation time 233237173 ps
CPU time 3.68 seconds
Started Aug 17 05:33:52 PM PDT 24
Finished Aug 17 05:33:56 PM PDT 24
Peak memory 198060 kb
Host smart-01afcb17-a299-4455-bd63-cf10f71e30f5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875471750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.1875471750
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.3831435073
Short name T709
Test name
Test status
Simulation time 87446288 ps
CPU time 0.93 seconds
Started Aug 17 05:33:53 PM PDT 24
Finished Aug 17 05:33:54 PM PDT 24
Peak memory 196376 kb
Host smart-50f86ed6-4931-4781-998d-ce2ac401a2be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831435073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.3831435073
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.2153070585
Short name T320
Test name
Test status
Simulation time 45558829 ps
CPU time 0.93 seconds
Started Aug 17 05:33:54 PM PDT 24
Finished Aug 17 05:33:55 PM PDT 24
Peak memory 196308 kb
Host smart-0c5047e6-35c3-4c30-b627-58e4ca5e10b9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153070585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.2153070585
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.1224436221
Short name T21
Test name
Test status
Simulation time 31571532875 ps
CPU time 187.88 seconds
Started Aug 17 05:33:56 PM PDT 24
Finished Aug 17 05:37:04 PM PDT 24
Peak memory 198328 kb
Host smart-cd2c980e-13d9-4b65-ab66-096bbf1dd306
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224436221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.1224436221
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_alert_test.4055470998
Short name T635
Test name
Test status
Simulation time 30082017 ps
CPU time 0.57 seconds
Started Aug 17 05:34:00 PM PDT 24
Finished Aug 17 05:34:01 PM PDT 24
Peak memory 194020 kb
Host smart-9b10bd6e-c4b0-4404-abd2-1b36549985cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055470998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.4055470998
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.3621979452
Short name T337
Test name
Test status
Simulation time 39889158 ps
CPU time 0.87 seconds
Started Aug 17 05:33:56 PM PDT 24
Finished Aug 17 05:33:57 PM PDT 24
Peak memory 196464 kb
Host smart-2cfbf908-c777-406e-9d4e-eaf93e677fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621979452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.3621979452
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.2419645343
Short name T632
Test name
Test status
Simulation time 1106130467 ps
CPU time 16.94 seconds
Started Aug 17 05:33:52 PM PDT 24
Finished Aug 17 05:34:09 PM PDT 24
Peak memory 195692 kb
Host smart-21997bb3-4d95-4cef-bc29-3f6e432d835e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419645343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.2419645343
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.285644806
Short name T293
Test name
Test status
Simulation time 251989683 ps
CPU time 0.89 seconds
Started Aug 17 05:34:00 PM PDT 24
Finished Aug 17 05:34:01 PM PDT 24
Peak memory 197372 kb
Host smart-5d3b41eb-5b2e-4cc5-a796-22f88c2f5348
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285644806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.285644806
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.2911122303
Short name T646
Test name
Test status
Simulation time 176325195 ps
CPU time 0.91 seconds
Started Aug 17 05:33:52 PM PDT 24
Finished Aug 17 05:33:53 PM PDT 24
Peak memory 196224 kb
Host smart-8269541e-483f-47b0-be87-5e7c64b7ee5a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911122303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.2911122303
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.3537080645
Short name T260
Test name
Test status
Simulation time 602475365 ps
CPU time 2.66 seconds
Started Aug 17 05:33:55 PM PDT 24
Finished Aug 17 05:33:58 PM PDT 24
Peak memory 196572 kb
Host smart-6fe688a5-6fc8-46da-a80c-b03d61c30e6a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537080645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.3537080645
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.1720278779
Short name T532
Test name
Test status
Simulation time 209646963 ps
CPU time 1.58 seconds
Started Aug 17 05:33:51 PM PDT 24
Finished Aug 17 05:33:53 PM PDT 24
Peak memory 197036 kb
Host smart-40e7c1f2-d383-4542-bf0c-5454a7fcc507
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720278779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.1720278779
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.2797523853
Short name T191
Test name
Test status
Simulation time 13784704 ps
CPU time 0.64 seconds
Started Aug 17 05:33:51 PM PDT 24
Finished Aug 17 05:33:52 PM PDT 24
Peak memory 194556 kb
Host smart-a3555ab1-fc2d-4b14-84de-aed782438ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797523853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.2797523853
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.2264792363
Short name T345
Test name
Test status
Simulation time 45243270 ps
CPU time 0.99 seconds
Started Aug 17 05:33:51 PM PDT 24
Finished Aug 17 05:33:52 PM PDT 24
Peak memory 196136 kb
Host smart-d9635dfd-bc6a-4b84-83f8-363f2861a2e7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264792363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.2264792363
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.3651807840
Short name T573
Test name
Test status
Simulation time 385928046 ps
CPU time 4.6 seconds
Started Aug 17 05:33:52 PM PDT 24
Finished Aug 17 05:33:57 PM PDT 24
Peak memory 198124 kb
Host smart-2520e00f-374f-4c5a-8941-afe27a76bbe0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651807840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.3651807840
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.3833711405
Short name T68
Test name
Test status
Simulation time 268326137 ps
CPU time 1.11 seconds
Started Aug 17 05:33:54 PM PDT 24
Finished Aug 17 05:33:56 PM PDT 24
Peak memory 196716 kb
Host smart-f0e4e021-6ed8-4e0e-89da-d0a07c94f17c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833711405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.3833711405
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.3263691473
Short name T593
Test name
Test status
Simulation time 35298031 ps
CPU time 0.81 seconds
Started Aug 17 05:33:52 PM PDT 24
Finished Aug 17 05:33:53 PM PDT 24
Peak memory 197256 kb
Host smart-2d95be10-55b7-41ec-9fac-548abf38c2f1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263691473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.3263691473
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.1293623758
Short name T683
Test name
Test status
Simulation time 25198961305 ps
CPU time 171.24 seconds
Started Aug 17 05:33:58 PM PDT 24
Finished Aug 17 05:36:49 PM PDT 24
Peak memory 198260 kb
Host smart-6197343c-9a0a-493a-afbe-769a1355f288
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293623758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.1293623758
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_stress_all_with_rand_reset.4288604297
Short name T531
Test name
Test status
Simulation time 15598707074 ps
CPU time 198.21 seconds
Started Aug 17 05:34:01 PM PDT 24
Finished Aug 17 05:37:20 PM PDT 24
Peak memory 198488 kb
Host smart-ab771f5e-fe4c-4263-a6ad-4131dace9e8d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4288604297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_stress_all_with_rand_reset.4288604297
Directory /workspace/18.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.gpio_alert_test.3312124805
Short name T189
Test name
Test status
Simulation time 37730022 ps
CPU time 0.56 seconds
Started Aug 17 05:34:03 PM PDT 24
Finished Aug 17 05:34:04 PM PDT 24
Peak memory 193996 kb
Host smart-f92ea54c-6bea-4f26-927c-1ab136ff3514
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312124805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.3312124805
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.2518262184
Short name T106
Test name
Test status
Simulation time 40849497 ps
CPU time 0.6 seconds
Started Aug 17 05:34:00 PM PDT 24
Finished Aug 17 05:34:01 PM PDT 24
Peak memory 194128 kb
Host smart-c86bd86b-5e38-4cd4-a77d-41373f0f850d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518262184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.2518262184
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.27739849
Short name T656
Test name
Test status
Simulation time 255942389 ps
CPU time 7.82 seconds
Started Aug 17 05:33:59 PM PDT 24
Finished Aug 17 05:34:07 PM PDT 24
Peak memory 198180 kb
Host smart-fb072deb-1d7c-4629-942d-38181b479667
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27739849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stress
.27739849
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.379022693
Short name T289
Test name
Test status
Simulation time 216649257 ps
CPU time 0.97 seconds
Started Aug 17 05:34:02 PM PDT 24
Finished Aug 17 05:34:03 PM PDT 24
Peak memory 197996 kb
Host smart-3946f80b-6cab-4793-a360-969da935d056
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379022693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.379022693
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.3901540500
Short name T416
Test name
Test status
Simulation time 20803140 ps
CPU time 0.74 seconds
Started Aug 17 05:34:00 PM PDT 24
Finished Aug 17 05:34:00 PM PDT 24
Peak memory 196192 kb
Host smart-de999749-90ec-4dc9-b47a-fd14004de062
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901540500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.3901540500
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.3372166296
Short name T647
Test name
Test status
Simulation time 36525981 ps
CPU time 0.98 seconds
Started Aug 17 05:33:59 PM PDT 24
Finished Aug 17 05:34:00 PM PDT 24
Peak memory 196064 kb
Host smart-82a73381-4b31-46cc-a941-58ff6e76100d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372166296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.3372166296
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.2912916322
Short name T330
Test name
Test status
Simulation time 604501802 ps
CPU time 3 seconds
Started Aug 17 05:33:59 PM PDT 24
Finished Aug 17 05:34:02 PM PDT 24
Peak memory 196000 kb
Host smart-b1635161-3431-4b1e-9e2f-935591f62679
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912916322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.2912916322
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.3412800304
Short name T629
Test name
Test status
Simulation time 153873882 ps
CPU time 1.28 seconds
Started Aug 17 05:34:02 PM PDT 24
Finished Aug 17 05:34:04 PM PDT 24
Peak memory 197000 kb
Host smart-413e90b4-793d-41a1-8e83-2cbadb2945ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412800304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.3412800304
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.857597717
Short name T328
Test name
Test status
Simulation time 141382797 ps
CPU time 0.99 seconds
Started Aug 17 05:34:00 PM PDT 24
Finished Aug 17 05:34:01 PM PDT 24
Peak memory 196108 kb
Host smart-ca408612-43f8-4d12-ad0d-077f3ffa959b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857597717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullup
_pulldown.857597717
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.2499573287
Short name T446
Test name
Test status
Simulation time 51328708 ps
CPU time 2.14 seconds
Started Aug 17 05:34:03 PM PDT 24
Finished Aug 17 05:34:05 PM PDT 24
Peak memory 198208 kb
Host smart-d334cae3-18f2-45d2-8c55-22bdb06964fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499573287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.2499573287
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.3807143377
Short name T558
Test name
Test status
Simulation time 78103445 ps
CPU time 1.2 seconds
Started Aug 17 05:34:04 PM PDT 24
Finished Aug 17 05:34:05 PM PDT 24
Peak memory 195920 kb
Host smart-f2324f18-8479-42b9-800d-30791f9fb557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807143377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.3807143377
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.1852714230
Short name T482
Test name
Test status
Simulation time 595067762 ps
CPU time 1.25 seconds
Started Aug 17 05:33:59 PM PDT 24
Finished Aug 17 05:34:00 PM PDT 24
Peak memory 197052 kb
Host smart-1372fd01-cd5c-4e6c-866b-05e5ec462f63
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852714230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.1852714230
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.934422611
Short name T414
Test name
Test status
Simulation time 4923581318 ps
CPU time 57.44 seconds
Started Aug 17 05:33:59 PM PDT 24
Finished Aug 17 05:34:57 PM PDT 24
Peak memory 198352 kb
Host smart-d24102e4-3363-4e05-b70d-ca50b81b1b53
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934422611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.g
pio_stress_all.934422611
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_alert_test.1686929340
Short name T278
Test name
Test status
Simulation time 27833215 ps
CPU time 0.53 seconds
Started Aug 17 05:32:37 PM PDT 24
Finished Aug 17 05:32:37 PM PDT 24
Peak memory 192824 kb
Host smart-ad171aba-1760-45d8-a193-ac6b69f99815
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686929340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.1686929340
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.501457135
Short name T304
Test name
Test status
Simulation time 274929771 ps
CPU time 0.62 seconds
Started Aug 17 05:32:25 PM PDT 24
Finished Aug 17 05:32:26 PM PDT 24
Peak memory 194172 kb
Host smart-49c25095-6de1-490c-9e0a-7a9a57a3333c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501457135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.501457135
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.3374030674
Short name T411
Test name
Test status
Simulation time 852138355 ps
CPU time 11.63 seconds
Started Aug 17 05:32:35 PM PDT 24
Finished Aug 17 05:32:47 PM PDT 24
Peak memory 197148 kb
Host smart-172a1709-4bf1-4191-b95f-b4d743210346
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374030674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.3374030674
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.3076731696
Short name T368
Test name
Test status
Simulation time 77354475 ps
CPU time 1.02 seconds
Started Aug 17 05:32:38 PM PDT 24
Finished Aug 17 05:32:39 PM PDT 24
Peak memory 196652 kb
Host smart-da4b7221-010e-4aed-82a6-864e3553ecf1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076731696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.3076731696
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.151215185
Short name T122
Test name
Test status
Simulation time 57650720 ps
CPU time 0.91 seconds
Started Aug 17 05:32:25 PM PDT 24
Finished Aug 17 05:32:26 PM PDT 24
Peak memory 195840 kb
Host smart-db42c5cf-ff3c-4c61-87e1-bdb691076a47
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151215185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.151215185
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.2933638284
Short name T661
Test name
Test status
Simulation time 28136939 ps
CPU time 1.19 seconds
Started Aug 17 05:32:28 PM PDT 24
Finished Aug 17 05:32:29 PM PDT 24
Peak memory 198096 kb
Host smart-20940a10-0587-4740-8f5b-8a7bb28f66b5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933638284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.2933638284
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.1941130061
Short name T109
Test name
Test status
Simulation time 135022941 ps
CPU time 3.29 seconds
Started Aug 17 05:32:28 PM PDT 24
Finished Aug 17 05:32:31 PM PDT 24
Peak memory 196044 kb
Host smart-55970d69-5a10-4e55-9977-5dd8a56470fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941130061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
1941130061
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.390789499
Short name T657
Test name
Test status
Simulation time 131145996 ps
CPU time 1.17 seconds
Started Aug 17 05:32:26 PM PDT 24
Finished Aug 17 05:32:27 PM PDT 24
Peak memory 197020 kb
Host smart-03e6559d-6059-47f4-aed8-0c1932200997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390789499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.390789499
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.2908704796
Short name T363
Test name
Test status
Simulation time 121026308 ps
CPU time 0.67 seconds
Started Aug 17 05:32:25 PM PDT 24
Finished Aug 17 05:32:26 PM PDT 24
Peak memory 194496 kb
Host smart-3dbc205c-5256-487d-9e94-26d85b1fd4dc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908704796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.2908704796
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.850134277
Short name T369
Test name
Test status
Simulation time 138036541 ps
CPU time 2.52 seconds
Started Aug 17 05:32:35 PM PDT 24
Finished Aug 17 05:32:37 PM PDT 24
Peak memory 198164 kb
Host smart-c853602f-5ff1-4d85-8e85-64605342d1be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850134277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand
om_long_reg_writes_reg_reads.850134277
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.1018987238
Short name T36
Test name
Test status
Simulation time 130950683 ps
CPU time 0.85 seconds
Started Aug 17 05:32:34 PM PDT 24
Finished Aug 17 05:32:35 PM PDT 24
Peak memory 214860 kb
Host smart-ef04330f-a1f2-40a1-8144-c9347c0430ca
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018987238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.1018987238
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.1145101781
Short name T143
Test name
Test status
Simulation time 39884555 ps
CPU time 1.23 seconds
Started Aug 17 05:32:26 PM PDT 24
Finished Aug 17 05:32:27 PM PDT 24
Peak memory 198096 kb
Host smart-d0de80f4-cc8c-4e3b-b31a-efd0e7ddfdfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145101781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.1145101781
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.4123846716
Short name T530
Test name
Test status
Simulation time 83830977 ps
CPU time 1.19 seconds
Started Aug 17 05:32:28 PM PDT 24
Finished Aug 17 05:32:30 PM PDT 24
Peak memory 196008 kb
Host smart-c3dd7b5b-f755-43c9-a701-fee817177e6c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123846716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.4123846716
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.912498618
Short name T688
Test name
Test status
Simulation time 19326382434 ps
CPU time 198.96 seconds
Started Aug 17 05:32:36 PM PDT 24
Finished Aug 17 05:35:55 PM PDT 24
Peak memory 198360 kb
Host smart-d0d5632b-4328-4327-906c-b3b63bd0f4d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912498618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gp
io_stress_all.912498618
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_alert_test.808256708
Short name T501
Test name
Test status
Simulation time 13003807 ps
CPU time 0.57 seconds
Started Aug 17 05:34:08 PM PDT 24
Finished Aug 17 05:34:09 PM PDT 24
Peak memory 194052 kb
Host smart-d94f5ae5-a44c-49a5-aa67-0b1a615ff8c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808256708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.808256708
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.669263447
Short name T211
Test name
Test status
Simulation time 24769712 ps
CPU time 0.8 seconds
Started Aug 17 05:33:59 PM PDT 24
Finished Aug 17 05:34:00 PM PDT 24
Peak memory 197388 kb
Host smart-abe748a6-23b2-48d4-a9f7-30801a7b989c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669263447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.669263447
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.389117990
Short name T349
Test name
Test status
Simulation time 542943148 ps
CPU time 17.61 seconds
Started Aug 17 05:34:12 PM PDT 24
Finished Aug 17 05:34:30 PM PDT 24
Peak memory 198108 kb
Host smart-99e40da8-f35a-4d72-bb87-cf1b68d47389
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389117990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stres
s.389117990
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.272537628
Short name T113
Test name
Test status
Simulation time 74706935 ps
CPU time 0.86 seconds
Started Aug 17 05:34:09 PM PDT 24
Finished Aug 17 05:34:10 PM PDT 24
Peak memory 196980 kb
Host smart-fd2a4578-2c27-4d75-b936-9b8cf5ecf41e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272537628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.272537628
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.35745823
Short name T160
Test name
Test status
Simulation time 159057810 ps
CPU time 1.14 seconds
Started Aug 17 05:34:09 PM PDT 24
Finished Aug 17 05:34:10 PM PDT 24
Peak memory 195956 kb
Host smart-710b45e3-421f-4c60-ae0e-4f1eda4a3a91
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35745823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.35745823
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.1757561170
Short name T662
Test name
Test status
Simulation time 125677999 ps
CPU time 1.33 seconds
Started Aug 17 05:34:07 PM PDT 24
Finished Aug 17 05:34:09 PM PDT 24
Peak memory 196788 kb
Host smart-97376397-27af-4af0-ac70-040dcb970c1c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757561170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.1757561170
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.2193480606
Short name T61
Test name
Test status
Simulation time 119284482 ps
CPU time 2.55 seconds
Started Aug 17 05:34:10 PM PDT 24
Finished Aug 17 05:34:13 PM PDT 24
Peak memory 198204 kb
Host smart-d70ffe02-f124-4d65-a9f6-4ac1b9198bf4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193480606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.2193480606
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.2135980142
Short name T195
Test name
Test status
Simulation time 59886764 ps
CPU time 1.23 seconds
Started Aug 17 05:34:02 PM PDT 24
Finished Aug 17 05:34:04 PM PDT 24
Peak memory 197064 kb
Host smart-cb16c405-bbb7-4bc8-a05f-59506d1eb051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135980142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.2135980142
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.1329321237
Short name T624
Test name
Test status
Simulation time 267293781 ps
CPU time 1.24 seconds
Started Aug 17 05:33:59 PM PDT 24
Finished Aug 17 05:34:01 PM PDT 24
Peak memory 196012 kb
Host smart-69c0f732-0da0-4e85-9b21-5fead7bcd48b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329321237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.1329321237
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.667724559
Short name T588
Test name
Test status
Simulation time 254891182 ps
CPU time 3.17 seconds
Started Aug 17 05:34:07 PM PDT 24
Finished Aug 17 05:34:10 PM PDT 24
Peak memory 198036 kb
Host smart-2e98292b-c9a8-4bc4-9db4-7c53a6574259
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667724559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ran
dom_long_reg_writes_reg_reads.667724559
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.3703493045
Short name T148
Test name
Test status
Simulation time 64522116 ps
CPU time 0.98 seconds
Started Aug 17 05:33:57 PM PDT 24
Finished Aug 17 05:33:59 PM PDT 24
Peak memory 195932 kb
Host smart-10af0c0e-01c9-46a8-88a2-e836b59e7a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703493045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.3703493045
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.749227195
Short name T198
Test name
Test status
Simulation time 48833469 ps
CPU time 0.95 seconds
Started Aug 17 05:34:02 PM PDT 24
Finished Aug 17 05:34:03 PM PDT 24
Peak memory 195836 kb
Host smart-b0074c5c-0251-489f-a031-1d73deab4bff
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749227195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.749227195
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.2374514655
Short name T210
Test name
Test status
Simulation time 14002831269 ps
CPU time 190.26 seconds
Started Aug 17 05:34:11 PM PDT 24
Finished Aug 17 05:37:22 PM PDT 24
Peak memory 198308 kb
Host smart-cecce1e5-b75a-4973-824d-c60ec9c5c72c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374514655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.2374514655
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_stress_all_with_rand_reset.2278463210
Short name T55
Test name
Test status
Simulation time 27409698124 ps
CPU time 257.69 seconds
Started Aug 17 05:34:08 PM PDT 24
Finished Aug 17 05:38:26 PM PDT 24
Peak memory 198508 kb
Host smart-64981c91-b147-45e6-99f9-73d7d5cbcf0b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2278463210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_stress_all_with_rand_reset.2278463210
Directory /workspace/20.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.gpio_alert_test.2699595937
Short name T11
Test name
Test status
Simulation time 20336882 ps
CPU time 0.55 seconds
Started Aug 17 05:34:15 PM PDT 24
Finished Aug 17 05:34:16 PM PDT 24
Peak memory 194020 kb
Host smart-7de45b4d-e223-4cc4-9f0e-82ad001d76c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699595937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.2699595937
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.951699247
Short name T124
Test name
Test status
Simulation time 21916127 ps
CPU time 0.7 seconds
Started Aug 17 05:34:12 PM PDT 24
Finished Aug 17 05:34:13 PM PDT 24
Peak memory 195376 kb
Host smart-e15c40fe-2991-4444-ae2b-edc2ca3608cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951699247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.951699247
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.2683211416
Short name T105
Test name
Test status
Simulation time 978415889 ps
CPU time 25.21 seconds
Started Aug 17 05:34:06 PM PDT 24
Finished Aug 17 05:34:31 PM PDT 24
Peak memory 198140 kb
Host smart-902dc473-cef1-414f-96d6-3f15aa016b5e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683211416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.2683211416
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.2259472737
Short name T264
Test name
Test status
Simulation time 140739773 ps
CPU time 0.78 seconds
Started Aug 17 05:34:07 PM PDT 24
Finished Aug 17 05:34:08 PM PDT 24
Peak memory 196264 kb
Host smart-92dc1490-d1a6-4806-b03e-dbd8cea1d09c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259472737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.2259472737
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.2983207029
Short name T225
Test name
Test status
Simulation time 209799299 ps
CPU time 1.07 seconds
Started Aug 17 05:34:09 PM PDT 24
Finished Aug 17 05:34:11 PM PDT 24
Peak memory 196192 kb
Host smart-83fe3f2b-6128-4cad-8afb-641b0d549a02
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983207029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.2983207029
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.3099247990
Short name T508
Test name
Test status
Simulation time 140183912 ps
CPU time 1.58 seconds
Started Aug 17 05:34:09 PM PDT 24
Finished Aug 17 05:34:10 PM PDT 24
Peak memory 198160 kb
Host smart-2d584cd9-a748-46ee-a433-6fd7090086ed
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099247990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.3099247990
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.1805773593
Short name T233
Test name
Test status
Simulation time 220185458 ps
CPU time 1.69 seconds
Started Aug 17 05:34:10 PM PDT 24
Finished Aug 17 05:34:12 PM PDT 24
Peak memory 196592 kb
Host smart-e01eadda-4199-44a3-bfa5-af3f4675da28
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805773593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.1805773593
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.3356585518
Short name T444
Test name
Test status
Simulation time 14784592 ps
CPU time 0.65 seconds
Started Aug 17 05:34:08 PM PDT 24
Finished Aug 17 05:34:08 PM PDT 24
Peak memory 195140 kb
Host smart-849ffa21-7fbb-43c1-9631-f0c22fa2426e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356585518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.3356585518
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.2088753103
Short name T141
Test name
Test status
Simulation time 137573011 ps
CPU time 0.94 seconds
Started Aug 17 05:34:08 PM PDT 24
Finished Aug 17 05:34:09 PM PDT 24
Peak memory 196068 kb
Host smart-2073b7f3-1454-454a-80df-4fb8a3deedbd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088753103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.2088753103
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.3780464754
Short name T52
Test name
Test status
Simulation time 146758179 ps
CPU time 2.61 seconds
Started Aug 17 05:34:10 PM PDT 24
Finished Aug 17 05:34:12 PM PDT 24
Peak memory 198112 kb
Host smart-5451b852-0eba-4ebf-beda-af291b50ac29
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780464754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.3780464754
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.1619922424
Short name T403
Test name
Test status
Simulation time 160254387 ps
CPU time 1.05 seconds
Started Aug 17 05:34:09 PM PDT 24
Finished Aug 17 05:34:10 PM PDT 24
Peak memory 195880 kb
Host smart-0ddface4-0fde-42ca-8bf4-95d8352ca174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619922424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.1619922424
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.774957989
Short name T274
Test name
Test status
Simulation time 43608572 ps
CPU time 1.1 seconds
Started Aug 17 05:34:08 PM PDT 24
Finished Aug 17 05:34:09 PM PDT 24
Peak memory 196424 kb
Host smart-a0151bdd-cd25-46d0-a22d-25dea1b6e4b9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774957989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.774957989
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.1916509519
Short name T2
Test name
Test status
Simulation time 49745627392 ps
CPU time 121.25 seconds
Started Aug 17 05:34:07 PM PDT 24
Finished Aug 17 05:36:08 PM PDT 24
Peak memory 198364 kb
Host smart-7cb11309-e00a-45a8-9e50-ab0088a760be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916509519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.1916509519
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_stress_all_with_rand_reset.250870934
Short name T518
Test name
Test status
Simulation time 5746510572 ps
CPU time 180.03 seconds
Started Aug 17 05:34:06 PM PDT 24
Finished Aug 17 05:37:06 PM PDT 24
Peak memory 198484 kb
Host smart-5121ecd5-d946-493e-8d11-6f1e98c46486
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=250870934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_stress_all_with_rand_reset.250870934
Directory /workspace/21.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.gpio_alert_test.2621298509
Short name T546
Test name
Test status
Simulation time 14973373 ps
CPU time 0.58 seconds
Started Aug 17 05:34:15 PM PDT 24
Finished Aug 17 05:34:16 PM PDT 24
Peak memory 194040 kb
Host smart-e76a7b50-05fd-44e5-bed3-4617ddcde71a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621298509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.2621298509
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.1802414679
Short name T681
Test name
Test status
Simulation time 24768657 ps
CPU time 0.69 seconds
Started Aug 17 05:34:18 PM PDT 24
Finished Aug 17 05:34:19 PM PDT 24
Peak memory 194288 kb
Host smart-3ca10e9b-f0e0-430e-94e2-cd945f1582ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802414679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.1802414679
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.2566373006
Short name T206
Test name
Test status
Simulation time 369767896 ps
CPU time 4.7 seconds
Started Aug 17 05:34:18 PM PDT 24
Finished Aug 17 05:34:23 PM PDT 24
Peak memory 195792 kb
Host smart-b5617f1a-ccee-4cb8-a769-34c701dd4468
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566373006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.2566373006
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.3103953743
Short name T20
Test name
Test status
Simulation time 51631376 ps
CPU time 0.8 seconds
Started Aug 17 05:34:16 PM PDT 24
Finished Aug 17 05:34:17 PM PDT 24
Peak memory 196636 kb
Host smart-e78f0211-f514-49bc-9673-b3be637efed2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103953743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.3103953743
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.689512429
Short name T492
Test name
Test status
Simulation time 238595478 ps
CPU time 1.06 seconds
Started Aug 17 05:34:18 PM PDT 24
Finished Aug 17 05:34:19 PM PDT 24
Peak memory 196644 kb
Host smart-eb23d0aa-0ed6-4adb-9af5-297eda95881c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689512429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.689512429
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.610312588
Short name T127
Test name
Test status
Simulation time 397824818 ps
CPU time 3.35 seconds
Started Aug 17 05:34:16 PM PDT 24
Finished Aug 17 05:34:20 PM PDT 24
Peak memory 198280 kb
Host smart-d706e132-3fa1-463d-aa3e-56f80e5e5223
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610312588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 22.gpio_intr_with_filter_rand_intr_event.610312588
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.975760093
Short name T261
Test name
Test status
Simulation time 82091189 ps
CPU time 2.42 seconds
Started Aug 17 05:34:14 PM PDT 24
Finished Aug 17 05:34:17 PM PDT 24
Peak memory 197380 kb
Host smart-0db254fb-472a-4247-85fb-857b7815e396
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975760093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger.
975760093
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.1247055322
Short name T678
Test name
Test status
Simulation time 31832207 ps
CPU time 0.65 seconds
Started Aug 17 05:34:18 PM PDT 24
Finished Aug 17 05:34:18 PM PDT 24
Peak memory 194956 kb
Host smart-9cb99443-39e5-46af-919e-4e2a3b50781b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247055322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.1247055322
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.1262052667
Short name T560
Test name
Test status
Simulation time 207271818 ps
CPU time 1.2 seconds
Started Aug 17 05:34:17 PM PDT 24
Finished Aug 17 05:34:19 PM PDT 24
Peak memory 198240 kb
Host smart-c5afc2ad-9fa7-4c57-8383-31956324ea38
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262052667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.1262052667
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.3836279937
Short name T455
Test name
Test status
Simulation time 381415757 ps
CPU time 6.06 seconds
Started Aug 17 05:34:19 PM PDT 24
Finished Aug 17 05:34:25 PM PDT 24
Peak memory 198108 kb
Host smart-3149f719-9584-43f6-a356-387393eafc30
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836279937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.3836279937
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.458869094
Short name T502
Test name
Test status
Simulation time 93388272 ps
CPU time 1.25 seconds
Started Aug 17 05:34:16 PM PDT 24
Finished Aug 17 05:34:17 PM PDT 24
Peak memory 196556 kb
Host smart-d1888735-b9bc-4395-b27b-304cebb06817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458869094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.458869094
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.2661964383
Short name T467
Test name
Test status
Simulation time 33873153 ps
CPU time 0.94 seconds
Started Aug 17 05:34:15 PM PDT 24
Finished Aug 17 05:34:16 PM PDT 24
Peak memory 196008 kb
Host smart-2edb011a-ce87-4b34-b514-fa7588787fff
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661964383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.2661964383
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.808532309
Short name T250
Test name
Test status
Simulation time 187066154590 ps
CPU time 157.06 seconds
Started Aug 17 05:34:17 PM PDT 24
Finished Aug 17 05:36:54 PM PDT 24
Peak memory 198300 kb
Host smart-9aab59ef-1ba0-4013-b674-bb4beb303350
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808532309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.g
pio_stress_all.808532309
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_alert_test.3281795369
Short name T203
Test name
Test status
Simulation time 13653283 ps
CPU time 0.57 seconds
Started Aug 17 05:34:14 PM PDT 24
Finished Aug 17 05:34:15 PM PDT 24
Peak memory 194168 kb
Host smart-833224d3-16c3-4ff1-8056-f58c26dc5402
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281795369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.3281795369
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.147345182
Short name T650
Test name
Test status
Simulation time 158990724 ps
CPU time 0.77 seconds
Started Aug 17 05:34:15 PM PDT 24
Finished Aug 17 05:34:16 PM PDT 24
Peak memory 195360 kb
Host smart-1a03bbfb-eda9-43f1-9cd7-49fce79e1f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147345182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.147345182
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.2675857504
Short name T685
Test name
Test status
Simulation time 1019477150 ps
CPU time 16.14 seconds
Started Aug 17 05:34:16 PM PDT 24
Finished Aug 17 05:34:32 PM PDT 24
Peak memory 195624 kb
Host smart-60c02ce2-3a58-4a2d-98aa-b71c99738b02
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675857504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.2675857504
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.2560367473
Short name T589
Test name
Test status
Simulation time 99754242 ps
CPU time 1.07 seconds
Started Aug 17 05:34:17 PM PDT 24
Finished Aug 17 05:34:18 PM PDT 24
Peak memory 198096 kb
Host smart-4a671897-b5ad-4608-a54e-abb9d9321d9e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560367473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.2560367473
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.1016737677
Short name T613
Test name
Test status
Simulation time 79207682 ps
CPU time 1.28 seconds
Started Aug 17 05:34:23 PM PDT 24
Finished Aug 17 05:34:25 PM PDT 24
Peak memory 197236 kb
Host smart-2cc11dc2-826b-406c-8733-7c1191f7e43f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016737677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.1016737677
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.632596391
Short name T123
Test name
Test status
Simulation time 57108289 ps
CPU time 1.84 seconds
Started Aug 17 05:34:16 PM PDT 24
Finished Aug 17 05:34:18 PM PDT 24
Peak memory 198168 kb
Host smart-51ff0a43-733a-4f01-a332-90cdd88b2ece
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632596391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 23.gpio_intr_with_filter_rand_intr_event.632596391
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.4049572331
Short name T500
Test name
Test status
Simulation time 229321670 ps
CPU time 1.45 seconds
Started Aug 17 05:34:20 PM PDT 24
Finished Aug 17 05:34:21 PM PDT 24
Peak memory 196060 kb
Host smart-13014934-43bf-40e6-b854-ae31a161b43b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049572331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.4049572331
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.922773788
Short name T377
Test name
Test status
Simulation time 56550026 ps
CPU time 1.22 seconds
Started Aug 17 05:34:18 PM PDT 24
Finished Aug 17 05:34:19 PM PDT 24
Peak memory 197112 kb
Host smart-123b1b09-b3b7-4b58-8822-f1718d1c7cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922773788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.922773788
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.3808030414
Short name T350
Test name
Test status
Simulation time 42375170 ps
CPU time 0.99 seconds
Started Aug 17 05:34:14 PM PDT 24
Finished Aug 17 05:34:15 PM PDT 24
Peak memory 196152 kb
Host smart-a17324f7-f4c6-4fb0-a233-eaa03f2ba9c1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808030414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.3808030414
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_smoke.2452896249
Short name T201
Test name
Test status
Simulation time 303829174 ps
CPU time 1.17 seconds
Started Aug 17 05:34:17 PM PDT 24
Finished Aug 17 05:34:19 PM PDT 24
Peak memory 195904 kb
Host smart-4ace6766-ddd6-4c4b-9d8b-47ce0108afde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452896249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.2452896249
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.2922290587
Short name T692
Test name
Test status
Simulation time 256045248 ps
CPU time 0.8 seconds
Started Aug 17 05:34:16 PM PDT 24
Finished Aug 17 05:34:17 PM PDT 24
Peak memory 195972 kb
Host smart-860589f9-d554-4896-9c0a-414ecf6d28ee
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922290587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.2922290587
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.1019949770
Short name T594
Test name
Test status
Simulation time 48639657814 ps
CPU time 153.26 seconds
Started Aug 17 05:34:14 PM PDT 24
Finished Aug 17 05:36:47 PM PDT 24
Peak memory 198264 kb
Host smart-2a7242a1-c29f-4915-9940-fa8910b534aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019949770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.1019949770
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_alert_test.3197638703
Short name T521
Test name
Test status
Simulation time 36249379 ps
CPU time 0.55 seconds
Started Aug 17 05:34:24 PM PDT 24
Finished Aug 17 05:34:25 PM PDT 24
Peak memory 194060 kb
Host smart-c2657f87-ba72-4558-9be3-82dc656fa0d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197638703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.3197638703
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.1850866325
Short name T443
Test name
Test status
Simulation time 99204002 ps
CPU time 0.8 seconds
Started Aug 17 05:34:15 PM PDT 24
Finished Aug 17 05:34:16 PM PDT 24
Peak memory 195552 kb
Host smart-67c4e101-bc58-4791-a6aa-1e04611dbfca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850866325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.1850866325
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.2748247660
Short name T491
Test name
Test status
Simulation time 7420880660 ps
CPU time 25.68 seconds
Started Aug 17 05:34:24 PM PDT 24
Finished Aug 17 05:34:49 PM PDT 24
Peak memory 196716 kb
Host smart-409029d6-133f-4802-a5d1-e1f4f000a378
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748247660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.2748247660
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.1388354083
Short name T695
Test name
Test status
Simulation time 98325525 ps
CPU time 1.03 seconds
Started Aug 17 05:34:23 PM PDT 24
Finished Aug 17 05:34:24 PM PDT 24
Peak memory 198020 kb
Host smart-2fedc652-9a0c-4904-9111-7858c8dedb11
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388354083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.1388354083
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.259938988
Short name T612
Test name
Test status
Simulation time 158085542 ps
CPU time 1.08 seconds
Started Aug 17 05:34:17 PM PDT 24
Finished Aug 17 05:34:18 PM PDT 24
Peak memory 195880 kb
Host smart-e9897b55-3980-4a1d-b040-cba89659611c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259938988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.259938988
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.1003657195
Short name T607
Test name
Test status
Simulation time 27617212 ps
CPU time 1.12 seconds
Started Aug 17 05:34:18 PM PDT 24
Finished Aug 17 05:34:20 PM PDT 24
Peak memory 197460 kb
Host smart-2744a8a3-bc57-4f95-9427-fa31566b012c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003657195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.1003657195
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.4087871816
Short name T258
Test name
Test status
Simulation time 348038812 ps
CPU time 1.87 seconds
Started Aug 17 05:34:20 PM PDT 24
Finished Aug 17 05:34:22 PM PDT 24
Peak memory 196844 kb
Host smart-fbbe2899-de3e-4187-bc1e-c493e050642e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087871816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.4087871816
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.544394918
Short name T138
Test name
Test status
Simulation time 168474188 ps
CPU time 0.67 seconds
Started Aug 17 05:34:17 PM PDT 24
Finished Aug 17 05:34:18 PM PDT 24
Peak memory 194492 kb
Host smart-1480f16c-97ac-4da7-b55a-5cccb6cf4ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544394918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.544394918
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.2410136163
Short name T666
Test name
Test status
Simulation time 76839602 ps
CPU time 0.86 seconds
Started Aug 17 05:34:14 PM PDT 24
Finished Aug 17 05:34:15 PM PDT 24
Peak memory 196896 kb
Host smart-70931029-f179-4f3c-81ce-ab554db6dbbe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410136163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullu
p_pulldown.2410136163
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.2848073960
Short name T13
Test name
Test status
Simulation time 1157306822 ps
CPU time 3.24 seconds
Started Aug 17 05:34:23 PM PDT 24
Finished Aug 17 05:34:26 PM PDT 24
Peak memory 198128 kb
Host smart-3df6a7f7-859c-4b77-81da-927acfab7859
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848073960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.2848073960
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.1196902874
Short name T711
Test name
Test status
Simulation time 45901413 ps
CPU time 1.26 seconds
Started Aug 17 05:34:14 PM PDT 24
Finished Aug 17 05:34:15 PM PDT 24
Peak memory 198208 kb
Host smart-96633f12-26e5-4b7e-ba1a-8aa0f9e38025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196902874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.1196902874
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.3750541522
Short name T677
Test name
Test status
Simulation time 130407232 ps
CPU time 1.1 seconds
Started Aug 17 05:34:16 PM PDT 24
Finished Aug 17 05:34:17 PM PDT 24
Peak memory 196568 kb
Host smart-d80b0bf5-d070-4f3d-b262-465333af9a18
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750541522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.3750541522
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.656469025
Short name T699
Test name
Test status
Simulation time 6044084450 ps
CPU time 157.72 seconds
Started Aug 17 05:34:22 PM PDT 24
Finished Aug 17 05:37:00 PM PDT 24
Peak memory 198348 kb
Host smart-95ae4fc2-28a1-4104-88b3-355d7e7204be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656469025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.g
pio_stress_all.656469025
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_alert_test.1451598880
Short name T162
Test name
Test status
Simulation time 46914504 ps
CPU time 0.57 seconds
Started Aug 17 05:34:34 PM PDT 24
Finished Aug 17 05:34:35 PM PDT 24
Peak memory 194048 kb
Host smart-ab44a00a-6df5-4e03-bba4-9bdabf27721f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451598880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.1451598880
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.429738523
Short name T696
Test name
Test status
Simulation time 92652865 ps
CPU time 0.63 seconds
Started Aug 17 05:34:23 PM PDT 24
Finished Aug 17 05:34:23 PM PDT 24
Peak memory 194208 kb
Host smart-7bcfc06a-9bd2-48d7-be02-f9685eaa8b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429738523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.429738523
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.4221209910
Short name T577
Test name
Test status
Simulation time 117883396 ps
CPU time 5.72 seconds
Started Aug 17 05:34:23 PM PDT 24
Finished Aug 17 05:34:28 PM PDT 24
Peak memory 195608 kb
Host smart-46ee4914-a9cd-4ecf-a84c-c1e3cb53133e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221209910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.4221209910
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.3067507088
Short name T228
Test name
Test status
Simulation time 527116326 ps
CPU time 0.83 seconds
Started Aug 17 05:34:25 PM PDT 24
Finished Aug 17 05:34:26 PM PDT 24
Peak memory 196124 kb
Host smart-8d6981b7-2303-4ef4-bfa6-3e965c446f7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067507088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.3067507088
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.2584700432
Short name T117
Test name
Test status
Simulation time 185554585 ps
CPU time 1.15 seconds
Started Aug 17 05:34:24 PM PDT 24
Finished Aug 17 05:34:25 PM PDT 24
Peak memory 197404 kb
Host smart-08ddf4ef-06a4-4d74-a9e0-00a55b6db2ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584700432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.2584700432
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.3865038251
Short name T282
Test name
Test status
Simulation time 81565341 ps
CPU time 3.03 seconds
Started Aug 17 05:34:23 PM PDT 24
Finished Aug 17 05:34:26 PM PDT 24
Peak memory 198152 kb
Host smart-ce1e850f-c9f5-4370-93ce-43eb8a913b9a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865038251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.3865038251
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.3260871464
Short name T107
Test name
Test status
Simulation time 299902895 ps
CPU time 1.98 seconds
Started Aug 17 05:34:23 PM PDT 24
Finished Aug 17 05:34:25 PM PDT 24
Peak memory 198208 kb
Host smart-56b29230-b1a9-41d3-acab-be1f087f8e2e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260871464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.3260871464
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.4058614495
Short name T473
Test name
Test status
Simulation time 71945559 ps
CPU time 1.17 seconds
Started Aug 17 05:34:25 PM PDT 24
Finished Aug 17 05:34:26 PM PDT 24
Peak memory 196656 kb
Host smart-9950ef35-06ef-4e4e-bb10-7075335183ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058614495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.4058614495
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.1506888947
Short name T296
Test name
Test status
Simulation time 208512431 ps
CPU time 1.29 seconds
Started Aug 17 05:34:24 PM PDT 24
Finished Aug 17 05:34:26 PM PDT 24
Peak memory 195956 kb
Host smart-096f6c89-bfa5-4656-acbd-af8e97487225
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506888947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.1506888947
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.2539305025
Short name T10
Test name
Test status
Simulation time 1637831091 ps
CPU time 4.52 seconds
Started Aug 17 05:34:22 PM PDT 24
Finished Aug 17 05:34:27 PM PDT 24
Peak memory 198164 kb
Host smart-2662bec9-9ed8-4032-8a3d-69aed995d7a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539305025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.2539305025
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.2176062427
Short name T364
Test name
Test status
Simulation time 120269183 ps
CPU time 0.96 seconds
Started Aug 17 05:34:23 PM PDT 24
Finished Aug 17 05:34:24 PM PDT 24
Peak memory 196016 kb
Host smart-8618dcff-d731-492e-81c2-a8bc2a93e710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176062427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.2176062427
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.600312105
Short name T604
Test name
Test status
Simulation time 83418634 ps
CPU time 1.4 seconds
Started Aug 17 05:34:25 PM PDT 24
Finished Aug 17 05:34:26 PM PDT 24
Peak memory 195692 kb
Host smart-5d86929a-8914-4f30-a5e5-712bcb333943
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600312105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.600312105
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.3145731458
Short name T582
Test name
Test status
Simulation time 13948224348 ps
CPU time 175.14 seconds
Started Aug 17 05:34:34 PM PDT 24
Finished Aug 17 05:37:29 PM PDT 24
Peak memory 198356 kb
Host smart-ad1a2235-5495-4673-908f-a80ffe10844d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145731458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.3145731458
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_alert_test.3945454005
Short name T131
Test name
Test status
Simulation time 162938682 ps
CPU time 0.55 seconds
Started Aug 17 05:34:34 PM PDT 24
Finished Aug 17 05:34:34 PM PDT 24
Peak memory 194700 kb
Host smart-bcfd78fa-5aab-4bb0-9e1f-36f0976bb161
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945454005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.3945454005
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.3187231393
Short name T462
Test name
Test status
Simulation time 29481974 ps
CPU time 0.7 seconds
Started Aug 17 05:34:33 PM PDT 24
Finished Aug 17 05:34:33 PM PDT 24
Peak memory 195276 kb
Host smart-11a26910-a82e-4bac-bb82-04ab37333098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187231393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.3187231393
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.1583983179
Short name T193
Test name
Test status
Simulation time 3839747659 ps
CPU time 24.04 seconds
Started Aug 17 05:34:33 PM PDT 24
Finished Aug 17 05:34:57 PM PDT 24
Peak memory 196820 kb
Host smart-c02de8ff-3079-453f-b38a-56367f36c5d7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583983179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.1583983179
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.2512102570
Short name T230
Test name
Test status
Simulation time 340767037 ps
CPU time 0.96 seconds
Started Aug 17 05:34:34 PM PDT 24
Finished Aug 17 05:34:35 PM PDT 24
Peak memory 196604 kb
Host smart-96f5e27b-49e5-48fa-a75a-3fc849718d06
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512102570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.2512102570
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.1626532035
Short name T547
Test name
Test status
Simulation time 25775367 ps
CPU time 0.87 seconds
Started Aug 17 05:34:33 PM PDT 24
Finished Aug 17 05:34:34 PM PDT 24
Peak memory 196724 kb
Host smart-219bbf0f-7dac-4160-9daa-aaad6000edef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626532035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.1626532035
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.3459466742
Short name T513
Test name
Test status
Simulation time 162169678 ps
CPU time 2.59 seconds
Started Aug 17 05:34:34 PM PDT 24
Finished Aug 17 05:34:37 PM PDT 24
Peak memory 198220 kb
Host smart-091637d0-05b5-4e55-9d51-602fa1020634
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459466742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.3459466742
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.3371927184
Short name T408
Test name
Test status
Simulation time 153415081 ps
CPU time 3.04 seconds
Started Aug 17 05:34:33 PM PDT 24
Finished Aug 17 05:34:36 PM PDT 24
Peak memory 197172 kb
Host smart-3e25f8e3-729b-45f8-846b-8be9e76328ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371927184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.3371927184
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.301420407
Short name T436
Test name
Test status
Simulation time 234705576 ps
CPU time 0.91 seconds
Started Aug 17 05:34:30 PM PDT 24
Finished Aug 17 05:34:31 PM PDT 24
Peak memory 196152 kb
Host smart-c1839bcf-5d71-43a9-bded-0a718e0c4fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301420407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.301420407
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.3615026423
Short name T14
Test name
Test status
Simulation time 277322310 ps
CPU time 1.35 seconds
Started Aug 17 05:34:34 PM PDT 24
Finished Aug 17 05:34:36 PM PDT 24
Peak memory 197144 kb
Host smart-bb2a9744-6da2-4c64-8f6c-2de622644bcf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615026423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.3615026423
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.2919443292
Short name T540
Test name
Test status
Simulation time 715934985 ps
CPU time 5.72 seconds
Started Aug 17 05:34:33 PM PDT 24
Finished Aug 17 05:34:39 PM PDT 24
Peak memory 198096 kb
Host smart-95489063-f637-40a4-a8b9-00a74bbfa635
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919443292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.2919443292
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.3105416373
Short name T356
Test name
Test status
Simulation time 94151600 ps
CPU time 1.4 seconds
Started Aug 17 05:34:34 PM PDT 24
Finished Aug 17 05:34:36 PM PDT 24
Peak memory 198100 kb
Host smart-886147aa-c580-4f3e-8f40-858df56e38b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105416373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.3105416373
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.821873787
Short name T689
Test name
Test status
Simulation time 219395739 ps
CPU time 1.07 seconds
Started Aug 17 05:34:31 PM PDT 24
Finished Aug 17 05:34:33 PM PDT 24
Peak memory 196000 kb
Host smart-c826cfff-94a5-4271-9834-1573487f5ff5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821873787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.821873787
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.1670042661
Short name T146
Test name
Test status
Simulation time 22721193909 ps
CPU time 148.07 seconds
Started Aug 17 05:34:33 PM PDT 24
Finished Aug 17 05:37:01 PM PDT 24
Peak memory 198196 kb
Host smart-ff37e776-1105-4a6b-bf2f-b0b2c8a5d6b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670042661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.1670042661
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_stress_all_with_rand_reset.2265423707
Short name T56
Test name
Test status
Simulation time 4341927873 ps
CPU time 145.17 seconds
Started Aug 17 05:34:30 PM PDT 24
Finished Aug 17 05:36:56 PM PDT 24
Peak memory 198528 kb
Host smart-ab75c25b-6402-4e98-a47c-88d06a74383c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2265423707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_stress_all_with_rand_reset.2265423707
Directory /workspace/26.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.gpio_alert_test.279156962
Short name T694
Test name
Test status
Simulation time 25379923 ps
CPU time 0.57 seconds
Started Aug 17 05:34:31 PM PDT 24
Finished Aug 17 05:34:32 PM PDT 24
Peak memory 194264 kb
Host smart-80e930cb-b7f8-4fa7-8871-db95d24739e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279156962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.279156962
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.1975862718
Short name T707
Test name
Test status
Simulation time 105069590 ps
CPU time 0.9 seconds
Started Aug 17 05:34:31 PM PDT 24
Finished Aug 17 05:34:32 PM PDT 24
Peak memory 196148 kb
Host smart-8b1e1f58-5ca9-40c1-99ca-591e82fb557a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975862718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.1975862718
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.3333728389
Short name T509
Test name
Test status
Simulation time 345695501 ps
CPU time 14.22 seconds
Started Aug 17 05:34:33 PM PDT 24
Finished Aug 17 05:34:48 PM PDT 24
Peak memory 196696 kb
Host smart-c1112efa-12d0-486b-bc9b-5a2284613424
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333728389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.3333728389
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.3372060057
Short name T342
Test name
Test status
Simulation time 146272499 ps
CPU time 0.97 seconds
Started Aug 17 05:34:34 PM PDT 24
Finished Aug 17 05:34:35 PM PDT 24
Peak memory 198160 kb
Host smart-f5cb2acb-2353-44f9-9806-c00782728b7e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372060057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.3372060057
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.1839054690
Short name T331
Test name
Test status
Simulation time 81856605 ps
CPU time 1.23 seconds
Started Aug 17 05:34:32 PM PDT 24
Finished Aug 17 05:34:34 PM PDT 24
Peak memory 196308 kb
Host smart-4e9a97b1-cc59-4c2d-b0cf-54384cc8d661
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839054690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.1839054690
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.2284242020
Short name T243
Test name
Test status
Simulation time 590678287 ps
CPU time 1.64 seconds
Started Aug 17 05:34:34 PM PDT 24
Finished Aug 17 05:34:36 PM PDT 24
Peak memory 196820 kb
Host smart-423d9be8-32cc-4b62-8cd7-37e0b2df7033
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284242020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.2284242020
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.3557647492
Short name T284
Test name
Test status
Simulation time 120252849 ps
CPU time 3.69 seconds
Started Aug 17 05:34:33 PM PDT 24
Finished Aug 17 05:34:36 PM PDT 24
Peak memory 197248 kb
Host smart-3057f98f-be9b-4515-8fe9-96f24ded57cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557647492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.3557647492
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.4335223
Short name T421
Test name
Test status
Simulation time 17776967 ps
CPU time 0.61 seconds
Started Aug 17 05:34:30 PM PDT 24
Finished Aug 17 05:34:31 PM PDT 24
Peak memory 194452 kb
Host smart-254a1d9d-e1c6-4888-9a0d-7b00b1047918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4335223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.4335223
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.1207744931
Short name T660
Test name
Test status
Simulation time 80868008 ps
CPU time 0.74 seconds
Started Aug 17 05:34:34 PM PDT 24
Finished Aug 17 05:34:35 PM PDT 24
Peak memory 196144 kb
Host smart-111723f2-d9ed-45ca-844d-cf2ea9123d68
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207744931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.1207744931
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.4069543095
Short name T9
Test name
Test status
Simulation time 141224787 ps
CPU time 1.48 seconds
Started Aug 17 05:34:33 PM PDT 24
Finished Aug 17 05:34:35 PM PDT 24
Peak memory 198116 kb
Host smart-6243e28d-a13c-410f-9b48-4c6c1ad8258e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069543095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.4069543095
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.426282204
Short name T108
Test name
Test status
Simulation time 146874001 ps
CPU time 0.91 seconds
Started Aug 17 05:34:31 PM PDT 24
Finished Aug 17 05:34:32 PM PDT 24
Peak memory 196500 kb
Host smart-00c9a9a1-ed10-4cd0-8da7-813c9f058c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426282204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.426282204
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.868702553
Short name T664
Test name
Test status
Simulation time 188334405 ps
CPU time 0.93 seconds
Started Aug 17 05:34:31 PM PDT 24
Finished Aug 17 05:34:32 PM PDT 24
Peak memory 196524 kb
Host smart-b46b1778-1e58-4a09-9864-3bf225447a60
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868702553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.868702553
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.1414636152
Short name T170
Test name
Test status
Simulation time 74341129952 ps
CPU time 128.05 seconds
Started Aug 17 05:34:36 PM PDT 24
Finished Aug 17 05:36:44 PM PDT 24
Peak memory 198368 kb
Host smart-a899946d-ec6d-4951-aaa7-37dd26b0ba1d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414636152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.1414636152
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_alert_test.2416431142
Short name T222
Test name
Test status
Simulation time 11551465 ps
CPU time 0.55 seconds
Started Aug 17 05:34:40 PM PDT 24
Finished Aug 17 05:34:41 PM PDT 24
Peak memory 194224 kb
Host smart-b4170693-49b1-4853-8a3a-94c9a6d75a51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416431142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.2416431142
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.3911237461
Short name T680
Test name
Test status
Simulation time 25799544 ps
CPU time 0.63 seconds
Started Aug 17 05:34:34 PM PDT 24
Finished Aug 17 05:34:35 PM PDT 24
Peak memory 194180 kb
Host smart-85eb674c-002f-44e1-88a4-4aa8e39563d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911237461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.3911237461
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.4166203779
Short name T194
Test name
Test status
Simulation time 234029258 ps
CPU time 3.83 seconds
Started Aug 17 05:34:35 PM PDT 24
Finished Aug 17 05:34:39 PM PDT 24
Peak memory 196776 kb
Host smart-6d989f32-5caa-4937-9a89-1491959bb27b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166203779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.4166203779
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.451920108
Short name T291
Test name
Test status
Simulation time 31973628 ps
CPU time 0.69 seconds
Started Aug 17 05:34:32 PM PDT 24
Finished Aug 17 05:34:33 PM PDT 24
Peak memory 194720 kb
Host smart-2db3ae53-6f00-4478-8224-0604b4e795f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451920108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.451920108
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.1461792905
Short name T104
Test name
Test status
Simulation time 31237447 ps
CPU time 0.93 seconds
Started Aug 17 05:34:33 PM PDT 24
Finished Aug 17 05:34:34 PM PDT 24
Peak memory 196140 kb
Host smart-7e557de8-bcf0-4a35-8936-a84acd25f7cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461792905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.1461792905
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.3073842469
Short name T574
Test name
Test status
Simulation time 114767312 ps
CPU time 2.43 seconds
Started Aug 17 05:34:31 PM PDT 24
Finished Aug 17 05:34:34 PM PDT 24
Peak memory 198172 kb
Host smart-9e4f1695-59df-46f9-b15e-3ff6741fe416
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073842469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.3073842469
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.977565975
Short name T244
Test name
Test status
Simulation time 243847204 ps
CPU time 1.42 seconds
Started Aug 17 05:34:30 PM PDT 24
Finished Aug 17 05:34:32 PM PDT 24
Peak memory 196300 kb
Host smart-396b8336-a913-4b64-875e-131b58f24be3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977565975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger.
977565975
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.2794411210
Short name T460
Test name
Test status
Simulation time 42233299 ps
CPU time 1.01 seconds
Started Aug 17 05:34:33 PM PDT 24
Finished Aug 17 05:34:34 PM PDT 24
Peak memory 196204 kb
Host smart-502de588-498d-45e1-a36d-db972abbd55b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794411210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.2794411210
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.1290658360
Short name T301
Test name
Test status
Simulation time 161470243 ps
CPU time 1.01 seconds
Started Aug 17 05:34:31 PM PDT 24
Finished Aug 17 05:34:32 PM PDT 24
Peak memory 196008 kb
Host smart-bb1ce11a-af23-4437-90cb-2c532a7902d1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290658360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.1290658360
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.833097091
Short name T373
Test name
Test status
Simulation time 287265711 ps
CPU time 4.81 seconds
Started Aug 17 05:34:33 PM PDT 24
Finished Aug 17 05:34:38 PM PDT 24
Peak memory 197880 kb
Host smart-a4c5a45a-f111-45d3-b5dd-d67c286864f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833097091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ran
dom_long_reg_writes_reg_reads.833097091
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.4086831077
Short name T620
Test name
Test status
Simulation time 112206916 ps
CPU time 1.06 seconds
Started Aug 17 05:34:32 PM PDT 24
Finished Aug 17 05:34:33 PM PDT 24
Peak memory 195716 kb
Host smart-bc632099-4d69-41fa-9bbe-64e082d4df26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086831077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.4086831077
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.3400852772
Short name T418
Test name
Test status
Simulation time 86933892 ps
CPU time 1.33 seconds
Started Aug 17 05:34:31 PM PDT 24
Finished Aug 17 05:34:33 PM PDT 24
Peak memory 196952 kb
Host smart-89339aad-8e3a-4ade-8b86-59f9c2763d65
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400852772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.3400852772
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.3211461297
Short name T226
Test name
Test status
Simulation time 8969480834 ps
CPU time 56.13 seconds
Started Aug 17 05:34:43 PM PDT 24
Finished Aug 17 05:35:39 PM PDT 24
Peak memory 198252 kb
Host smart-780ba94f-fc3f-49bc-9174-88b112dbbcd5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211461297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.3211461297
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_alert_test.956020488
Short name T383
Test name
Test status
Simulation time 11326530 ps
CPU time 0.55 seconds
Started Aug 17 05:34:41 PM PDT 24
Finished Aug 17 05:34:42 PM PDT 24
Peak memory 194024 kb
Host smart-b2207dfd-a74f-4d92-bf56-e35fbda2a286
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956020488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.956020488
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.354297633
Short name T440
Test name
Test status
Simulation time 40746945 ps
CPU time 0.59 seconds
Started Aug 17 05:34:41 PM PDT 24
Finished Aug 17 05:34:42 PM PDT 24
Peak memory 194000 kb
Host smart-b0a52513-5608-43bb-affd-3f24ddd84143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354297633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.354297633
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.3724932977
Short name T512
Test name
Test status
Simulation time 1620609671 ps
CPU time 15.72 seconds
Started Aug 17 05:34:44 PM PDT 24
Finished Aug 17 05:35:00 PM PDT 24
Peak memory 197068 kb
Host smart-04e17c1f-929b-4c19-aeca-e71414cec4f4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724932977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.3724932977
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.2701512884
Short name T16
Test name
Test status
Simulation time 134854424 ps
CPU time 1.14 seconds
Started Aug 17 05:34:44 PM PDT 24
Finished Aug 17 05:34:45 PM PDT 24
Peak memory 198224 kb
Host smart-de3947d3-af7c-45fb-b0bf-1dbbd127f06c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701512884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.2701512884
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.2027070324
Short name T636
Test name
Test status
Simulation time 172752092 ps
CPU time 0.96 seconds
Started Aug 17 05:34:42 PM PDT 24
Finished Aug 17 05:34:43 PM PDT 24
Peak memory 195960 kb
Host smart-0719858c-0bdc-42e9-beb0-0c38f3386dd4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027070324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.2027070324
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.1506716376
Short name T625
Test name
Test status
Simulation time 65226242 ps
CPU time 2.54 seconds
Started Aug 17 05:34:44 PM PDT 24
Finished Aug 17 05:34:47 PM PDT 24
Peak memory 198252 kb
Host smart-894be5b9-5352-468b-a8cc-790192c74eac
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506716376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.1506716376
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.4217974210
Short name T126
Test name
Test status
Simulation time 207469095 ps
CPU time 1.07 seconds
Started Aug 17 05:34:44 PM PDT 24
Finished Aug 17 05:34:45 PM PDT 24
Peak memory 196216 kb
Host smart-2feb81c1-bcbb-4cdd-9775-4a62054224a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217974210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.4217974210
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.1356450165
Short name T114
Test name
Test status
Simulation time 166276041 ps
CPU time 1.09 seconds
Started Aug 17 05:34:44 PM PDT 24
Finished Aug 17 05:34:45 PM PDT 24
Peak memory 196224 kb
Host smart-525e1ebf-c5d0-4a37-8db8-173550031560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356450165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.1356450165
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.3710753985
Short name T643
Test name
Test status
Simulation time 185570613 ps
CPU time 1.01 seconds
Started Aug 17 05:34:43 PM PDT 24
Finished Aug 17 05:34:44 PM PDT 24
Peak memory 195932 kb
Host smart-b410fb2d-e13b-4b7d-afac-51a1c0270580
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710753985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.3710753985
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.1712412673
Short name T404
Test name
Test status
Simulation time 383357183 ps
CPU time 4.77 seconds
Started Aug 17 05:34:44 PM PDT 24
Finished Aug 17 05:34:49 PM PDT 24
Peak memory 198144 kb
Host smart-ab4aa988-8d1c-4fe3-9a07-95defd2d0446
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712412673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.1712412673
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.1284583508
Short name T111
Test name
Test status
Simulation time 262974787 ps
CPU time 1.35 seconds
Started Aug 17 05:34:41 PM PDT 24
Finished Aug 17 05:34:42 PM PDT 24
Peak memory 198136 kb
Host smart-4fc9646c-9199-4210-8fa7-1247a44adff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284583508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.1284583508
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.2666050894
Short name T603
Test name
Test status
Simulation time 91956580 ps
CPU time 0.82 seconds
Started Aug 17 05:34:42 PM PDT 24
Finished Aug 17 05:34:43 PM PDT 24
Peak memory 195344 kb
Host smart-4f7f1568-b8cb-4f31-bff7-8b24f259b2b8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666050894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.2666050894
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.4119208433
Short name T419
Test name
Test status
Simulation time 1835659645 ps
CPU time 53.36 seconds
Started Aug 17 05:34:41 PM PDT 24
Finished Aug 17 05:35:35 PM PDT 24
Peak memory 198264 kb
Host smart-5197401d-c78c-435f-a601-afd5ddafafc7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119208433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.4119208433
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_stress_all_with_rand_reset.4110872817
Short name T30
Test name
Test status
Simulation time 19807799454 ps
CPU time 132.65 seconds
Started Aug 17 05:34:43 PM PDT 24
Finished Aug 17 05:36:56 PM PDT 24
Peak memory 198564 kb
Host smart-956ccba7-2f93-4a15-9275-a411f895c43c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4110872817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_stress_all_with_rand_reset.4110872817
Directory /workspace/29.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.gpio_alert_test.1934418383
Short name T394
Test name
Test status
Simulation time 42440276 ps
CPU time 0.56 seconds
Started Aug 17 05:32:45 PM PDT 24
Finished Aug 17 05:32:45 PM PDT 24
Peak memory 194756 kb
Host smart-11de5747-aacf-4658-a9fc-cc4e9652355e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934418383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.1934418383
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.4266641570
Short name T549
Test name
Test status
Simulation time 26509708 ps
CPU time 0.73 seconds
Started Aug 17 05:32:42 PM PDT 24
Finished Aug 17 05:32:43 PM PDT 24
Peak memory 195080 kb
Host smart-bb29471e-f2a6-4a7e-9142-24e50367faf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266641570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.4266641570
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.1280140830
Short name T371
Test name
Test status
Simulation time 2154058616 ps
CPU time 24.44 seconds
Started Aug 17 05:32:45 PM PDT 24
Finished Aug 17 05:33:09 PM PDT 24
Peak memory 195972 kb
Host smart-72242f4a-d57c-4606-8e16-b14a06ec9bbe
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280140830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.1280140830
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.79973055
Short name T420
Test name
Test status
Simulation time 138678732 ps
CPU time 0.85 seconds
Started Aug 17 05:32:43 PM PDT 24
Finished Aug 17 05:32:44 PM PDT 24
Peak memory 196848 kb
Host smart-e3fa2001-4c43-41c2-9715-b1e47caa51de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79973055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.79973055
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.3033536511
Short name T633
Test name
Test status
Simulation time 75330642 ps
CPU time 1.05 seconds
Started Aug 17 05:32:46 PM PDT 24
Finished Aug 17 05:32:47 PM PDT 24
Peak memory 195940 kb
Host smart-0d5d1997-67c9-46a4-8d2c-0b7b6e84762d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033536511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.3033536511
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.1094888166
Short name T510
Test name
Test status
Simulation time 51966270 ps
CPU time 2.22 seconds
Started Aug 17 05:32:45 PM PDT 24
Finished Aug 17 05:32:47 PM PDT 24
Peak memory 198180 kb
Host smart-9116db1d-0165-4ac6-a691-f27425872b00
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094888166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.1094888166
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.466156027
Short name T351
Test name
Test status
Simulation time 186493686 ps
CPU time 1.96 seconds
Started Aug 17 05:32:43 PM PDT 24
Finished Aug 17 05:32:45 PM PDT 24
Peak memory 196384 kb
Host smart-732ab0df-0a45-4e03-b09a-81b5cc2a392e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466156027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.466156027
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.1982475131
Short name T197
Test name
Test status
Simulation time 147077134 ps
CPU time 0.88 seconds
Started Aug 17 05:32:35 PM PDT 24
Finished Aug 17 05:32:36 PM PDT 24
Peak memory 195964 kb
Host smart-81f74058-013b-4d61-9b3b-99df99647bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982475131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.1982475131
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.3398643870
Short name T234
Test name
Test status
Simulation time 58713141 ps
CPU time 0.63 seconds
Started Aug 17 05:32:35 PM PDT 24
Finished Aug 17 05:32:36 PM PDT 24
Peak memory 194428 kb
Host smart-6d389dc7-95c0-450e-b852-d0e160fc41b6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398643870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.3398643870
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.1340366544
Short name T231
Test name
Test status
Simulation time 95858822 ps
CPU time 1.38 seconds
Started Aug 17 05:32:44 PM PDT 24
Finished Aug 17 05:32:45 PM PDT 24
Peak memory 198164 kb
Host smart-20050804-5790-40d6-92ed-0c5e9ebd62fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340366544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.1340366544
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_smoke.789152538
Short name T53
Test name
Test status
Simulation time 35561197 ps
CPU time 1.12 seconds
Started Aug 17 05:32:37 PM PDT 24
Finished Aug 17 05:32:38 PM PDT 24
Peak memory 195808 kb
Host smart-26d7d6c1-3a8b-4f42-b175-54f5d83a721c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789152538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.789152538
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.4181161834
Short name T168
Test name
Test status
Simulation time 24798901 ps
CPU time 0.82 seconds
Started Aug 17 05:32:38 PM PDT 24
Finished Aug 17 05:32:39 PM PDT 24
Peak memory 196132 kb
Host smart-e9f2a3da-36fb-4ac0-8dbb-d03265ea6635
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181161834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.4181161834
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.3591024285
Short name T480
Test name
Test status
Simulation time 12258493102 ps
CPU time 123.68 seconds
Started Aug 17 05:32:44 PM PDT 24
Finished Aug 17 05:34:47 PM PDT 24
Peak memory 198360 kb
Host smart-c377a032-0c56-4821-95fe-3aee766e5aab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591024285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.3591024285
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_alert_test.2717929290
Short name T287
Test name
Test status
Simulation time 13274993 ps
CPU time 0.57 seconds
Started Aug 17 05:34:42 PM PDT 24
Finished Aug 17 05:34:43 PM PDT 24
Peak memory 194052 kb
Host smart-9bf753ae-9c77-4cb1-9469-9cb27debb586
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717929290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.2717929290
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.4053930965
Short name T452
Test name
Test status
Simulation time 17482021 ps
CPU time 0.65 seconds
Started Aug 17 05:34:43 PM PDT 24
Finished Aug 17 05:34:44 PM PDT 24
Peak memory 194236 kb
Host smart-d2da569b-6922-408b-bc5a-e104c6db1e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053930965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.4053930965
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.3174504836
Short name T526
Test name
Test status
Simulation time 210223520 ps
CPU time 5.46 seconds
Started Aug 17 05:34:39 PM PDT 24
Finished Aug 17 05:34:45 PM PDT 24
Peak memory 197092 kb
Host smart-2b311c58-2cec-419d-8eea-b62d2ebacb6f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174504836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.3174504836
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.541457402
Short name T485
Test name
Test status
Simulation time 135323496 ps
CPU time 0.93 seconds
Started Aug 17 05:34:42 PM PDT 24
Finished Aug 17 05:34:43 PM PDT 24
Peak memory 196704 kb
Host smart-960b3827-b770-4534-a6e4-b7de3b425555
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541457402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.541457402
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.1777096013
Short name T450
Test name
Test status
Simulation time 550988391 ps
CPU time 1.3 seconds
Started Aug 17 05:34:43 PM PDT 24
Finished Aug 17 05:34:44 PM PDT 24
Peak memory 197080 kb
Host smart-4bc2c41a-01f2-4368-9c91-e83ec3dbdab4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777096013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.1777096013
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.3869660787
Short name T606
Test name
Test status
Simulation time 130983405 ps
CPU time 2.65 seconds
Started Aug 17 05:34:42 PM PDT 24
Finished Aug 17 05:34:45 PM PDT 24
Peak memory 198232 kb
Host smart-cd1abd3d-5d7b-4641-bce0-f0302678b3a5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869660787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.3869660787
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.2450737954
Short name T163
Test name
Test status
Simulation time 852575842 ps
CPU time 2.77 seconds
Started Aug 17 05:34:43 PM PDT 24
Finished Aug 17 05:34:45 PM PDT 24
Peak memory 197244 kb
Host smart-7fb0cb33-1829-41c2-b249-b04141843e31
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450737954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.2450737954
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.4218378633
Short name T199
Test name
Test status
Simulation time 55689116 ps
CPU time 1.29 seconds
Started Aug 17 05:34:43 PM PDT 24
Finished Aug 17 05:34:44 PM PDT 24
Peak memory 195896 kb
Host smart-06bf49a0-95e7-4dbb-8eb0-4c9c3fd55159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218378633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.4218378633
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.944154863
Short name T247
Test name
Test status
Simulation time 17818402 ps
CPU time 0.78 seconds
Started Aug 17 05:34:43 PM PDT 24
Finished Aug 17 05:34:44 PM PDT 24
Peak memory 196400 kb
Host smart-05125536-0247-4e0f-bacd-460c49d52d86
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944154863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullup
_pulldown.944154863
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.3863954413
Short name T476
Test name
Test status
Simulation time 72168234 ps
CPU time 3.12 seconds
Started Aug 17 05:34:43 PM PDT 24
Finished Aug 17 05:34:46 PM PDT 24
Peak memory 197980 kb
Host smart-48c8fa79-e6f2-4e27-b94a-44969ab9f88f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863954413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.3863954413
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.469534848
Short name T434
Test name
Test status
Simulation time 90441345 ps
CPU time 0.89 seconds
Started Aug 17 05:34:44 PM PDT 24
Finished Aug 17 05:34:45 PM PDT 24
Peak memory 195848 kb
Host smart-52e60b6e-f678-4f4a-bcf6-fc26f3637ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469534848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.469534848
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.2224518377
Short name T121
Test name
Test status
Simulation time 284364503 ps
CPU time 1.25 seconds
Started Aug 17 05:34:42 PM PDT 24
Finished Aug 17 05:34:44 PM PDT 24
Peak memory 195864 kb
Host smart-a697428b-c71c-4035-9d26-7b1b036eb866
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224518377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.2224518377
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.223794952
Short name T658
Test name
Test status
Simulation time 933167937 ps
CPU time 21.94 seconds
Started Aug 17 05:34:42 PM PDT 24
Finished Aug 17 05:35:04 PM PDT 24
Peak memory 198204 kb
Host smart-7932652f-9ab6-4d1a-9f7b-592c167bfb3b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223794952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.g
pio_stress_all.223794952
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_alert_test.1155734204
Short name T144
Test name
Test status
Simulation time 15615332 ps
CPU time 0.6 seconds
Started Aug 17 05:34:52 PM PDT 24
Finished Aug 17 05:34:53 PM PDT 24
Peak memory 194044 kb
Host smart-9ad20251-cc21-49b7-a705-a790954302b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155734204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.1155734204
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.3739729666
Short name T235
Test name
Test status
Simulation time 61287967 ps
CPU time 0.68 seconds
Started Aug 17 05:34:53 PM PDT 24
Finished Aug 17 05:34:54 PM PDT 24
Peak memory 194256 kb
Host smart-0662f8eb-cc0f-428b-92cd-acdaaae588e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739729666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.3739729666
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.1991068276
Short name T381
Test name
Test status
Simulation time 1197982620 ps
CPU time 16.17 seconds
Started Aug 17 05:34:50 PM PDT 24
Finished Aug 17 05:35:07 PM PDT 24
Peak memory 196880 kb
Host smart-30188a49-03c4-4e5e-92fd-26d52316ef1f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991068276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.1991068276
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.4137893554
Short name T702
Test name
Test status
Simulation time 246826564 ps
CPU time 0.98 seconds
Started Aug 17 05:34:52 PM PDT 24
Finished Aug 17 05:34:54 PM PDT 24
Peak memory 198008 kb
Host smart-0a53e49a-2544-4642-a86c-f6c129d874e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137893554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.4137893554
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.1540477
Short name T659
Test name
Test status
Simulation time 338557490 ps
CPU time 1.15 seconds
Started Aug 17 05:34:52 PM PDT 24
Finished Aug 17 05:34:53 PM PDT 24
Peak memory 196132 kb
Host smart-9c1fc741-c56b-471b-9b3a-a3d646a9904d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.1540477
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.138674024
Short name T463
Test name
Test status
Simulation time 164348105 ps
CPU time 3.16 seconds
Started Aug 17 05:34:52 PM PDT 24
Finished Aug 17 05:34:55 PM PDT 24
Peak memory 198224 kb
Host smart-826d52c5-3671-436e-a76a-f813ac1d75b9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138674024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 31.gpio_intr_with_filter_rand_intr_event.138674024
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.3713596088
Short name T536
Test name
Test status
Simulation time 70949737 ps
CPU time 2.19 seconds
Started Aug 17 05:34:51 PM PDT 24
Finished Aug 17 05:34:54 PM PDT 24
Peak memory 196612 kb
Host smart-bd6c3c45-0718-450f-b928-3831f782fd58
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713596088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.3713596088
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.4166629024
Short name T432
Test name
Test status
Simulation time 28679322 ps
CPU time 0.74 seconds
Started Aug 17 05:34:43 PM PDT 24
Finished Aug 17 05:34:44 PM PDT 24
Peak memory 195524 kb
Host smart-9dbc868b-c201-4834-bec4-ef6ad949460d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166629024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.4166629024
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.3621562643
Short name T392
Test name
Test status
Simulation time 60118346 ps
CPU time 1.12 seconds
Started Aug 17 05:34:50 PM PDT 24
Finished Aug 17 05:34:51 PM PDT 24
Peak memory 196224 kb
Host smart-9e8930cc-00d4-4413-b92f-ba2873560a09
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621562643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.3621562643
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.2668919036
Short name T410
Test name
Test status
Simulation time 244834020 ps
CPU time 3.02 seconds
Started Aug 17 05:34:52 PM PDT 24
Finished Aug 17 05:34:55 PM PDT 24
Peak memory 198164 kb
Host smart-f155c0a2-f11e-4a84-bd2f-8b0074a61e52
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668919036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.2668919036
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.2471427553
Short name T158
Test name
Test status
Simulation time 159570762 ps
CPU time 1.2 seconds
Started Aug 17 05:34:43 PM PDT 24
Finished Aug 17 05:34:44 PM PDT 24
Peak memory 196936 kb
Host smart-e294c90e-196b-4f1b-b0f2-ab6b02e3213e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471427553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.2471427553
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.3185568267
Short name T437
Test name
Test status
Simulation time 249717662 ps
CPU time 1.12 seconds
Started Aug 17 05:34:43 PM PDT 24
Finished Aug 17 05:34:44 PM PDT 24
Peak memory 195896 kb
Host smart-d8ba21d0-2086-4e94-a826-dfb20f6e028b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185568267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.3185568267
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.1195663921
Short name T484
Test name
Test status
Simulation time 38290689049 ps
CPU time 207.93 seconds
Started Aug 17 05:34:51 PM PDT 24
Finished Aug 17 05:38:19 PM PDT 24
Peak memory 198320 kb
Host smart-efba29f5-d6db-4fec-a458-9aded53c5928
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195663921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.1195663921
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_alert_test.946090884
Short name T312
Test name
Test status
Simulation time 12518571 ps
CPU time 0.57 seconds
Started Aug 17 05:34:55 PM PDT 24
Finished Aug 17 05:34:56 PM PDT 24
Peak memory 193980 kb
Host smart-fea0b89c-3ca0-4259-a92c-97103cb76a0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946090884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.946090884
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.3177853444
Short name T442
Test name
Test status
Simulation time 134557149 ps
CPU time 0.65 seconds
Started Aug 17 05:34:53 PM PDT 24
Finished Aug 17 05:34:54 PM PDT 24
Peak memory 194864 kb
Host smart-c0c04808-b172-4604-81e0-ddceb82786a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177853444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.3177853444
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.747318336
Short name T205
Test name
Test status
Simulation time 379229850 ps
CPU time 19.48 seconds
Started Aug 17 05:34:53 PM PDT 24
Finished Aug 17 05:35:13 PM PDT 24
Peak memory 195692 kb
Host smart-b8b89112-6453-4187-903e-2b6bafb86f39
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747318336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stres
s.747318336
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.3681429637
Short name T616
Test name
Test status
Simulation time 140052469 ps
CPU time 0.93 seconds
Started Aug 17 05:34:57 PM PDT 24
Finished Aug 17 05:34:58 PM PDT 24
Peak memory 197276 kb
Host smart-ccaf358b-2b18-4252-b7a1-c2f9fb511a3e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681429637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.3681429637
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.916719905
Short name T325
Test name
Test status
Simulation time 175285577 ps
CPU time 1.19 seconds
Started Aug 17 05:34:55 PM PDT 24
Finished Aug 17 05:34:56 PM PDT 24
Peak memory 196156 kb
Host smart-06fc9bc8-2075-4c13-9f9b-bcacb72f8aa7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916719905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.916719905
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.1084420559
Short name T525
Test name
Test status
Simulation time 144762027 ps
CPU time 1.11 seconds
Started Aug 17 05:34:50 PM PDT 24
Finished Aug 17 05:34:52 PM PDT 24
Peak memory 197440 kb
Host smart-8a8e1f28-1ce0-461e-8dec-c1347f89ed3b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084420559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.1084420559
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.3232237004
Short name T426
Test name
Test status
Simulation time 49661510 ps
CPU time 1.22 seconds
Started Aug 17 05:34:50 PM PDT 24
Finished Aug 17 05:34:51 PM PDT 24
Peak memory 196744 kb
Host smart-c7029edd-675b-46c4-a5a6-f17718f9ca05
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232237004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.3232237004
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.759049510
Short name T290
Test name
Test status
Simulation time 39956253 ps
CPU time 0.88 seconds
Started Aug 17 05:34:50 PM PDT 24
Finished Aug 17 05:34:51 PM PDT 24
Peak memory 196056 kb
Host smart-a98b767d-178e-4546-b549-b5439d5e7e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759049510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.759049510
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.4233064469
Short name T566
Test name
Test status
Simulation time 157992513 ps
CPU time 1.2 seconds
Started Aug 17 05:34:50 PM PDT 24
Finished Aug 17 05:34:52 PM PDT 24
Peak memory 197136 kb
Host smart-05b0270f-7881-4678-9edb-507d2471001f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233064469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.4233064469
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.2938345314
Short name T447
Test name
Test status
Simulation time 137599244 ps
CPU time 2.31 seconds
Started Aug 17 05:34:49 PM PDT 24
Finished Aug 17 05:34:52 PM PDT 24
Peak memory 198112 kb
Host smart-212d52dd-588a-49fd-b020-9e189d584b55
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938345314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.2938345314
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.2400863901
Short name T339
Test name
Test status
Simulation time 62752026 ps
CPU time 1.03 seconds
Started Aug 17 05:34:52 PM PDT 24
Finished Aug 17 05:34:53 PM PDT 24
Peak memory 195852 kb
Host smart-6858f1f8-ba44-45e9-b8f1-d6152b0a605b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400863901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.2400863901
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.247231124
Short name T149
Test name
Test status
Simulation time 61926204 ps
CPU time 1.1 seconds
Started Aug 17 05:34:51 PM PDT 24
Finished Aug 17 05:34:53 PM PDT 24
Peak memory 195612 kb
Host smart-a9000477-87fa-4772-ad0c-bde23d78b1c9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247231124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.247231124
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.2261065002
Short name T413
Test name
Test status
Simulation time 13117557163 ps
CPU time 154.47 seconds
Started Aug 17 05:34:50 PM PDT 24
Finished Aug 17 05:37:25 PM PDT 24
Peak memory 198316 kb
Host smart-63e2644e-a6f3-4694-94a6-5609a99dcc35
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261065002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.2261065002
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_stress_all_with_rand_reset.2989500494
Short name T57
Test name
Test status
Simulation time 2311834890 ps
CPU time 17.92 seconds
Started Aug 17 05:34:51 PM PDT 24
Finished Aug 17 05:35:10 PM PDT 24
Peak memory 197916 kb
Host smart-004ef609-26cc-4ff0-a3ae-91b08284a5df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2989500494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_stress_all_with_rand_reset.2989500494
Directory /workspace/32.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.gpio_alert_test.1478877640
Short name T524
Test name
Test status
Simulation time 19570715 ps
CPU time 0.58 seconds
Started Aug 17 05:34:54 PM PDT 24
Finished Aug 17 05:34:55 PM PDT 24
Peak memory 195064 kb
Host smart-70485efc-3df9-48f4-9a96-8700461c3d8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478877640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.1478877640
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.1650547880
Short name T533
Test name
Test status
Simulation time 35376357 ps
CPU time 0.73 seconds
Started Aug 17 05:34:54 PM PDT 24
Finished Aug 17 05:34:55 PM PDT 24
Peak memory 195296 kb
Host smart-b7e37dc2-3ab1-491c-b147-4776d18e94dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650547880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.1650547880
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.3394260975
Short name T157
Test name
Test status
Simulation time 1016305664 ps
CPU time 23.23 seconds
Started Aug 17 05:34:52 PM PDT 24
Finished Aug 17 05:35:16 PM PDT 24
Peak memory 196964 kb
Host smart-677ce472-f495-4f4e-8beb-f8e7b2f3a772
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394260975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.3394260975
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.2525782984
Short name T428
Test name
Test status
Simulation time 52454981 ps
CPU time 0.77 seconds
Started Aug 17 05:34:56 PM PDT 24
Finished Aug 17 05:34:57 PM PDT 24
Peak memory 195936 kb
Host smart-3f7dd25d-23c1-4aa4-a4f3-631e8577bfd7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525782984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.2525782984
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.936835819
Short name T586
Test name
Test status
Simulation time 51976777 ps
CPU time 1.31 seconds
Started Aug 17 05:34:51 PM PDT 24
Finished Aug 17 05:34:52 PM PDT 24
Peak memory 198260 kb
Host smart-f9314cf0-a04a-4b56-8fe0-e302ed19f28a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936835819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.936835819
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.3848662300
Short name T241
Test name
Test status
Simulation time 74649113 ps
CPU time 1.62 seconds
Started Aug 17 05:34:49 PM PDT 24
Finished Aug 17 05:34:50 PM PDT 24
Peak memory 197072 kb
Host smart-1d7c4453-1821-4c72-9696-6a9a6f71bc91
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848662300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.3848662300
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.508251971
Short name T135
Test name
Test status
Simulation time 191251117 ps
CPU time 2.76 seconds
Started Aug 17 05:34:50 PM PDT 24
Finished Aug 17 05:34:53 PM PDT 24
Peak memory 197160 kb
Host smart-217ad726-70f3-4f55-8074-6b14ba44c532
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508251971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger.
508251971
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.4055146769
Short name T112
Test name
Test status
Simulation time 165651016 ps
CPU time 0.91 seconds
Started Aug 17 05:34:52 PM PDT 24
Finished Aug 17 05:34:53 PM PDT 24
Peak memory 195940 kb
Host smart-ac35e98e-6cde-4cef-a01e-396883c92966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055146769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.4055146769
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.605859606
Short name T464
Test name
Test status
Simulation time 15724966 ps
CPU time 0.66 seconds
Started Aug 17 05:34:57 PM PDT 24
Finished Aug 17 05:34:58 PM PDT 24
Peak memory 194468 kb
Host smart-dd3365fc-a669-4cf0-b558-318de0e01258
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605859606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullup
_pulldown.605859606
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.4069886130
Short name T269
Test name
Test status
Simulation time 700584590 ps
CPU time 3.11 seconds
Started Aug 17 05:34:52 PM PDT 24
Finished Aug 17 05:34:56 PM PDT 24
Peak memory 198148 kb
Host smart-07450946-4f50-487b-8473-4368bacc6a3c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069886130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.4069886130
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.737359986
Short name T708
Test name
Test status
Simulation time 169034028 ps
CPU time 1.32 seconds
Started Aug 17 05:34:51 PM PDT 24
Finished Aug 17 05:34:53 PM PDT 24
Peak memory 198144 kb
Host smart-8e8ea115-b981-40b7-ad7a-b204d3f748e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737359986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.737359986
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.2850108739
Short name T654
Test name
Test status
Simulation time 140592251 ps
CPU time 1.23 seconds
Started Aug 17 05:34:52 PM PDT 24
Finished Aug 17 05:34:54 PM PDT 24
Peak memory 196608 kb
Host smart-17978d11-34a7-421f-ac7b-c0dcfb680b25
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850108739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.2850108739
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.1359059709
Short name T352
Test name
Test status
Simulation time 66715661549 ps
CPU time 90.91 seconds
Started Aug 17 05:34:54 PM PDT 24
Finished Aug 17 05:36:25 PM PDT 24
Peak memory 198340 kb
Host smart-0fed7865-8150-4bfb-b392-6d29df2ae136
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359059709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.1359059709
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_alert_test.351520872
Short name T186
Test name
Test status
Simulation time 18123005 ps
CPU time 0.64 seconds
Started Aug 17 05:34:58 PM PDT 24
Finished Aug 17 05:34:59 PM PDT 24
Peak memory 194292 kb
Host smart-a10661b3-f106-4908-9f14-ed4b8d0d28f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351520872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.351520872
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.696366598
Short name T415
Test name
Test status
Simulation time 42147298 ps
CPU time 0.7 seconds
Started Aug 17 05:35:08 PM PDT 24
Finished Aug 17 05:35:09 PM PDT 24
Peak memory 194172 kb
Host smart-5cbed70a-5846-4bbd-b597-1017a25c47a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696366598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.696366598
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.2121760839
Short name T257
Test name
Test status
Simulation time 1019396167 ps
CPU time 27.83 seconds
Started Aug 17 05:34:57 PM PDT 24
Finished Aug 17 05:35:25 PM PDT 24
Peak memory 196912 kb
Host smart-fefca082-fa75-4989-abe1-18e2a0daad0a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121760839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.2121760839
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.3531925360
Short name T584
Test name
Test status
Simulation time 45933240 ps
CPU time 0.81 seconds
Started Aug 17 05:34:59 PM PDT 24
Finished Aug 17 05:35:00 PM PDT 24
Peak memory 195964 kb
Host smart-27bf1456-e017-4d4e-a0cd-2f5f2fda67bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531925360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.3531925360
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.3273965478
Short name T285
Test name
Test status
Simulation time 23540901 ps
CPU time 0.65 seconds
Started Aug 17 05:35:08 PM PDT 24
Finished Aug 17 05:35:09 PM PDT 24
Peak memory 194208 kb
Host smart-48c0c691-db00-417d-bad7-80f21a4a5280
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273965478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.3273965478
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.2722685287
Short name T297
Test name
Test status
Simulation time 84179429 ps
CPU time 3.05 seconds
Started Aug 17 05:34:58 PM PDT 24
Finished Aug 17 05:35:01 PM PDT 24
Peak memory 198192 kb
Host smart-554bf9c0-ff95-424f-bd82-8a012065ef5f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722685287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.2722685287
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.2378699549
Short name T329
Test name
Test status
Simulation time 81675950 ps
CPU time 2.38 seconds
Started Aug 17 05:34:58 PM PDT 24
Finished Aug 17 05:35:01 PM PDT 24
Peak memory 197420 kb
Host smart-c5a89600-782d-472f-9b5e-542e51aa1bfb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378699549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.2378699549
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.1135859155
Short name T118
Test name
Test status
Simulation time 31277390 ps
CPU time 0.79 seconds
Started Aug 17 05:34:53 PM PDT 24
Finished Aug 17 05:34:54 PM PDT 24
Peak memory 195672 kb
Host smart-78caa2a4-7d07-43dc-9bc9-017353f7341e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135859155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.1135859155
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.3968954898
Short name T63
Test name
Test status
Simulation time 31782162 ps
CPU time 1.04 seconds
Started Aug 17 05:34:56 PM PDT 24
Finished Aug 17 05:34:57 PM PDT 24
Peak memory 196940 kb
Host smart-9e69689f-3a74-4af3-9f6d-5bca4e0b2b2e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968954898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.3968954898
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.2428391662
Short name T552
Test name
Test status
Simulation time 89774461 ps
CPU time 1.55 seconds
Started Aug 17 05:35:08 PM PDT 24
Finished Aug 17 05:35:09 PM PDT 24
Peak memory 197948 kb
Host smart-dc2d6309-fe3d-4247-871e-3a766b022354
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428391662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.2428391662
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.1655301303
Short name T615
Test name
Test status
Simulation time 268282168 ps
CPU time 1.37 seconds
Started Aug 17 05:34:57 PM PDT 24
Finished Aug 17 05:34:58 PM PDT 24
Peak memory 195720 kb
Host smart-37ecbe4a-647a-4396-a7e6-d3209657fa47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655301303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.1655301303
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.2877354657
Short name T634
Test name
Test status
Simulation time 89670700 ps
CPU time 1.39 seconds
Started Aug 17 05:34:51 PM PDT 24
Finished Aug 17 05:34:53 PM PDT 24
Peak memory 196848 kb
Host smart-239beb96-b216-4735-884e-292eac65bc01
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877354657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.2877354657
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.1674503123
Short name T8
Test name
Test status
Simulation time 70553232249 ps
CPU time 215.18 seconds
Started Aug 17 05:35:02 PM PDT 24
Finished Aug 17 05:38:37 PM PDT 24
Peak memory 198340 kb
Host smart-6db0c51a-0089-4c0e-9032-204dbf3e01ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674503123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.1674503123
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_alert_test.3629562529
Short name T564
Test name
Test status
Simulation time 27219161 ps
CPU time 0.57 seconds
Started Aug 17 05:34:57 PM PDT 24
Finished Aug 17 05:34:58 PM PDT 24
Peak memory 194244 kb
Host smart-166c8bf3-f04d-4161-927d-ac3ac2dd414f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629562529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.3629562529
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.520168377
Short name T266
Test name
Test status
Simulation time 465458952 ps
CPU time 0.8 seconds
Started Aug 17 05:35:00 PM PDT 24
Finished Aug 17 05:35:00 PM PDT 24
Peak memory 196540 kb
Host smart-49c6d58a-5663-43c4-af13-438f1168ee57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520168377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.520168377
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.1095897163
Short name T506
Test name
Test status
Simulation time 519343455 ps
CPU time 18.04 seconds
Started Aug 17 05:34:59 PM PDT 24
Finished Aug 17 05:35:17 PM PDT 24
Peak memory 195652 kb
Host smart-3137bd44-0f03-44ba-be00-71e5a06790e3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095897163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.1095897163
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.2345482541
Short name T568
Test name
Test status
Simulation time 208277809 ps
CPU time 0.89 seconds
Started Aug 17 05:34:58 PM PDT 24
Finished Aug 17 05:34:58 PM PDT 24
Peak memory 197336 kb
Host smart-1058943c-61c1-46d4-a7d8-2126e61c4a48
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345482541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.2345482541
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.2967433594
Short name T355
Test name
Test status
Simulation time 78975073 ps
CPU time 1.19 seconds
Started Aug 17 05:34:58 PM PDT 24
Finished Aug 17 05:34:59 PM PDT 24
Peak memory 196048 kb
Host smart-78bb3452-dc13-498f-a7f2-033949058f1e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967433594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.2967433594
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.1521184636
Short name T652
Test name
Test status
Simulation time 405998191 ps
CPU time 1.45 seconds
Started Aug 17 05:35:00 PM PDT 24
Finished Aug 17 05:35:02 PM PDT 24
Peak memory 196888 kb
Host smart-a82a13e7-b467-4824-840d-08ede1051adc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521184636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.1521184636
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.3593629168
Short name T216
Test name
Test status
Simulation time 140604822 ps
CPU time 2.66 seconds
Started Aug 17 05:35:08 PM PDT 24
Finished Aug 17 05:35:11 PM PDT 24
Peak memory 197156 kb
Host smart-e112fcba-110c-4aa4-8f49-b135249ec02f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593629168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.3593629168
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.3353472605
Short name T100
Test name
Test status
Simulation time 69161756 ps
CPU time 1.2 seconds
Started Aug 17 05:35:01 PM PDT 24
Finished Aug 17 05:35:02 PM PDT 24
Peak memory 197096 kb
Host smart-be79ab44-8a4d-4337-921b-bac0b5fb70b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353472605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.3353472605
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.1247564805
Short name T565
Test name
Test status
Simulation time 18289987 ps
CPU time 0.75 seconds
Started Aug 17 05:34:59 PM PDT 24
Finished Aug 17 05:35:00 PM PDT 24
Peak memory 195380 kb
Host smart-5f9863ed-d731-4b06-967c-e83ffdeefdd4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247564805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.1247564805
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.1115883691
Short name T302
Test name
Test status
Simulation time 115882561 ps
CPU time 2.91 seconds
Started Aug 17 05:34:58 PM PDT 24
Finished Aug 17 05:35:01 PM PDT 24
Peak memory 198056 kb
Host smart-00a8faad-9543-4b60-8b7f-113e66da22fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115883691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.1115883691
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.3527758607
Short name T238
Test name
Test status
Simulation time 442304675 ps
CPU time 0.96 seconds
Started Aug 17 05:34:56 PM PDT 24
Finished Aug 17 05:34:57 PM PDT 24
Peak memory 196720 kb
Host smart-38ab30bf-9592-4a99-9748-e1cf83bf69da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527758607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.3527758607
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.3100537386
Short name T273
Test name
Test status
Simulation time 56054634 ps
CPU time 1.04 seconds
Started Aug 17 05:34:57 PM PDT 24
Finished Aug 17 05:34:58 PM PDT 24
Peak memory 195900 kb
Host smart-01ce8c90-b0aa-4821-b038-8fad08f0932e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100537386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.3100537386
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.192467457
Short name T365
Test name
Test status
Simulation time 4098885006 ps
CPU time 50.78 seconds
Started Aug 17 05:34:59 PM PDT 24
Finished Aug 17 05:35:50 PM PDT 24
Peak memory 198276 kb
Host smart-ccd26ab3-82a9-48be-bff3-2869e4b80694
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192467457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.g
pio_stress_all.192467457
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_stress_all_with_rand_reset.1797397821
Short name T59
Test name
Test status
Simulation time 7082161770 ps
CPU time 81.73 seconds
Started Aug 17 05:35:08 PM PDT 24
Finished Aug 17 05:36:30 PM PDT 24
Peak memory 198436 kb
Host smart-85dead33-d5d0-43d5-a3dc-5a605b5c2273
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1797397821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_stress_all_with_rand_reset.1797397821
Directory /workspace/35.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.gpio_alert_test.1000228753
Short name T645
Test name
Test status
Simulation time 12114191 ps
CPU time 0.55 seconds
Started Aug 17 05:35:04 PM PDT 24
Finished Aug 17 05:35:05 PM PDT 24
Peak memory 194028 kb
Host smart-bf2ebf8e-c998-47f8-9e6c-e2069c72f5fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000228753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.1000228753
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.662371756
Short name T576
Test name
Test status
Simulation time 82816565 ps
CPU time 0.69 seconds
Started Aug 17 05:35:01 PM PDT 24
Finished Aug 17 05:35:02 PM PDT 24
Peak memory 194144 kb
Host smart-8920f11a-5354-425c-94f7-d3d4d86a9f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662371756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.662371756
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.2451937332
Short name T265
Test name
Test status
Simulation time 113470184 ps
CPU time 5.65 seconds
Started Aug 17 05:34:57 PM PDT 24
Finished Aug 17 05:35:03 PM PDT 24
Peak memory 196904 kb
Host smart-ea89a4ba-2206-4e55-a1fe-7e3f9b00fc33
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451937332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.2451937332
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.2739701502
Short name T679
Test name
Test status
Simulation time 101407284 ps
CPU time 0.73 seconds
Started Aug 17 05:35:08 PM PDT 24
Finished Aug 17 05:35:09 PM PDT 24
Peak memory 195864 kb
Host smart-e7511c1f-4351-4bd4-b379-373056b82683
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739701502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.2739701502
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.1594384760
Short name T388
Test name
Test status
Simulation time 915782138 ps
CPU time 1.18 seconds
Started Aug 17 05:34:58 PM PDT 24
Finished Aug 17 05:35:00 PM PDT 24
Peak memory 196352 kb
Host smart-e2e22457-2d83-4f75-bf07-ace72aaf1639
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594384760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.1594384760
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.2852223831
Short name T64
Test name
Test status
Simulation time 356481908 ps
CPU time 3.11 seconds
Started Aug 17 05:34:58 PM PDT 24
Finished Aug 17 05:35:01 PM PDT 24
Peak memory 196588 kb
Host smart-8a7c3d8c-59c3-40e7-bd77-3d7eec6a4daa
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852223831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.2852223831
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.861982483
Short name T563
Test name
Test status
Simulation time 110489817 ps
CPU time 2.44 seconds
Started Aug 17 05:35:02 PM PDT 24
Finished Aug 17 05:35:04 PM PDT 24
Peak memory 195976 kb
Host smart-0fe9c706-d464-424b-81fb-a9e63f7f37cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861982483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger.
861982483
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.3419158619
Short name T102
Test name
Test status
Simulation time 227567372 ps
CPU time 1.19 seconds
Started Aug 17 05:34:58 PM PDT 24
Finished Aug 17 05:34:59 PM PDT 24
Peak memory 196200 kb
Host smart-f83e5843-a351-4fb2-8302-3a49156b7d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419158619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.3419158619
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.4109674135
Short name T672
Test name
Test status
Simulation time 23972067 ps
CPU time 0.69 seconds
Started Aug 17 05:34:58 PM PDT 24
Finished Aug 17 05:34:59 PM PDT 24
Peak memory 194360 kb
Host smart-fed234a4-a0c5-4548-a7e0-7e491003dda1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109674135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.4109674135
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.3664841288
Short name T638
Test name
Test status
Simulation time 305941666 ps
CPU time 3.43 seconds
Started Aug 17 05:35:06 PM PDT 24
Finished Aug 17 05:35:10 PM PDT 24
Peak memory 198196 kb
Host smart-e57c68b6-9b7f-431f-9345-53fe6ed118c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664841288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.3664841288
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.293429166
Short name T192
Test name
Test status
Simulation time 48351845 ps
CPU time 0.75 seconds
Started Aug 17 05:34:59 PM PDT 24
Finished Aug 17 05:35:00 PM PDT 24
Peak memory 195428 kb
Host smart-171cd0de-3d61-4451-b1f2-327d731360e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293429166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.293429166
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.2441584463
Short name T344
Test name
Test status
Simulation time 40436752 ps
CPU time 0.9 seconds
Started Aug 17 05:34:57 PM PDT 24
Finished Aug 17 05:34:58 PM PDT 24
Peak memory 195864 kb
Host smart-968ac637-eaa9-4614-b1c3-854c15e9a10c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441584463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.2441584463
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.2346788125
Short name T295
Test name
Test status
Simulation time 170734745304 ps
CPU time 182.59 seconds
Started Aug 17 05:35:11 PM PDT 24
Finished Aug 17 05:38:13 PM PDT 24
Peak memory 198332 kb
Host smart-e1a44583-db83-4a22-b78b-e909a5dc0937
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346788125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.2346788125
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_alert_test.381482919
Short name T520
Test name
Test status
Simulation time 29533343 ps
CPU time 0.59 seconds
Started Aug 17 05:35:06 PM PDT 24
Finished Aug 17 05:35:06 PM PDT 24
Peak memory 194004 kb
Host smart-9aefde1f-0213-46d7-a631-b5797e96ca3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381482919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.381482919
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.1037933228
Short name T390
Test name
Test status
Simulation time 32427651 ps
CPU time 0.89 seconds
Started Aug 17 05:35:08 PM PDT 24
Finished Aug 17 05:35:09 PM PDT 24
Peak memory 196208 kb
Host smart-1663d930-9264-432c-bbb3-05d7e8595239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037933228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.1037933228
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.1839561775
Short name T270
Test name
Test status
Simulation time 339470004 ps
CPU time 8.14 seconds
Started Aug 17 05:35:04 PM PDT 24
Finished Aug 17 05:35:13 PM PDT 24
Peak memory 196960 kb
Host smart-550865bc-130e-49d2-84bb-26f219a66f95
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839561775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stre
ss.1839561775
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.2485485279
Short name T314
Test name
Test status
Simulation time 120453815 ps
CPU time 1.07 seconds
Started Aug 17 05:35:11 PM PDT 24
Finished Aug 17 05:35:12 PM PDT 24
Peak memory 197868 kb
Host smart-76a78e75-1511-4cf7-9d1b-459c2918d97e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485485279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.2485485279
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.3154891807
Short name T323
Test name
Test status
Simulation time 54995040 ps
CPU time 0.91 seconds
Started Aug 17 05:35:05 PM PDT 24
Finished Aug 17 05:35:06 PM PDT 24
Peak memory 196200 kb
Host smart-a3f03a91-83d4-49d5-b7ea-307a92c936a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154891807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.3154891807
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.4048138654
Short name T187
Test name
Test status
Simulation time 44313432 ps
CPU time 1.22 seconds
Started Aug 17 05:35:04 PM PDT 24
Finished Aug 17 05:35:05 PM PDT 24
Peak memory 196532 kb
Host smart-8863442c-bdfa-41c0-b709-68a8550ccaa4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048138654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.4048138654
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.4101335331
Short name T587
Test name
Test status
Simulation time 109505737 ps
CPU time 2 seconds
Started Aug 17 05:35:10 PM PDT 24
Finished Aug 17 05:35:12 PM PDT 24
Peak memory 196072 kb
Host smart-32321054-632d-42dc-bcbd-78e5e1cd5513
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101335331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.4101335331
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.4022393188
Short name T581
Test name
Test status
Simulation time 53741908 ps
CPU time 1.07 seconds
Started Aug 17 05:35:05 PM PDT 24
Finished Aug 17 05:35:06 PM PDT 24
Peak memory 196276 kb
Host smart-bf98b00d-3790-4079-bbbe-112f685a9cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022393188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.4022393188
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.1035170829
Short name T382
Test name
Test status
Simulation time 67120185 ps
CPU time 0.83 seconds
Started Aug 17 05:35:06 PM PDT 24
Finished Aug 17 05:35:07 PM PDT 24
Peak memory 196588 kb
Host smart-017ae16b-efc0-482e-b0c6-47d04f7ccbb9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035170829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.1035170829
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.1660878891
Short name T522
Test name
Test status
Simulation time 399819199 ps
CPU time 4.58 seconds
Started Aug 17 05:35:04 PM PDT 24
Finished Aug 17 05:35:09 PM PDT 24
Peak memory 198084 kb
Host smart-6ba5d6fa-7b6c-48b4-a4fa-649924fee5b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660878891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.1660878891
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.152228256
Short name T183
Test name
Test status
Simulation time 38068630 ps
CPU time 1.16 seconds
Started Aug 17 05:35:05 PM PDT 24
Finished Aug 17 05:35:06 PM PDT 24
Peak memory 198092 kb
Host smart-c9721e1e-42fd-4810-bd86-e275d26d5dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152228256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.152228256
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.926335324
Short name T288
Test name
Test status
Simulation time 353728701 ps
CPU time 0.92 seconds
Started Aug 17 05:35:08 PM PDT 24
Finished Aug 17 05:35:09 PM PDT 24
Peak memory 195408 kb
Host smart-5490928f-f5d6-40a3-a771-e27371ef641b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926335324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.926335324
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.394959309
Short name T130
Test name
Test status
Simulation time 16001184595 ps
CPU time 206.52 seconds
Started Aug 17 05:35:08 PM PDT 24
Finished Aug 17 05:38:34 PM PDT 24
Peak memory 198340 kb
Host smart-fa9e5557-a622-4785-bf53-0651e2d83343
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394959309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.g
pio_stress_all.394959309
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_alert_test.2600159676
Short name T626
Test name
Test status
Simulation time 21256959 ps
CPU time 0.59 seconds
Started Aug 17 05:35:15 PM PDT 24
Finished Aug 17 05:35:16 PM PDT 24
Peak memory 194692 kb
Host smart-79260c0a-e6d5-419f-8970-27f8e6f5ea22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600159676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.2600159676
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.3625847833
Short name T618
Test name
Test status
Simulation time 36362851 ps
CPU time 0.85 seconds
Started Aug 17 05:35:05 PM PDT 24
Finished Aug 17 05:35:06 PM PDT 24
Peak memory 196444 kb
Host smart-f7698271-ec0d-4bfb-92a7-f6de79231787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625847833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.3625847833
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.332555944
Short name T490
Test name
Test status
Simulation time 130260015 ps
CPU time 5.3 seconds
Started Aug 17 05:35:14 PM PDT 24
Finished Aug 17 05:35:19 PM PDT 24
Peak memory 198156 kb
Host smart-3706b03a-173d-4206-881e-64d710d46f67
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332555944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stres
s.332555944
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.1474619994
Short name T173
Test name
Test status
Simulation time 27976739 ps
CPU time 0.71 seconds
Started Aug 17 05:35:15 PM PDT 24
Finished Aug 17 05:35:16 PM PDT 24
Peak memory 194752 kb
Host smart-94171dae-b251-4a3d-8da6-9bc9dea18419
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474619994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.1474619994
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.3931961729
Short name T405
Test name
Test status
Simulation time 89113116 ps
CPU time 0.84 seconds
Started Aug 17 05:35:12 PM PDT 24
Finished Aug 17 05:35:13 PM PDT 24
Peak memory 196568 kb
Host smart-cfb72672-98ff-4be7-acbd-4d564033c4b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931961729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.3931961729
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.368272211
Short name T631
Test name
Test status
Simulation time 52814152 ps
CPU time 1.15 seconds
Started Aug 17 05:35:14 PM PDT 24
Finished Aug 17 05:35:15 PM PDT 24
Peak memory 198016 kb
Host smart-11fa8834-1c01-44d6-8bd4-2bc684b766ea
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368272211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 38.gpio_intr_with_filter_rand_intr_event.368272211
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.2329433233
Short name T499
Test name
Test status
Simulation time 31608921 ps
CPU time 1.07 seconds
Started Aug 17 05:35:19 PM PDT 24
Finished Aug 17 05:35:21 PM PDT 24
Peak memory 195908 kb
Host smart-73d5bac5-6e49-4d98-bf45-2de02dea71b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329433233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.2329433233
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.811472558
Short name T18
Test name
Test status
Simulation time 289054751 ps
CPU time 1.25 seconds
Started Aug 17 05:35:04 PM PDT 24
Finished Aug 17 05:35:05 PM PDT 24
Peak memory 197136 kb
Host smart-1e21777b-a895-4500-a6e4-4ca3678d55a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811472558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.811472558
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.468261593
Short name T454
Test name
Test status
Simulation time 123906399 ps
CPU time 0.83 seconds
Started Aug 17 05:35:07 PM PDT 24
Finished Aug 17 05:35:08 PM PDT 24
Peak memory 196232 kb
Host smart-55a3c10f-1df6-46ce-a722-d8f5a90d788c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468261593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullup
_pulldown.468261593
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.3642968405
Short name T449
Test name
Test status
Simulation time 61875530 ps
CPU time 1.08 seconds
Started Aug 17 05:35:11 PM PDT 24
Finished Aug 17 05:35:12 PM PDT 24
Peak memory 197964 kb
Host smart-e45f0732-18f5-4aed-b50d-be6a2d364ae2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642968405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.3642968405
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.188377962
Short name T397
Test name
Test status
Simulation time 122664480 ps
CPU time 1.09 seconds
Started Aug 17 05:35:07 PM PDT 24
Finished Aug 17 05:35:08 PM PDT 24
Peak memory 195688 kb
Host smart-fe38b4d7-0abe-4202-8a7e-968859f6abdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188377962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.188377962
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.328069111
Short name T528
Test name
Test status
Simulation time 58194176 ps
CPU time 1.13 seconds
Started Aug 17 05:35:06 PM PDT 24
Finished Aug 17 05:35:07 PM PDT 24
Peak memory 196712 kb
Host smart-be71d792-def9-46b8-8be5-f44ad40d409e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328069111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.328069111
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.747161690
Short name T372
Test name
Test status
Simulation time 14445829638 ps
CPU time 158.59 seconds
Started Aug 17 05:35:11 PM PDT 24
Finished Aug 17 05:37:50 PM PDT 24
Peak memory 198300 kb
Host smart-e8cf89e6-1b76-43c8-8be7-4397c22b385b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747161690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.g
pio_stress_all.747161690
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_alert_test.2993824683
Short name T317
Test name
Test status
Simulation time 21732275 ps
CPU time 0.57 seconds
Started Aug 17 05:35:12 PM PDT 24
Finished Aug 17 05:35:13 PM PDT 24
Peak memory 194056 kb
Host smart-1df0b46c-5cc3-4382-a346-7f8615f56f44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993824683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.2993824683
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.2335665836
Short name T286
Test name
Test status
Simulation time 20086352 ps
CPU time 0.76 seconds
Started Aug 17 05:35:16 PM PDT 24
Finished Aug 17 05:35:16 PM PDT 24
Peak memory 195412 kb
Host smart-b871e073-d79c-45a2-9c8b-805ce5d80a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335665836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.2335665836
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.1976162098
Short name T400
Test name
Test status
Simulation time 344255847 ps
CPU time 17.52 seconds
Started Aug 17 05:35:18 PM PDT 24
Finished Aug 17 05:35:36 PM PDT 24
Peak memory 197240 kb
Host smart-4af1870d-72d7-4fa6-8245-0b11ade1ff0c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976162098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.1976162098
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.2838953052
Short name T396
Test name
Test status
Simulation time 278077392 ps
CPU time 0.94 seconds
Started Aug 17 05:35:17 PM PDT 24
Finished Aug 17 05:35:18 PM PDT 24
Peak memory 198172 kb
Host smart-73e1bf27-9b8c-4912-b104-d04a1d46d1dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838953052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.2838953052
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.2924835713
Short name T583
Test name
Test status
Simulation time 66872752 ps
CPU time 0.78 seconds
Started Aug 17 05:35:18 PM PDT 24
Finished Aug 17 05:35:19 PM PDT 24
Peak memory 195696 kb
Host smart-30320390-96b5-4b4d-b3cd-87689347b813
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924835713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.2924835713
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.2192196691
Short name T324
Test name
Test status
Simulation time 130928111 ps
CPU time 2.65 seconds
Started Aug 17 05:35:20 PM PDT 24
Finished Aug 17 05:35:23 PM PDT 24
Peak memory 198228 kb
Host smart-92a06ab4-284b-4a50-8f37-3beda3f73edf
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192196691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.2192196691
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.1147599913
Short name T601
Test name
Test status
Simulation time 52871553 ps
CPU time 1.65 seconds
Started Aug 17 05:35:18 PM PDT 24
Finished Aug 17 05:35:20 PM PDT 24
Peak memory 196984 kb
Host smart-b48ce11b-8075-4324-81e4-8b4cd69952fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147599913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.1147599913
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.2207121915
Short name T147
Test name
Test status
Simulation time 25537442 ps
CPU time 0.79 seconds
Started Aug 17 05:35:16 PM PDT 24
Finished Aug 17 05:35:17 PM PDT 24
Peak memory 195560 kb
Host smart-c5c58d02-01e1-4d75-b2ca-69367ebfd17c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207121915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.2207121915
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.2599144718
Short name T164
Test name
Test status
Simulation time 40609493 ps
CPU time 0.96 seconds
Started Aug 17 05:35:16 PM PDT 24
Finished Aug 17 05:35:17 PM PDT 24
Peak memory 195864 kb
Host smart-c3763f82-bb9c-4421-9c93-bc3744ef9a7d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599144718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.2599144718
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.259698789
Short name T379
Test name
Test status
Simulation time 73551826 ps
CPU time 3.31 seconds
Started Aug 17 05:35:13 PM PDT 24
Finished Aug 17 05:35:16 PM PDT 24
Peak memory 198128 kb
Host smart-c0ce9a74-23c4-4dc3-acba-9356282eaa67
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259698789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ran
dom_long_reg_writes_reg_reads.259698789
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.1207124388
Short name T402
Test name
Test status
Simulation time 77747337 ps
CPU time 1.5 seconds
Started Aug 17 05:35:16 PM PDT 24
Finished Aug 17 05:35:18 PM PDT 24
Peak memory 196856 kb
Host smart-274abf73-c5e8-4bb3-bf31-171f41979d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207124388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.1207124388
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.2565199942
Short name T393
Test name
Test status
Simulation time 40829169 ps
CPU time 0.96 seconds
Started Aug 17 05:35:12 PM PDT 24
Finished Aug 17 05:35:13 PM PDT 24
Peak memory 196612 kb
Host smart-87dadb45-63e2-46c6-81ee-5ad26a232f96
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565199942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.2565199942
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.398790959
Short name T471
Test name
Test status
Simulation time 12989743213 ps
CPU time 176.28 seconds
Started Aug 17 05:35:18 PM PDT 24
Finished Aug 17 05:38:14 PM PDT 24
Peak memory 198420 kb
Host smart-d24318d6-e399-43f8-b24b-2db96b862c60
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398790959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.g
pio_stress_all.398790959
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_stress_all_with_rand_reset.2314683654
Short name T54
Test name
Test status
Simulation time 7973828502 ps
CPU time 134.49 seconds
Started Aug 17 05:35:16 PM PDT 24
Finished Aug 17 05:37:30 PM PDT 24
Peak memory 198540 kb
Host smart-09f25239-a4c4-4e6f-9742-4d6d42eda930
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2314683654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_stress_all_with_rand_reset.2314683654
Directory /workspace/39.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.gpio_alert_test.2650731245
Short name T684
Test name
Test status
Simulation time 41137181 ps
CPU time 0.54 seconds
Started Aug 17 05:32:54 PM PDT 24
Finished Aug 17 05:32:55 PM PDT 24
Peak memory 194068 kb
Host smart-7883aeb4-2454-4ef0-81cc-f919b592dc6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650731245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.2650731245
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.629124971
Short name T550
Test name
Test status
Simulation time 72472587 ps
CPU time 0.89 seconds
Started Aug 17 05:32:44 PM PDT 24
Finished Aug 17 05:32:45 PM PDT 24
Peak memory 197316 kb
Host smart-ee22ae2b-bafb-4eb0-b931-316959e2f41b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629124971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.629124971
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.1876007571
Short name T218
Test name
Test status
Simulation time 1732261969 ps
CPU time 13.02 seconds
Started Aug 17 05:32:53 PM PDT 24
Finished Aug 17 05:33:06 PM PDT 24
Peak memory 198116 kb
Host smart-eba3b663-88df-48fe-8ac6-c0565836fa54
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876007571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.1876007571
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.1280802205
Short name T298
Test name
Test status
Simulation time 349582965 ps
CPU time 1.01 seconds
Started Aug 17 05:32:51 PM PDT 24
Finished Aug 17 05:32:53 PM PDT 24
Peak memory 196456 kb
Host smart-874ac668-a62d-4293-84ba-908b9b1b728b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280802205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.1280802205
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.3682435768
Short name T466
Test name
Test status
Simulation time 46949613 ps
CPU time 1.15 seconds
Started Aug 17 05:32:53 PM PDT 24
Finished Aug 17 05:32:54 PM PDT 24
Peak memory 196724 kb
Host smart-bd6c16ce-7363-4359-9d35-ca906cebea72
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682435768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.3682435768
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.915156777
Short name T567
Test name
Test status
Simulation time 40536718 ps
CPU time 1.37 seconds
Started Aug 17 05:32:53 PM PDT 24
Finished Aug 17 05:32:54 PM PDT 24
Peak memory 196648 kb
Host smart-d8e06a2d-cfb0-49bf-9b54-d62adbe27212
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915156777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.915156777
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.1503615029
Short name T277
Test name
Test status
Simulation time 60667395 ps
CPU time 1.24 seconds
Started Aug 17 05:32:43 PM PDT 24
Finished Aug 17 05:32:45 PM PDT 24
Peak memory 197184 kb
Host smart-92994451-37fc-49d9-83a6-97be74ea80b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503615029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.1503615029
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.2012018949
Short name T219
Test name
Test status
Simulation time 126611389 ps
CPU time 1.28 seconds
Started Aug 17 05:32:44 PM PDT 24
Finished Aug 17 05:32:46 PM PDT 24
Peak memory 197204 kb
Host smart-aea7d4a5-d818-43aa-91bf-2d15e09f01eb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012018949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.2012018949
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.3094335170
Short name T51
Test name
Test status
Simulation time 45822657 ps
CPU time 2.1 seconds
Started Aug 17 05:32:51 PM PDT 24
Finished Aug 17 05:32:53 PM PDT 24
Peak memory 198164 kb
Host smart-01f2c86c-092c-46f0-b91b-7db8d0020ceb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094335170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.3094335170
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.2129009262
Short name T35
Test name
Test status
Simulation time 333142870 ps
CPU time 0.91 seconds
Started Aug 17 05:32:55 PM PDT 24
Finished Aug 17 05:32:56 PM PDT 24
Peak memory 215096 kb
Host smart-fb74ca1f-823c-4067-9d4b-09f9262463d7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129009262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.2129009262
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.1352324261
Short name T185
Test name
Test status
Simulation time 171224051 ps
CPU time 1.29 seconds
Started Aug 17 05:32:42 PM PDT 24
Finished Aug 17 05:32:43 PM PDT 24
Peak memory 198156 kb
Host smart-3bc565b2-f7d6-4fd6-8688-b0403acb2972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352324261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.1352324261
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.3924318648
Short name T412
Test name
Test status
Simulation time 76595660 ps
CPU time 1.25 seconds
Started Aug 17 05:32:44 PM PDT 24
Finished Aug 17 05:32:45 PM PDT 24
Peak memory 196720 kb
Host smart-88970f00-711d-4a7f-b0e1-6ef1ca042a24
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924318648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.3924318648
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.1196561769
Short name T622
Test name
Test status
Simulation time 7005128403 ps
CPU time 161.83 seconds
Started Aug 17 05:32:54 PM PDT 24
Finished Aug 17 05:35:36 PM PDT 24
Peak memory 198272 kb
Host smart-4d2cacc9-e517-41d1-8bef-17916dd8bdb4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196561769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.1196561769
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_alert_test.2622596467
Short name T597
Test name
Test status
Simulation time 107194414 ps
CPU time 0.59 seconds
Started Aug 17 05:35:14 PM PDT 24
Finished Aug 17 05:35:14 PM PDT 24
Peak memory 194976 kb
Host smart-d13e6e23-0d2b-4cad-86f5-57e1114ffd05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622596467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.2622596467
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.3667886029
Short name T152
Test name
Test status
Simulation time 23099834 ps
CPU time 0.67 seconds
Started Aug 17 05:35:16 PM PDT 24
Finished Aug 17 05:35:16 PM PDT 24
Peak memory 194912 kb
Host smart-fbbd7763-a85a-4eea-859c-3893bb604726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667886029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.3667886029
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.2651923398
Short name T541
Test name
Test status
Simulation time 1011732096 ps
CPU time 16.45 seconds
Started Aug 17 05:35:13 PM PDT 24
Finished Aug 17 05:35:29 PM PDT 24
Peak memory 197064 kb
Host smart-ad6d2dc8-fdff-4885-9b65-8a1f086584a3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651923398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.2651923398
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.711184043
Short name T465
Test name
Test status
Simulation time 71409194 ps
CPU time 0.93 seconds
Started Aug 17 05:35:12 PM PDT 24
Finished Aug 17 05:35:13 PM PDT 24
Peak memory 197764 kb
Host smart-2c4754a9-9056-4c42-941e-e588a00b4b1e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711184043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.711184043
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.129629777
Short name T527
Test name
Test status
Simulation time 124763245 ps
CPU time 0.83 seconds
Started Aug 17 05:35:11 PM PDT 24
Finished Aug 17 05:35:12 PM PDT 24
Peak memory 195740 kb
Host smart-ecdff55a-94dc-4d2d-8d6b-ab35e39de646
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129629777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.129629777
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.1319932133
Short name T161
Test name
Test status
Simulation time 48623910 ps
CPU time 1.33 seconds
Started Aug 17 05:35:17 PM PDT 24
Finished Aug 17 05:35:18 PM PDT 24
Peak memory 196428 kb
Host smart-730114b5-fd5a-492e-9f2a-3c23071981a4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319932133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.1319932133
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.234143408
Short name T610
Test name
Test status
Simulation time 360467435 ps
CPU time 2.86 seconds
Started Aug 17 05:35:12 PM PDT 24
Finished Aug 17 05:35:15 PM PDT 24
Peak memory 198156 kb
Host smart-076b72c1-8d7f-46cd-a04f-df3b5620415a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234143408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger.
234143408
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.1738490894
Short name T384
Test name
Test status
Simulation time 269777908 ps
CPU time 1.24 seconds
Started Aug 17 05:35:16 PM PDT 24
Finished Aug 17 05:35:17 PM PDT 24
Peak memory 197116 kb
Host smart-8649d4f3-ab66-433c-a81e-e83946923a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738490894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.1738490894
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.4272775563
Short name T294
Test name
Test status
Simulation time 61324608 ps
CPU time 0.75 seconds
Started Aug 17 05:35:16 PM PDT 24
Finished Aug 17 05:35:17 PM PDT 24
Peak memory 197512 kb
Host smart-477aa29f-ee7b-411a-b1a4-1445506ccc01
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272775563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.4272775563
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.2370970946
Short name T4
Test name
Test status
Simulation time 81627177 ps
CPU time 1.46 seconds
Started Aug 17 05:35:13 PM PDT 24
Finished Aug 17 05:35:15 PM PDT 24
Peak memory 198152 kb
Host smart-12b9d947-9ed3-43cf-beaa-2b531e8a545b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370970946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.2370970946
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.3458314411
Short name T600
Test name
Test status
Simulation time 20514838 ps
CPU time 0.73 seconds
Started Aug 17 05:35:16 PM PDT 24
Finished Aug 17 05:35:17 PM PDT 24
Peak memory 195244 kb
Host smart-b18f8bfa-ad7a-4327-a0df-a91bd7db32d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458314411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.3458314411
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.3629863768
Short name T362
Test name
Test status
Simulation time 212745488 ps
CPU time 1.17 seconds
Started Aug 17 05:35:13 PM PDT 24
Finished Aug 17 05:35:14 PM PDT 24
Peak memory 195796 kb
Host smart-05376106-112d-462f-a038-05906828d8fd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629863768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.3629863768
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.2255633751
Short name T353
Test name
Test status
Simulation time 6922757416 ps
CPU time 174.17 seconds
Started Aug 17 05:35:14 PM PDT 24
Finished Aug 17 05:38:08 PM PDT 24
Peak memory 198280 kb
Host smart-8eab0385-bd91-42b5-b01b-83216a44f624
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255633751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.2255633751
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_alert_test.880207375
Short name T196
Test name
Test status
Simulation time 68466883 ps
CPU time 0.56 seconds
Started Aug 17 05:35:24 PM PDT 24
Finished Aug 17 05:35:24 PM PDT 24
Peak memory 194040 kb
Host smart-f5bbd7b4-d670-48ae-803e-d190f81c53bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880207375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.880207375
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.56533473
Short name T303
Test name
Test status
Simulation time 41383304 ps
CPU time 0.92 seconds
Started Aug 17 05:35:12 PM PDT 24
Finished Aug 17 05:35:13 PM PDT 24
Peak memory 197392 kb
Host smart-44599e70-a5a2-44cf-a363-aae562906e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56533473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.56533473
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.1579211566
Short name T669
Test name
Test status
Simulation time 419370009 ps
CPU time 17.15 seconds
Started Aug 17 05:35:21 PM PDT 24
Finished Aug 17 05:35:38 PM PDT 24
Peak memory 196988 kb
Host smart-a52bd1a9-b721-4061-8678-2f4a1aca958f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579211566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.1579211566
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.728127679
Short name T136
Test name
Test status
Simulation time 542558575 ps
CPU time 0.82 seconds
Started Aug 17 05:35:23 PM PDT 24
Finished Aug 17 05:35:24 PM PDT 24
Peak memory 195968 kb
Host smart-4dfacb6c-bb62-43c3-a3f7-1b5c66e49318
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728127679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.728127679
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.2196493046
Short name T334
Test name
Test status
Simulation time 87046289 ps
CPU time 1.25 seconds
Started Aug 17 05:35:25 PM PDT 24
Finished Aug 17 05:35:26 PM PDT 24
Peak memory 195932 kb
Host smart-25131e96-2ac6-4887-b6ee-bcb96b79d7f5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196493046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.2196493046
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.2110736317
Short name T639
Test name
Test status
Simulation time 114607689 ps
CPU time 2.45 seconds
Started Aug 17 05:35:23 PM PDT 24
Finished Aug 17 05:35:26 PM PDT 24
Peak memory 198172 kb
Host smart-534898d3-c9e2-4abf-a106-8194e7c52799
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110736317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.2110736317
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.683187771
Short name T496
Test name
Test status
Simulation time 973180339 ps
CPU time 2.49 seconds
Started Aug 17 05:35:27 PM PDT 24
Finished Aug 17 05:35:30 PM PDT 24
Peak memory 197224 kb
Host smart-3314afdf-b0af-4c3d-996b-e059e104c076
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683187771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger.
683187771
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.2158525628
Short name T387
Test name
Test status
Simulation time 15563827 ps
CPU time 0.64 seconds
Started Aug 17 05:35:14 PM PDT 24
Finished Aug 17 05:35:14 PM PDT 24
Peak memory 194336 kb
Host smart-c7a6f2cd-6d32-4391-8a2d-3dc416f54e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158525628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.2158525628
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.673715738
Short name T23
Test name
Test status
Simulation time 45477255 ps
CPU time 1.15 seconds
Started Aug 17 05:35:17 PM PDT 24
Finished Aug 17 05:35:18 PM PDT 24
Peak memory 196076 kb
Host smart-6cd621e6-efa0-46d2-9ee6-cdbf0920c4d1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673715738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullup
_pulldown.673715738
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.2280883346
Short name T653
Test name
Test status
Simulation time 100656934 ps
CPU time 1.47 seconds
Started Aug 17 05:35:21 PM PDT 24
Finished Aug 17 05:35:22 PM PDT 24
Peak memory 198144 kb
Host smart-9cb6ce8e-7af8-451a-bfe9-c574edb0ebb2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280883346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.2280883346
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.366672442
Short name T489
Test name
Test status
Simulation time 191979575 ps
CPU time 1.27 seconds
Started Aug 17 05:35:15 PM PDT 24
Finished Aug 17 05:35:16 PM PDT 24
Peak memory 198084 kb
Host smart-f948e2d0-b023-4a1f-b512-1f8904a487b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366672442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.366672442
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.2499718006
Short name T19
Test name
Test status
Simulation time 505066212 ps
CPU time 1.3 seconds
Started Aug 17 05:35:11 PM PDT 24
Finished Aug 17 05:35:13 PM PDT 24
Peak memory 198148 kb
Host smart-a982fd9b-bf0e-4c6b-a27b-f622dea1169c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499718006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.2499718006
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.1011904282
Short name T137
Test name
Test status
Simulation time 9665228072 ps
CPU time 68.32 seconds
Started Aug 17 05:35:23 PM PDT 24
Finished Aug 17 05:36:31 PM PDT 24
Peak memory 198340 kb
Host smart-133dde8d-7eb8-439c-8e02-3570b51c766b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011904282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.1011904282
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_alert_test.3976623326
Short name T682
Test name
Test status
Simulation time 110223148 ps
CPU time 0.55 seconds
Started Aug 17 05:35:21 PM PDT 24
Finished Aug 17 05:35:21 PM PDT 24
Peak memory 194240 kb
Host smart-b109f3b8-2bbf-44ee-a06f-f40ea56fb014
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976623326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.3976623326
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.2205627798
Short name T129
Test name
Test status
Simulation time 43246315 ps
CPU time 0.96 seconds
Started Aug 17 05:35:21 PM PDT 24
Finished Aug 17 05:35:22 PM PDT 24
Peak memory 196144 kb
Host smart-f6109ed8-e4c0-46f4-b52b-b5b847941f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205627798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.2205627798
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.3877501093
Short name T252
Test name
Test status
Simulation time 1430626325 ps
CPU time 22.63 seconds
Started Aug 17 05:35:22 PM PDT 24
Finished Aug 17 05:35:45 PM PDT 24
Peak memory 198148 kb
Host smart-c2ab3a3b-81d8-425f-b2fb-f03b7e8ce18e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877501093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.3877501093
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.1355198039
Short name T545
Test name
Test status
Simulation time 282353948 ps
CPU time 0.87 seconds
Started Aug 17 05:35:25 PM PDT 24
Finished Aug 17 05:35:26 PM PDT 24
Peak memory 197020 kb
Host smart-ae43acdc-3056-416b-9ed5-c2d46ebbc593
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355198039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.1355198039
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.364587440
Short name T281
Test name
Test status
Simulation time 404187439 ps
CPU time 1.31 seconds
Started Aug 17 05:35:22 PM PDT 24
Finished Aug 17 05:35:23 PM PDT 24
Peak memory 197116 kb
Host smart-9a0b4614-379b-4e30-a3d2-ce6428579d49
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364587440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.364587440
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.2917636953
Short name T311
Test name
Test status
Simulation time 97139441 ps
CPU time 3.42 seconds
Started Aug 17 05:35:22 PM PDT 24
Finished Aug 17 05:35:25 PM PDT 24
Peak memory 196420 kb
Host smart-7bc5a712-9b56-4a24-92fa-0e7d1c091652
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917636953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.2917636953
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.3844931261
Short name T204
Test name
Test status
Simulation time 375322706 ps
CPU time 1.86 seconds
Started Aug 17 05:35:20 PM PDT 24
Finished Aug 17 05:35:22 PM PDT 24
Peak memory 196244 kb
Host smart-3cd6cb8f-7c9b-4cf3-be9f-92a8f156bfc3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844931261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.3844931261
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.2571423420
Short name T497
Test name
Test status
Simulation time 24246352 ps
CPU time 0.98 seconds
Started Aug 17 05:35:22 PM PDT 24
Finished Aug 17 05:35:23 PM PDT 24
Peak memory 196052 kb
Host smart-03046918-4632-4743-8910-f942ddab97d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571423420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.2571423420
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.769956293
Short name T641
Test name
Test status
Simulation time 709725970 ps
CPU time 0.96 seconds
Started Aug 17 05:35:25 PM PDT 24
Finished Aug 17 05:35:26 PM PDT 24
Peak memory 196020 kb
Host smart-7ed1e679-6e5e-4122-bdb7-c19bc55e8bfd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769956293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullup
_pulldown.769956293
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.2415598055
Short name T580
Test name
Test status
Simulation time 1116749340 ps
CPU time 5.31 seconds
Started Aug 17 05:35:25 PM PDT 24
Finished Aug 17 05:35:30 PM PDT 24
Peak memory 198156 kb
Host smart-897b3dc7-efda-4403-9712-f7cb919f03d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415598055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.2415598055
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.2859833955
Short name T575
Test name
Test status
Simulation time 44960413 ps
CPU time 1.21 seconds
Started Aug 17 05:35:23 PM PDT 24
Finished Aug 17 05:35:24 PM PDT 24
Peak memory 196572 kb
Host smart-b70e6e6d-5633-42fb-9459-1d30567268e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859833955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.2859833955
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.1048686758
Short name T182
Test name
Test status
Simulation time 35593120 ps
CPU time 1.09 seconds
Started Aug 17 05:35:24 PM PDT 24
Finished Aug 17 05:35:25 PM PDT 24
Peak memory 195712 kb
Host smart-3541636b-5fb6-44c6-bed2-4f205394872a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048686758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.1048686758
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.3692271346
Short name T145
Test name
Test status
Simulation time 23171923904 ps
CPU time 156.98 seconds
Started Aug 17 05:35:22 PM PDT 24
Finished Aug 17 05:37:59 PM PDT 24
Peak memory 198228 kb
Host smart-6d1a69be-5328-4fad-bb8e-c5814289eb51
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692271346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.3692271346
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_stress_all_with_rand_reset.129022558
Short name T29
Test name
Test status
Simulation time 11525031013 ps
CPU time 193.39 seconds
Started Aug 17 05:35:24 PM PDT 24
Finished Aug 17 05:38:37 PM PDT 24
Peak memory 198496 kb
Host smart-555fc6af-9cd4-4492-b8aa-428291eb95bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=129022558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_stress_all_with_rand_reset.129022558
Directory /workspace/42.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.gpio_alert_test.2978210616
Short name T37
Test name
Test status
Simulation time 31358655 ps
CPU time 0.6 seconds
Started Aug 17 05:35:32 PM PDT 24
Finished Aug 17 05:35:32 PM PDT 24
Peak memory 194216 kb
Host smart-25e71b3f-8727-462f-9cc6-d882fbaa2106
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978210616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.2978210616
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.2647020201
Short name T458
Test name
Test status
Simulation time 94993989 ps
CPU time 0.67 seconds
Started Aug 17 05:35:23 PM PDT 24
Finished Aug 17 05:35:24 PM PDT 24
Peak memory 194980 kb
Host smart-7adae084-688c-4768-8b72-0fdbe15b0cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647020201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.2647020201
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.1826441590
Short name T674
Test name
Test status
Simulation time 1842529793 ps
CPU time 16.47 seconds
Started Aug 17 05:35:22 PM PDT 24
Finished Aug 17 05:35:38 PM PDT 24
Peak memory 198164 kb
Host smart-fdc4f74c-d3df-44e0-9cf7-e199e202d269
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826441590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.1826441590
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.2933114886
Short name T407
Test name
Test status
Simulation time 114443379 ps
CPU time 0.91 seconds
Started Aug 17 05:35:24 PM PDT 24
Finished Aug 17 05:35:25 PM PDT 24
Peak memory 197776 kb
Host smart-4d694beb-a7ba-42c7-9d0f-7f3595f9f372
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933114886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.2933114886
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.274040937
Short name T423
Test name
Test status
Simulation time 127485314 ps
CPU time 1.11 seconds
Started Aug 17 05:35:23 PM PDT 24
Finished Aug 17 05:35:24 PM PDT 24
Peak memory 196828 kb
Host smart-b408766e-d695-477c-9d41-75245e0b686f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274040937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.274040937
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.623781238
Short name T456
Test name
Test status
Simulation time 323353525 ps
CPU time 3.19 seconds
Started Aug 17 05:35:21 PM PDT 24
Finished Aug 17 05:35:25 PM PDT 24
Peak memory 198200 kb
Host smart-2533f4d6-98f5-4c23-b6fd-6816b5bdfc3f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623781238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 43.gpio_intr_with_filter_rand_intr_event.623781238
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.3012721491
Short name T166
Test name
Test status
Simulation time 665309956 ps
CPU time 1.98 seconds
Started Aug 17 05:35:24 PM PDT 24
Finished Aug 17 05:35:26 PM PDT 24
Peak memory 198168 kb
Host smart-3ea99aef-124e-4735-9d89-6161c8f2540c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012721491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.3012721491
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.1206007833
Short name T283
Test name
Test status
Simulation time 69131572 ps
CPU time 0.86 seconds
Started Aug 17 05:35:21 PM PDT 24
Finished Aug 17 05:35:22 PM PDT 24
Peak memory 195984 kb
Host smart-1ecd261b-e55f-405b-8d90-f784be942e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206007833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.1206007833
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.2588148530
Short name T498
Test name
Test status
Simulation time 101425096 ps
CPU time 0.99 seconds
Started Aug 17 05:35:25 PM PDT 24
Finished Aug 17 05:35:26 PM PDT 24
Peak memory 196672 kb
Host smart-fcf87afb-bb84-4abd-8ee6-7fa85f493b3d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588148530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.2588148530
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.2068931363
Short name T3
Test name
Test status
Simulation time 129971372 ps
CPU time 1.15 seconds
Started Aug 17 05:35:22 PM PDT 24
Finished Aug 17 05:35:23 PM PDT 24
Peak memory 196592 kb
Host smart-737550db-8926-423a-b6c8-1ebf38b30185
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068931363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.2068931363
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.1408918114
Short name T537
Test name
Test status
Simulation time 51294345 ps
CPU time 0.97 seconds
Started Aug 17 05:35:22 PM PDT 24
Finished Aug 17 05:35:23 PM PDT 24
Peak memory 196580 kb
Host smart-472c2799-cb20-48d1-8683-b9eb72ec6f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408918114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.1408918114
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.3575604966
Short name T24
Test name
Test status
Simulation time 77566912 ps
CPU time 0.94 seconds
Started Aug 17 05:35:22 PM PDT 24
Finished Aug 17 05:35:23 PM PDT 24
Peak memory 197148 kb
Host smart-f975d8b7-4afd-49ba-9c99-0eb60bb5df31
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575604966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.3575604966
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.2950592007
Short name T232
Test name
Test status
Simulation time 143094331074 ps
CPU time 136.89 seconds
Started Aug 17 05:35:28 PM PDT 24
Finished Aug 17 05:37:45 PM PDT 24
Peak memory 198288 kb
Host smart-7bf0661d-fcf2-4cff-bdb4-6b8423a471e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950592007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.2950592007
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_alert_test.2854441048
Short name T539
Test name
Test status
Simulation time 17480411 ps
CPU time 0.59 seconds
Started Aug 17 05:35:28 PM PDT 24
Finished Aug 17 05:35:29 PM PDT 24
Peak memory 194880 kb
Host smart-d8b1d64a-dbe8-4606-89c2-77f06c865c1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854441048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.2854441048
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.3766255976
Short name T179
Test name
Test status
Simulation time 51028266 ps
CPU time 0.97 seconds
Started Aug 17 05:35:32 PM PDT 24
Finished Aug 17 05:35:33 PM PDT 24
Peak memory 195840 kb
Host smart-6e029dab-7332-4d4e-a572-64491180902d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766255976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.3766255976
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.3658126340
Short name T48
Test name
Test status
Simulation time 858080327 ps
CPU time 7.53 seconds
Started Aug 17 05:35:31 PM PDT 24
Finished Aug 17 05:35:39 PM PDT 24
Peak memory 198128 kb
Host smart-07664669-bcd2-4513-8e3c-d3902160a415
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658126340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.3658126340
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.1297716173
Short name T468
Test name
Test status
Simulation time 44307783 ps
CPU time 0.79 seconds
Started Aug 17 05:35:28 PM PDT 24
Finished Aug 17 05:35:29 PM PDT 24
Peak memory 196724 kb
Host smart-11a30848-99bc-46f6-a50b-c72ff45b2924
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297716173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.1297716173
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.1282711711
Short name T519
Test name
Test status
Simulation time 137286440 ps
CPU time 0.86 seconds
Started Aug 17 05:35:33 PM PDT 24
Finished Aug 17 05:35:34 PM PDT 24
Peak memory 196540 kb
Host smart-ab26b8d3-1d55-4603-ab17-840202f1175f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282711711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.1282711711
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.2203570892
Short name T578
Test name
Test status
Simulation time 253868045 ps
CPU time 2.63 seconds
Started Aug 17 05:35:35 PM PDT 24
Finished Aug 17 05:35:37 PM PDT 24
Peak memory 197924 kb
Host smart-ebbbaff4-e4eb-4801-a187-f55e8651e48a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203570892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.2203570892
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.277916460
Short name T571
Test name
Test status
Simulation time 149919488 ps
CPU time 3.11 seconds
Started Aug 17 05:35:29 PM PDT 24
Finished Aug 17 05:35:33 PM PDT 24
Peak memory 195900 kb
Host smart-8c5157d3-e9a9-417c-b4e2-26c8ce2e9d69
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277916460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger.
277916460
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.3342073559
Short name T272
Test name
Test status
Simulation time 54205314 ps
CPU time 1.13 seconds
Started Aug 17 05:35:29 PM PDT 24
Finished Aug 17 05:35:30 PM PDT 24
Peak memory 196984 kb
Host smart-edd3aea4-dae4-4095-87fe-642123bd30c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342073559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.3342073559
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.518920892
Short name T237
Test name
Test status
Simulation time 39909380 ps
CPU time 0.92 seconds
Started Aug 17 05:35:33 PM PDT 24
Finished Aug 17 05:35:34 PM PDT 24
Peak memory 196116 kb
Host smart-c8fe3981-27f8-431a-a82c-40a732962924
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518920892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullup
_pulldown.518920892
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.3421301590
Short name T66
Test name
Test status
Simulation time 250766094 ps
CPU time 5.65 seconds
Started Aug 17 05:35:30 PM PDT 24
Finished Aug 17 05:35:36 PM PDT 24
Peak memory 198040 kb
Host smart-9b7c1366-561f-4e46-95a1-82e039f6d632
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421301590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.3421301590
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.606840027
Short name T705
Test name
Test status
Simulation time 324786224 ps
CPU time 1.23 seconds
Started Aug 17 05:35:31 PM PDT 24
Finished Aug 17 05:35:33 PM PDT 24
Peak memory 195620 kb
Host smart-992c196d-910f-4c25-8e8d-c16b03a54558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606840027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.606840027
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.1465077179
Short name T213
Test name
Test status
Simulation time 97698922 ps
CPU time 0.91 seconds
Started Aug 17 05:35:29 PM PDT 24
Finished Aug 17 05:35:30 PM PDT 24
Peak memory 195980 kb
Host smart-426a2b2c-857a-4983-96eb-458c903aee69
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465077179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.1465077179
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.1378728940
Short name T184
Test name
Test status
Simulation time 25361699663 ps
CPU time 188.46 seconds
Started Aug 17 05:35:30 PM PDT 24
Finished Aug 17 05:38:39 PM PDT 24
Peak memory 198360 kb
Host smart-ae178bb2-ff8e-4a42-8519-d6ba7a0d6ea2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378728940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.1378728940
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_alert_test.4223692045
Short name T262
Test name
Test status
Simulation time 87791433 ps
CPU time 0.55 seconds
Started Aug 17 05:35:28 PM PDT 24
Finished Aug 17 05:35:29 PM PDT 24
Peak memory 194776 kb
Host smart-e7bcb12f-8185-47a2-a4f3-936b1de2c8da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223692045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.4223692045
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.2711318914
Short name T120
Test name
Test status
Simulation time 64016177 ps
CPU time 0.8 seconds
Started Aug 17 05:35:28 PM PDT 24
Finished Aug 17 05:35:29 PM PDT 24
Peak memory 196208 kb
Host smart-df5a5129-2d4d-4473-a100-11f94ba10ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711318914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.2711318914
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.62716497
Short name T472
Test name
Test status
Simulation time 481205771 ps
CPU time 23.55 seconds
Started Aug 17 05:35:32 PM PDT 24
Finished Aug 17 05:35:56 PM PDT 24
Peak memory 195708 kb
Host smart-deda5380-26cb-42be-abf6-960aa391a436
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62716497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stress
.62716497
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.1171556667
Short name T171
Test name
Test status
Simulation time 173382528 ps
CPU time 0.81 seconds
Started Aug 17 05:35:30 PM PDT 24
Finished Aug 17 05:35:30 PM PDT 24
Peak memory 195956 kb
Host smart-df9c0e26-198c-4248-8a24-c89cab29ea0e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171556667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.1171556667
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.265983938
Short name T648
Test name
Test status
Simulation time 22420128 ps
CPU time 0.61 seconds
Started Aug 17 05:35:28 PM PDT 24
Finished Aug 17 05:35:29 PM PDT 24
Peak memory 194324 kb
Host smart-8a48e1ce-a050-41f3-8adc-10796b05b409
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265983938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.265983938
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.3065333709
Short name T486
Test name
Test status
Simulation time 73688850 ps
CPU time 2.89 seconds
Started Aug 17 05:35:32 PM PDT 24
Finished Aug 17 05:35:35 PM PDT 24
Peak memory 198168 kb
Host smart-27b042c8-123c-4b13-ba6d-9ca458650c10
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065333709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.3065333709
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.4108078013
Short name T367
Test name
Test status
Simulation time 65338584 ps
CPU time 0.95 seconds
Started Aug 17 05:35:26 PM PDT 24
Finished Aug 17 05:35:27 PM PDT 24
Peak memory 195756 kb
Host smart-ae907561-fa78-4f2d-ac66-e0e49daa1afd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108078013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.4108078013
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.1525503249
Short name T529
Test name
Test status
Simulation time 106923722 ps
CPU time 0.77 seconds
Started Aug 17 05:35:30 PM PDT 24
Finished Aug 17 05:35:30 PM PDT 24
Peak memory 197356 kb
Host smart-51e8fee9-6b74-40b2-8e84-50f53a2ae87c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525503249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.1525503249
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.342923764
Short name T101
Test name
Test status
Simulation time 104494097 ps
CPU time 1.07 seconds
Started Aug 17 05:35:29 PM PDT 24
Finished Aug 17 05:35:30 PM PDT 24
Peak memory 196220 kb
Host smart-35effceb-22c0-412d-a492-f8ea0f41c568
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342923764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullup
_pulldown.342923764
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.585038434
Short name T424
Test name
Test status
Simulation time 234745960 ps
CPU time 1.4 seconds
Started Aug 17 05:35:31 PM PDT 24
Finished Aug 17 05:35:33 PM PDT 24
Peak memory 198184 kb
Host smart-2932ca01-c77c-41e8-a5a5-4b530ced61b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585038434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ran
dom_long_reg_writes_reg_reads.585038434
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.3437764708
Short name T151
Test name
Test status
Simulation time 233442050 ps
CPU time 1.22 seconds
Started Aug 17 05:35:32 PM PDT 24
Finished Aug 17 05:35:34 PM PDT 24
Peak memory 196732 kb
Host smart-38c2c7e6-a381-4422-988e-cd6f94ba15ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437764708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.3437764708
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.580682079
Short name T119
Test name
Test status
Simulation time 59973776 ps
CPU time 0.98 seconds
Started Aug 17 05:35:31 PM PDT 24
Finished Aug 17 05:35:33 PM PDT 24
Peak memory 196308 kb
Host smart-92d7e25d-2d41-41c0-8d1f-48d331f67763
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580682079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.580682079
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.2137357
Short name T605
Test name
Test status
Simulation time 23164253731 ps
CPU time 83.51 seconds
Started Aug 17 05:35:31 PM PDT 24
Finished Aug 17 05:36:54 PM PDT 24
Peak memory 198304 kb
Host smart-059b0c7d-6deb-4304-a8f4-1c4206935ef5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TES
T_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpi
o_stress_all.2137357
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_alert_test.3306311617
Short name T174
Test name
Test status
Simulation time 18726639 ps
CPU time 0.56 seconds
Started Aug 17 05:35:37 PM PDT 24
Finished Aug 17 05:35:38 PM PDT 24
Peak memory 193976 kb
Host smart-40218fa3-1707-4a68-9b83-ffa564fccdd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306311617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.3306311617
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.2035518853
Short name T427
Test name
Test status
Simulation time 32928418 ps
CPU time 0.59 seconds
Started Aug 17 05:35:30 PM PDT 24
Finished Aug 17 05:35:30 PM PDT 24
Peak memory 194708 kb
Host smart-8647f029-8291-493e-aee1-2ea78320d7bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035518853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.2035518853
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.3222963483
Short name T242
Test name
Test status
Simulation time 887300420 ps
CPU time 14.67 seconds
Started Aug 17 05:35:31 PM PDT 24
Finished Aug 17 05:35:46 PM PDT 24
Peak memory 196904 kb
Host smart-79416bef-b09a-4ccc-96f1-99087da296a8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222963483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.3222963483
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.3517069923
Short name T535
Test name
Test status
Simulation time 68240661 ps
CPU time 1 seconds
Started Aug 17 05:35:32 PM PDT 24
Finished Aug 17 05:35:34 PM PDT 24
Peak memory 196784 kb
Host smart-13cb4bf0-22cd-438c-a2dc-a30af76228c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517069923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.3517069923
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.2824568975
Short name T176
Test name
Test status
Simulation time 209692609 ps
CPU time 1 seconds
Started Aug 17 05:35:31 PM PDT 24
Finished Aug 17 05:35:32 PM PDT 24
Peak memory 196868 kb
Host smart-bcd164e3-612a-4954-b880-b539fb9029ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824568975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.2824568975
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.1642282570
Short name T523
Test name
Test status
Simulation time 137326173 ps
CPU time 2.66 seconds
Started Aug 17 05:35:30 PM PDT 24
Finished Aug 17 05:35:32 PM PDT 24
Peak memory 198144 kb
Host smart-a28c0a4c-9f0f-48ad-96da-2ccad4baa652
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642282570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.1642282570
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.2946321440
Short name T327
Test name
Test status
Simulation time 101915010 ps
CPU time 2.63 seconds
Started Aug 17 05:35:30 PM PDT 24
Finished Aug 17 05:35:33 PM PDT 24
Peak memory 197392 kb
Host smart-2f6b6359-6c59-4de7-a9f9-c19801a8cbc6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946321440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.2946321440
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.3428095847
Short name T246
Test name
Test status
Simulation time 24570622 ps
CPU time 0.68 seconds
Started Aug 17 05:35:29 PM PDT 24
Finished Aug 17 05:35:29 PM PDT 24
Peak memory 195356 kb
Host smart-59657133-35c3-41b7-8f9b-449cb4945117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428095847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.3428095847
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.1041299002
Short name T280
Test name
Test status
Simulation time 38081710 ps
CPU time 1.14 seconds
Started Aug 17 05:35:32 PM PDT 24
Finished Aug 17 05:35:34 PM PDT 24
Peak memory 196672 kb
Host smart-e76ad568-0322-4653-b231-295583d8a83c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041299002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.1041299002
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.4180412497
Short name T494
Test name
Test status
Simulation time 1259984642 ps
CPU time 2.5 seconds
Started Aug 17 05:35:28 PM PDT 24
Finished Aug 17 05:35:30 PM PDT 24
Peak memory 198136 kb
Host smart-056b6fc8-4015-458c-bd0d-fdad095af6ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180412497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.4180412497
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.107144977
Short name T155
Test name
Test status
Simulation time 306491027 ps
CPU time 1.36 seconds
Started Aug 17 05:35:28 PM PDT 24
Finished Aug 17 05:35:29 PM PDT 24
Peak memory 198156 kb
Host smart-979e7523-0ce7-4492-923f-8905b12f4b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107144977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.107144977
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.3253294582
Short name T704
Test name
Test status
Simulation time 74986174 ps
CPU time 1.27 seconds
Started Aug 17 05:35:31 PM PDT 24
Finished Aug 17 05:35:32 PM PDT 24
Peak memory 195712 kb
Host smart-d6f0aa09-87d8-4ced-b159-0a5e865f81f6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253294582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.3253294582
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.1381985374
Short name T6
Test name
Test status
Simulation time 8229243060 ps
CPU time 41.7 seconds
Started Aug 17 05:35:33 PM PDT 24
Finished Aug 17 05:36:15 PM PDT 24
Peak memory 192184 kb
Host smart-7a347a37-03b5-4ca0-9536-c3c51b5f4e8f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381985374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.1381985374
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_alert_test.1424031913
Short name T309
Test name
Test status
Simulation time 24833985 ps
CPU time 0.57 seconds
Started Aug 17 05:35:38 PM PDT 24
Finished Aug 17 05:35:39 PM PDT 24
Peak memory 194676 kb
Host smart-1cf37542-14e0-4799-a05f-89204942c8c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424031913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.1424031913
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.3360186367
Short name T517
Test name
Test status
Simulation time 39131506 ps
CPU time 0.87 seconds
Started Aug 17 05:35:37 PM PDT 24
Finished Aug 17 05:35:38 PM PDT 24
Peak memory 196536 kb
Host smart-4c1ec9f8-8302-40ff-a411-aff223e1d6ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360186367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.3360186367
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.93478118
Short name T279
Test name
Test status
Simulation time 341397292 ps
CPU time 18.27 seconds
Started Aug 17 05:35:41 PM PDT 24
Finished Aug 17 05:35:59 PM PDT 24
Peak memory 195616 kb
Host smart-2c85aa55-4444-4bd4-bbc4-b2a9d98114c3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93478118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stress
.93478118
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.734011656
Short name T609
Test name
Test status
Simulation time 139422281 ps
CPU time 0.68 seconds
Started Aug 17 05:35:36 PM PDT 24
Finished Aug 17 05:35:37 PM PDT 24
Peak memory 194812 kb
Host smart-fab10cb2-9065-4dee-9e10-961b37bda4cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734011656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.734011656
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.994137098
Short name T556
Test name
Test status
Simulation time 47811148 ps
CPU time 0.93 seconds
Started Aug 17 05:35:40 PM PDT 24
Finished Aug 17 05:35:41 PM PDT 24
Peak memory 196932 kb
Host smart-b9157924-dca5-4169-9abe-aafff6c7f829
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994137098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.994137098
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.1937040085
Short name T481
Test name
Test status
Simulation time 94784531 ps
CPU time 1.94 seconds
Started Aug 17 05:35:40 PM PDT 24
Finished Aug 17 05:35:42 PM PDT 24
Peak memory 198184 kb
Host smart-e7823e43-d1fa-4612-a160-2394ecc8366c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937040085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.1937040085
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.2854686268
Short name T180
Test name
Test status
Simulation time 80034427 ps
CPU time 1.76 seconds
Started Aug 17 05:35:37 PM PDT 24
Finished Aug 17 05:35:39 PM PDT 24
Peak memory 196344 kb
Host smart-2de458c9-2f40-4775-89e4-6a687fb8ac7a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854686268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.2854686268
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.2693801789
Short name T479
Test name
Test status
Simulation time 50643172 ps
CPU time 1.06 seconds
Started Aug 17 05:35:38 PM PDT 24
Finished Aug 17 05:35:39 PM PDT 24
Peak memory 196148 kb
Host smart-f6ad87ef-f98d-4c64-a4ff-274850ac4e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693801789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.2693801789
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.3966888050
Short name T275
Test name
Test status
Simulation time 76444002 ps
CPU time 0.99 seconds
Started Aug 17 05:35:39 PM PDT 24
Finished Aug 17 05:35:40 PM PDT 24
Peak memory 196960 kb
Host smart-d01b645f-c671-4c6f-bb2a-397d2cf63222
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966888050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.3966888050
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.3559983202
Short name T343
Test name
Test status
Simulation time 215565547 ps
CPU time 4.88 seconds
Started Aug 17 05:35:38 PM PDT 24
Finished Aug 17 05:35:43 PM PDT 24
Peak memory 198120 kb
Host smart-b038aacc-39d8-4044-a98e-b945ea8a0e4f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559983202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.3559983202
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.2714017865
Short name T239
Test name
Test status
Simulation time 127624305 ps
CPU time 1.18 seconds
Started Aug 17 05:35:36 PM PDT 24
Finished Aug 17 05:35:38 PM PDT 24
Peak memory 196792 kb
Host smart-89b91619-e4d9-4a6a-b0b6-8270b6c232ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714017865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.2714017865
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.3882548324
Short name T591
Test name
Test status
Simulation time 215951097 ps
CPU time 1.38 seconds
Started Aug 17 05:35:37 PM PDT 24
Finished Aug 17 05:35:38 PM PDT 24
Peak memory 196944 kb
Host smart-4bea151e-f898-440e-b5f8-a3d2b68a3fa2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882548324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.3882548324
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.269673761
Short name T315
Test name
Test status
Simulation time 10498070442 ps
CPU time 36.56 seconds
Started Aug 17 05:35:40 PM PDT 24
Finished Aug 17 05:36:16 PM PDT 24
Peak memory 198336 kb
Host smart-a05122ad-12bc-4f7a-8d2f-bcf9719f9546
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269673761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.g
pio_stress_all.269673761
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_alert_test.3404738179
Short name T292
Test name
Test status
Simulation time 21627518 ps
CPU time 0.56 seconds
Started Aug 17 05:35:39 PM PDT 24
Finished Aug 17 05:35:39 PM PDT 24
Peak memory 194752 kb
Host smart-26ac6622-f2ea-405c-9352-a5e4843e62a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404738179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.3404738179
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.1540505997
Short name T488
Test name
Test status
Simulation time 43187305 ps
CPU time 0.82 seconds
Started Aug 17 05:35:39 PM PDT 24
Finished Aug 17 05:35:40 PM PDT 24
Peak memory 196296 kb
Host smart-8ebff6f2-3a69-4c82-b076-abfdc36c161c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540505997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.1540505997
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.3609995624
Short name T507
Test name
Test status
Simulation time 290852214 ps
CPU time 9.95 seconds
Started Aug 17 05:35:45 PM PDT 24
Finished Aug 17 05:35:55 PM PDT 24
Peak memory 197360 kb
Host smart-09b17436-4efe-40df-a21c-6719d2a5b54a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609995624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.3609995624
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.736493410
Short name T132
Test name
Test status
Simulation time 110945386 ps
CPU time 0.87 seconds
Started Aug 17 05:35:42 PM PDT 24
Finished Aug 17 05:35:43 PM PDT 24
Peak memory 196160 kb
Host smart-ea8005c8-9704-40dd-884e-8debcfff38c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736493410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.736493410
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.3450298697
Short name T667
Test name
Test status
Simulation time 284196779 ps
CPU time 1.06 seconds
Started Aug 17 05:35:40 PM PDT 24
Finished Aug 17 05:35:41 PM PDT 24
Peak memory 197012 kb
Host smart-1c318d10-ba84-41fe-ad70-05347ff947a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450298697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.3450298697
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.2379304568
Short name T98
Test name
Test status
Simulation time 339741344 ps
CPU time 3.5 seconds
Started Aug 17 05:35:43 PM PDT 24
Finished Aug 17 05:35:47 PM PDT 24
Peak memory 198224 kb
Host smart-0b9d23b5-4b7c-4ea5-bbb2-738afea8079b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379304568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.2379304568
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.1566237359
Short name T627
Test name
Test status
Simulation time 80159093 ps
CPU time 2.3 seconds
Started Aug 17 05:35:37 PM PDT 24
Finished Aug 17 05:35:39 PM PDT 24
Peak memory 197192 kb
Host smart-f3c7a62a-7e89-411c-a91c-130934340e7f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566237359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.1566237359
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.1648548509
Short name T543
Test name
Test status
Simulation time 30569578 ps
CPU time 0.85 seconds
Started Aug 17 05:35:38 PM PDT 24
Finished Aug 17 05:35:39 PM PDT 24
Peak memory 197364 kb
Host smart-09693cf3-b650-41b7-a10d-4138ea41f5b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648548509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.1648548509
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.449105210
Short name T256
Test name
Test status
Simulation time 59212193 ps
CPU time 1.09 seconds
Started Aug 17 05:35:41 PM PDT 24
Finished Aug 17 05:35:42 PM PDT 24
Peak memory 196184 kb
Host smart-52eea8f1-2d57-420e-ae61-ecf6512d448b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449105210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullup
_pulldown.449105210
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.3771690104
Short name T391
Test name
Test status
Simulation time 336774095 ps
CPU time 2.89 seconds
Started Aug 17 05:35:40 PM PDT 24
Finished Aug 17 05:35:43 PM PDT 24
Peak memory 198152 kb
Host smart-a7815d6e-27b8-42f7-bc5a-1d67a74fd06b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771690104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.3771690104
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.3338302134
Short name T156
Test name
Test status
Simulation time 62665486 ps
CPU time 1.13 seconds
Started Aug 17 05:35:39 PM PDT 24
Finished Aug 17 05:35:40 PM PDT 24
Peak memory 195836 kb
Host smart-52447075-dc57-4ec9-a520-c784c1fb3ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338302134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.3338302134
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.579826252
Short name T347
Test name
Test status
Simulation time 401383211 ps
CPU time 1.12 seconds
Started Aug 17 05:35:43 PM PDT 24
Finished Aug 17 05:35:44 PM PDT 24
Peak memory 195832 kb
Host smart-67f2b47d-6775-4575-816b-d85b805f35f5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579826252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.579826252
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.18808409
Short name T116
Test name
Test status
Simulation time 11399235101 ps
CPU time 68.35 seconds
Started Aug 17 05:35:38 PM PDT 24
Finished Aug 17 05:36:47 PM PDT 24
Peak memory 198360 kb
Host smart-5e4e2e2c-de0c-4a07-b9c9-1876015a4eac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18808409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gp
io_stress_all.18808409
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_alert_test.635595991
Short name T38
Test name
Test status
Simulation time 23858425 ps
CPU time 0.55 seconds
Started Aug 17 05:35:39 PM PDT 24
Finished Aug 17 05:35:39 PM PDT 24
Peak memory 194064 kb
Host smart-b16e5f0a-cb88-47c8-98d6-7ff1eaa91143
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635595991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.635595991
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.2329089534
Short name T557
Test name
Test status
Simulation time 42417147 ps
CPU time 0.92 seconds
Started Aug 17 05:35:36 PM PDT 24
Finished Aug 17 05:35:37 PM PDT 24
Peak memory 197140 kb
Host smart-89968cc8-a3fe-4b50-8ddd-fe2178b399c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329089534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.2329089534
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.107161358
Short name T429
Test name
Test status
Simulation time 3249247393 ps
CPU time 27.71 seconds
Started Aug 17 05:35:40 PM PDT 24
Finished Aug 17 05:36:08 PM PDT 24
Peak memory 197276 kb
Host smart-2499cf6b-813d-40c1-8f73-44688d7a4ae1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107161358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stres
s.107161358
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.2498301015
Short name T5
Test name
Test status
Simulation time 131024503 ps
CPU time 0.88 seconds
Started Aug 17 05:35:44 PM PDT 24
Finished Aug 17 05:35:45 PM PDT 24
Peak memory 196108 kb
Host smart-a12edf2e-3ad9-4da4-8bd1-6ffff531a808
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498301015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.2498301015
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.1112574130
Short name T691
Test name
Test status
Simulation time 82991011 ps
CPU time 1.24 seconds
Started Aug 17 05:35:39 PM PDT 24
Finished Aug 17 05:35:40 PM PDT 24
Peak memory 196184 kb
Host smart-7fdd1d94-ace4-4c29-9256-e60efb858446
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112574130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.1112574130
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.2406497398
Short name T505
Test name
Test status
Simulation time 134796836 ps
CPU time 1.6 seconds
Started Aug 17 05:35:42 PM PDT 24
Finished Aug 17 05:35:43 PM PDT 24
Peak memory 198276 kb
Host smart-9a3fc7e1-17d1-4f88-93cb-8bf2ee978115
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406497398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.2406497398
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.3863925112
Short name T542
Test name
Test status
Simulation time 199035973 ps
CPU time 2.18 seconds
Started Aug 17 05:35:43 PM PDT 24
Finished Aug 17 05:35:45 PM PDT 24
Peak memory 197188 kb
Host smart-03ee0189-29dd-4638-9fb9-e7cd4a819aa0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863925112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.3863925112
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.1475280438
Short name T308
Test name
Test status
Simulation time 61115952 ps
CPU time 0.77 seconds
Started Aug 17 05:35:44 PM PDT 24
Finished Aug 17 05:35:45 PM PDT 24
Peak memory 195512 kb
Host smart-0bcf07ff-2cec-4f93-934a-d262294cc0ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475280438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.1475280438
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.1453833900
Short name T128
Test name
Test status
Simulation time 58206258 ps
CPU time 1.33 seconds
Started Aug 17 05:35:40 PM PDT 24
Finished Aug 17 05:35:41 PM PDT 24
Peak memory 197184 kb
Host smart-5e8e2333-dae4-4cf2-a8f6-3f70994d28c8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453833900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.1453833900
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.4015339494
Short name T608
Test name
Test status
Simulation time 623376650 ps
CPU time 2.42 seconds
Started Aug 17 05:35:36 PM PDT 24
Finished Aug 17 05:35:39 PM PDT 24
Peak memory 198140 kb
Host smart-77ae706e-f0d4-4834-bd5b-f5fc0595fcd9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015339494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.4015339494
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.4032631666
Short name T310
Test name
Test status
Simulation time 50962637 ps
CPU time 1.04 seconds
Started Aug 17 05:35:37 PM PDT 24
Finished Aug 17 05:35:38 PM PDT 24
Peak memory 195716 kb
Host smart-a515bb9a-ae7c-4e81-b626-764b781e068e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032631666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.4032631666
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.286575580
Short name T263
Test name
Test status
Simulation time 131252797 ps
CPU time 1.02 seconds
Started Aug 17 05:35:43 PM PDT 24
Finished Aug 17 05:35:44 PM PDT 24
Peak memory 195576 kb
Host smart-bb47ecf8-da8d-46cf-a965-a3e53d64edf7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286575580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.286575580
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.1069391713
Short name T299
Test name
Test status
Simulation time 2713237907 ps
CPU time 69.84 seconds
Started Aug 17 05:35:37 PM PDT 24
Finished Aug 17 05:36:47 PM PDT 24
Peak memory 198328 kb
Host smart-aa954a50-2403-4f04-a793-97e08a316f40
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069391713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.1069391713
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_alert_test.1497173652
Short name T477
Test name
Test status
Simulation time 31420424 ps
CPU time 0.53 seconds
Started Aug 17 05:33:00 PM PDT 24
Finished Aug 17 05:33:00 PM PDT 24
Peak memory 192868 kb
Host smart-afe7d8fd-33d2-4afa-877d-8379c4c05a4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497173652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.1497173652
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.3105444086
Short name T202
Test name
Test status
Simulation time 333296191 ps
CPU time 0.82 seconds
Started Aug 17 05:32:51 PM PDT 24
Finished Aug 17 05:32:52 PM PDT 24
Peak memory 196792 kb
Host smart-c530a2cc-be7d-4d10-9feb-89645d778bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105444086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.3105444086
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.1228581516
Short name T221
Test name
Test status
Simulation time 506004838 ps
CPU time 9.02 seconds
Started Aug 17 05:33:01 PM PDT 24
Finished Aug 17 05:33:10 PM PDT 24
Peak memory 197212 kb
Host smart-496b20ec-dd86-4104-9bfe-056c1d63a879
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228581516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.1228581516
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.4252864188
Short name T175
Test name
Test status
Simulation time 177937579 ps
CPU time 0.97 seconds
Started Aug 17 05:33:01 PM PDT 24
Finished Aug 17 05:33:02 PM PDT 24
Peak memory 196772 kb
Host smart-2c320d05-b51f-401c-b908-f7c7c95837a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252864188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.4252864188
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.871201247
Short name T592
Test name
Test status
Simulation time 71829868 ps
CPU time 1.2 seconds
Started Aug 17 05:32:51 PM PDT 24
Finished Aug 17 05:32:53 PM PDT 24
Peak memory 196176 kb
Host smart-c5bc19fe-fdf5-44d8-9e0d-84b474a705f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871201247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.871201247
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.80413721
Short name T165
Test name
Test status
Simulation time 64632653 ps
CPU time 2.56 seconds
Started Aug 17 05:33:00 PM PDT 24
Finished Aug 17 05:33:03 PM PDT 24
Peak memory 198248 kb
Host smart-ec1e51d6-ff2f-47c0-868d-86a7f9897948
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80413721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 5.gpio_intr_with_filter_rand_intr_event.80413721
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.1442153719
Short name T495
Test name
Test status
Simulation time 276972896 ps
CPU time 2.25 seconds
Started Aug 17 05:33:02 PM PDT 24
Finished Aug 17 05:33:05 PM PDT 24
Peak memory 197300 kb
Host smart-2fab769d-fb1f-42b0-ad69-07c2b93e377d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442153719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
1442153719
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.2009150608
Short name T236
Test name
Test status
Simulation time 195757937 ps
CPU time 1.19 seconds
Started Aug 17 05:32:51 PM PDT 24
Finished Aug 17 05:32:53 PM PDT 24
Peak memory 196792 kb
Host smart-045e9625-33bf-4faf-9124-d758caf1516f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009150608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.2009150608
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.3228029249
Short name T178
Test name
Test status
Simulation time 203057651 ps
CPU time 0.86 seconds
Started Aug 17 05:32:53 PM PDT 24
Finished Aug 17 05:32:54 PM PDT 24
Peak memory 195920 kb
Host smart-9a3855cb-b8b6-40d2-93d7-4208474b02a1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228029249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.3228029249
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.3077013614
Short name T313
Test name
Test status
Simulation time 418176968 ps
CPU time 5.48 seconds
Started Aug 17 05:33:00 PM PDT 24
Finished Aug 17 05:33:06 PM PDT 24
Peak memory 197884 kb
Host smart-71756168-8def-49ff-ad9a-1ac872d51cd2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077013614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.3077013614
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.2465488837
Short name T125
Test name
Test status
Simulation time 37992429 ps
CPU time 0.79 seconds
Started Aug 17 05:32:51 PM PDT 24
Finished Aug 17 05:32:52 PM PDT 24
Peak memory 195432 kb
Host smart-7807a3ed-d3d8-4efa-b46b-1b891cbe01d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465488837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.2465488837
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.2332802012
Short name T380
Test name
Test status
Simulation time 199557385 ps
CPU time 0.8 seconds
Started Aug 17 05:32:50 PM PDT 24
Finished Aug 17 05:32:51 PM PDT 24
Peak memory 195276 kb
Host smart-d7088af3-0055-4ad0-bf60-1f0b7fadb738
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332802012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.2332802012
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.3461383180
Short name T332
Test name
Test status
Simulation time 19055024336 ps
CPU time 195.72 seconds
Started Aug 17 05:33:05 PM PDT 24
Finished Aug 17 05:36:20 PM PDT 24
Peak memory 198336 kb
Host smart-3b9fec50-8224-4395-ac87-8fb36effc32e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461383180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.3461383180
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_alert_test.1307408615
Short name T617
Test name
Test status
Simulation time 13660872 ps
CPU time 0.57 seconds
Started Aug 17 05:33:02 PM PDT 24
Finished Aug 17 05:33:03 PM PDT 24
Peak memory 194040 kb
Host smart-6fd94368-f280-4f29-b385-d49b46998fec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307408615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.1307408615
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.4188653652
Short name T611
Test name
Test status
Simulation time 97660066 ps
CPU time 0.87 seconds
Started Aug 17 05:33:05 PM PDT 24
Finished Aug 17 05:33:06 PM PDT 24
Peak memory 196160 kb
Host smart-82c43e82-cc79-4394-aec0-dd7c475363a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188653652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.4188653652
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.3129504412
Short name T451
Test name
Test status
Simulation time 536850191 ps
CPU time 25.77 seconds
Started Aug 17 05:32:59 PM PDT 24
Finished Aug 17 05:33:25 PM PDT 24
Peak memory 197136 kb
Host smart-c40cef15-09a5-4896-a14b-640906408f53
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129504412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.3129504412
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.4234465198
Short name T376
Test name
Test status
Simulation time 80235883 ps
CPU time 0.97 seconds
Started Aug 17 05:33:02 PM PDT 24
Finished Aug 17 05:33:03 PM PDT 24
Peak memory 197272 kb
Host smart-657cd5fc-ac49-4565-a278-0a1eb77dcbca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234465198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.4234465198
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.1334947338
Short name T621
Test name
Test status
Simulation time 125738083 ps
CPU time 0.91 seconds
Started Aug 17 05:33:01 PM PDT 24
Finished Aug 17 05:33:02 PM PDT 24
Peak memory 195992 kb
Host smart-ad0fc834-4636-4ac4-838a-562a8433defa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334947338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.1334947338
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.3664344607
Short name T483
Test name
Test status
Simulation time 378107796 ps
CPU time 3.59 seconds
Started Aug 17 05:33:01 PM PDT 24
Finished Aug 17 05:33:05 PM PDT 24
Peak memory 198216 kb
Host smart-96322625-4506-4b6c-951b-a09d63722dc3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664344607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.3664344607
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.19315475
Short name T341
Test name
Test status
Simulation time 524950247 ps
CPU time 1.42 seconds
Started Aug 17 05:33:00 PM PDT 24
Finished Aug 17 05:33:01 PM PDT 24
Peak memory 196304 kb
Host smart-6c82bc5d-f453-451a-8830-5879699f825d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19315475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.19315475
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.3199914080
Short name T676
Test name
Test status
Simulation time 140204752 ps
CPU time 0.95 seconds
Started Aug 17 05:33:01 PM PDT 24
Finished Aug 17 05:33:02 PM PDT 24
Peak memory 196048 kb
Host smart-eecc38f4-34ec-4ad8-9ffe-7359d1f10612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199914080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.3199914080
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.1206541818
Short name T248
Test name
Test status
Simulation time 58690728 ps
CPU time 1.24 seconds
Started Aug 17 05:33:02 PM PDT 24
Finished Aug 17 05:33:04 PM PDT 24
Peak memory 195996 kb
Host smart-9b04a5f9-44fc-40ab-9597-c6234b089f46
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206541818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup
_pulldown.1206541818
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.3976075820
Short name T395
Test name
Test status
Simulation time 797852431 ps
CPU time 3.37 seconds
Started Aug 17 05:33:04 PM PDT 24
Finished Aug 17 05:33:08 PM PDT 24
Peak memory 198164 kb
Host smart-f0c0437b-1c96-4aff-8c27-e88b8516f606
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976075820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran
dom_long_reg_writes_reg_reads.3976075820
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.3414710579
Short name T26
Test name
Test status
Simulation time 78164645 ps
CPU time 1.02 seconds
Started Aug 17 05:33:06 PM PDT 24
Finished Aug 17 05:33:07 PM PDT 24
Peak memory 195664 kb
Host smart-c7d430ee-4b81-496c-b586-ffe2e4770ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414710579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.3414710579
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.1077360899
Short name T357
Test name
Test status
Simulation time 477665112 ps
CPU time 1.15 seconds
Started Aug 17 05:33:02 PM PDT 24
Finished Aug 17 05:33:03 PM PDT 24
Peak memory 196008 kb
Host smart-a737a44d-6bc3-4f37-9a7a-03f21ca82cbd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077360899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.1077360899
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.871485115
Short name T139
Test name
Test status
Simulation time 2171133313 ps
CPU time 54.15 seconds
Started Aug 17 05:33:01 PM PDT 24
Finished Aug 17 05:33:56 PM PDT 24
Peak memory 198008 kb
Host smart-f0f22295-a874-4d85-a0f0-127cff852958
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871485115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gp
io_stress_all.871485115
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_stress_all_with_rand_reset.741566298
Short name T590
Test name
Test status
Simulation time 4055756553 ps
CPU time 130.78 seconds
Started Aug 17 05:33:02 PM PDT 24
Finished Aug 17 05:35:13 PM PDT 24
Peak memory 198532 kb
Host smart-046866cf-98a8-417a-8b7f-27aa15d076fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=741566298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_stress_all_with_rand_reset.741566298
Directory /workspace/6.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.gpio_alert_test.2020449463
Short name T538
Test name
Test status
Simulation time 13539913 ps
CPU time 0.54 seconds
Started Aug 17 05:33:07 PM PDT 24
Finished Aug 17 05:33:07 PM PDT 24
Peak memory 194012 kb
Host smart-6282a4b9-8afd-42a5-91e0-c63fbc5ebcff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020449463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.2020449463
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.1386108583
Short name T457
Test name
Test status
Simulation time 92497799 ps
CPU time 0.83 seconds
Started Aug 17 05:33:07 PM PDT 24
Finished Aug 17 05:33:08 PM PDT 24
Peak memory 196552 kb
Host smart-fadd03fb-9346-4aac-a9ec-3b5d1e8cf939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386108583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.1386108583
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.3646503912
Short name T386
Test name
Test status
Simulation time 2220268618 ps
CPU time 5.6 seconds
Started Aug 17 05:33:08 PM PDT 24
Finished Aug 17 05:33:14 PM PDT 24
Peak memory 197192 kb
Host smart-1f0fba44-6895-4d57-b8ba-9899cb143329
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646503912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.3646503912
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.1569592114
Short name T249
Test name
Test status
Simulation time 73020882 ps
CPU time 0.93 seconds
Started Aug 17 05:33:09 PM PDT 24
Finished Aug 17 05:33:10 PM PDT 24
Peak memory 197704 kb
Host smart-ddc4987e-54a4-49e5-b4a6-b3ae52dddfb6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569592114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.1569592114
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.2366511216
Short name T224
Test name
Test status
Simulation time 293729915 ps
CPU time 1.31 seconds
Started Aug 17 05:33:06 PM PDT 24
Finished Aug 17 05:33:08 PM PDT 24
Peak memory 198240 kb
Host smart-eac8c6c1-cc45-4720-bf20-0fcf9b5af2f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366511216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.2366511216
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.465685455
Short name T554
Test name
Test status
Simulation time 37528032 ps
CPU time 1.56 seconds
Started Aug 17 05:33:07 PM PDT 24
Finished Aug 17 05:33:08 PM PDT 24
Peak memory 196904 kb
Host smart-d1e6e525-3014-4831-af57-4a4f6a17da1c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465685455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 7.gpio_intr_with_filter_rand_intr_event.465685455
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.81891935
Short name T623
Test name
Test status
Simulation time 28309503 ps
CPU time 0.95 seconds
Started Aug 17 05:33:08 PM PDT 24
Finished Aug 17 05:33:09 PM PDT 24
Peak memory 195692 kb
Host smart-9d00c256-b2cc-4fac-afa3-2330352b030d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81891935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.81891935
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.1034891547
Short name T316
Test name
Test status
Simulation time 243286879 ps
CPU time 1.43 seconds
Started Aug 17 05:33:00 PM PDT 24
Finished Aug 17 05:33:02 PM PDT 24
Peak memory 198244 kb
Host smart-9fbbb3ea-8d9d-41d7-984c-85099b7b460d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034891547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.1034891547
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.629116950
Short name T619
Test name
Test status
Simulation time 98690662 ps
CPU time 1 seconds
Started Aug 17 05:33:06 PM PDT 24
Finished Aug 17 05:33:08 PM PDT 24
Peak memory 195928 kb
Host smart-3459d3ce-c9a5-4ea4-96bd-259c679e5bb4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629116950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup_
pulldown.629116950
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.1881514805
Short name T461
Test name
Test status
Simulation time 1695654504 ps
CPU time 5.32 seconds
Started Aug 17 05:33:09 PM PDT 24
Finished Aug 17 05:33:15 PM PDT 24
Peak memory 198160 kb
Host smart-3a57f5e9-276f-4c30-8e30-62788be544ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881514805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.1881514805
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.3552036131
Short name T259
Test name
Test status
Simulation time 161122295 ps
CPU time 1.1 seconds
Started Aug 17 05:32:59 PM PDT 24
Finished Aug 17 05:33:00 PM PDT 24
Peak memory 195804 kb
Host smart-607f9141-6d8d-4392-9f7b-4b6224a2fb65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552036131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.3552036131
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.9070695
Short name T579
Test name
Test status
Simulation time 116898243 ps
CPU time 1.02 seconds
Started Aug 17 05:33:06 PM PDT 24
Finished Aug 17 05:33:07 PM PDT 24
Peak memory 195788 kb
Host smart-e58a6b40-7db2-428d-b58a-337e0d952265
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9070695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.9070695
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.4066908517
Short name T398
Test name
Test status
Simulation time 34689125932 ps
CPU time 211.94 seconds
Started Aug 17 05:33:09 PM PDT 24
Finished Aug 17 05:36:41 PM PDT 24
Peak memory 198332 kb
Host smart-61c0a6ce-b1a2-4d8b-aa07-d6d0fd56ed45
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066908517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.g
pio_stress_all.4066908517
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_stress_all_with_rand_reset.1050263792
Short name T58
Test name
Test status
Simulation time 25824123574 ps
CPU time 82.06 seconds
Started Aug 17 05:33:08 PM PDT 24
Finished Aug 17 05:34:30 PM PDT 24
Peak memory 206744 kb
Host smart-3cac613e-9e1f-457d-a79f-f4f74dedb357
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1050263792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_stress_all_with_rand_reset.1050263792
Directory /workspace/7.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.gpio_alert_test.1188199398
Short name T401
Test name
Test status
Simulation time 11530809 ps
CPU time 0.56 seconds
Started Aug 17 05:33:17 PM PDT 24
Finished Aug 17 05:33:17 PM PDT 24
Peak memory 194012 kb
Host smart-e579a429-9962-46f5-b439-56880a9a412b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188199398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.1188199398
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.1190280460
Short name T240
Test name
Test status
Simulation time 25908062 ps
CPU time 0.79 seconds
Started Aug 17 05:33:08 PM PDT 24
Finished Aug 17 05:33:09 PM PDT 24
Peak memory 195408 kb
Host smart-1fd303bb-36f7-48b1-9759-86ba58817261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190280460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.1190280460
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.2663409955
Short name T271
Test name
Test status
Simulation time 2789954472 ps
CPU time 23.79 seconds
Started Aug 17 05:33:04 PM PDT 24
Finished Aug 17 05:33:28 PM PDT 24
Peak memory 197032 kb
Host smart-24366d6b-15e4-4059-91ce-d144f4aea903
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663409955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.2663409955
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.1897671899
Short name T431
Test name
Test status
Simulation time 56125223 ps
CPU time 0.79 seconds
Started Aug 17 05:33:08 PM PDT 24
Finished Aug 17 05:33:09 PM PDT 24
Peak memory 195968 kb
Host smart-a3dfa61c-8ca3-4335-b7e2-7a7dbedcec33
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897671899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.1897671899
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.1356134171
Short name T630
Test name
Test status
Simulation time 24532326 ps
CPU time 0.69 seconds
Started Aug 17 05:33:09 PM PDT 24
Finished Aug 17 05:33:10 PM PDT 24
Peak memory 195012 kb
Host smart-b84f9392-f790-478b-976e-bf55d0459b36
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356134171 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.1356134171
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.1950090202
Short name T159
Test name
Test status
Simulation time 28074161 ps
CPU time 1.19 seconds
Started Aug 17 05:33:06 PM PDT 24
Finished Aug 17 05:33:07 PM PDT 24
Peak memory 196616 kb
Host smart-0c726f54-e78d-4c61-93dc-5fbf00072ccc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950090202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.1950090202
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.3269454251
Short name T181
Test name
Test status
Simulation time 210755789 ps
CPU time 2.33 seconds
Started Aug 17 05:33:08 PM PDT 24
Finished Aug 17 05:33:11 PM PDT 24
Peak memory 197100 kb
Host smart-5951085a-f8a7-480b-8bbe-963f564ce29d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269454251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
3269454251
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.1816898981
Short name T640
Test name
Test status
Simulation time 219539609 ps
CPU time 0.83 seconds
Started Aug 17 05:33:07 PM PDT 24
Finished Aug 17 05:33:08 PM PDT 24
Peak memory 197468 kb
Host smart-10d1fc57-00a8-452c-9ce8-67e3f652b3e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816898981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.1816898981
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.668730311
Short name T154
Test name
Test status
Simulation time 202722571 ps
CPU time 0.91 seconds
Started Aug 17 05:33:12 PM PDT 24
Finished Aug 17 05:33:13 PM PDT 24
Peak memory 196764 kb
Host smart-34e96172-f77c-45f2-bd27-26534b64a679
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668730311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup_
pulldown.668730311
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.3654839665
Short name T686
Test name
Test status
Simulation time 111883100 ps
CPU time 2.67 seconds
Started Aug 17 05:33:06 PM PDT 24
Finished Aug 17 05:33:09 PM PDT 24
Peak memory 198172 kb
Host smart-a61f406d-76f2-40cb-a961-4b0e5c275a62
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654839665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.3654839665
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.115431383
Short name T333
Test name
Test status
Simulation time 52947409 ps
CPU time 1.05 seconds
Started Aug 17 05:33:09 PM PDT 24
Finished Aug 17 05:33:10 PM PDT 24
Peak memory 195864 kb
Host smart-c7f9fd5b-239f-4d4a-a1aa-4ebf8c86d5e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115431383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.115431383
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.3727729832
Short name T514
Test name
Test status
Simulation time 128956651 ps
CPU time 0.89 seconds
Started Aug 17 05:33:07 PM PDT 24
Finished Aug 17 05:33:08 PM PDT 24
Peak memory 196484 kb
Host smart-09112e5b-c534-412a-9312-e6b8f5852d33
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727729832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.3727729832
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.1178440505
Short name T555
Test name
Test status
Simulation time 2237515134 ps
CPU time 58.13 seconds
Started Aug 17 05:33:09 PM PDT 24
Finished Aug 17 05:34:08 PM PDT 24
Peak memory 198276 kb
Host smart-cb931416-36c0-404f-89e9-9304767afa5b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178440505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.1178440505
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_alert_test.982461212
Short name T668
Test name
Test status
Simulation time 52042226 ps
CPU time 0.57 seconds
Started Aug 17 05:33:23 PM PDT 24
Finished Aug 17 05:33:23 PM PDT 24
Peak memory 194260 kb
Host smart-788e09dc-badb-4c8f-bb93-12531f184785
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982461212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.982461212
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.2949336666
Short name T599
Test name
Test status
Simulation time 90312342 ps
CPU time 0.78 seconds
Started Aug 17 05:33:16 PM PDT 24
Finished Aug 17 05:33:17 PM PDT 24
Peak memory 196044 kb
Host smart-99dbe042-1133-406f-8ff4-982fdb143e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949336666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.2949336666
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.1657499677
Short name T338
Test name
Test status
Simulation time 633189823 ps
CPU time 15.77 seconds
Started Aug 17 05:33:17 PM PDT 24
Finished Aug 17 05:33:33 PM PDT 24
Peak memory 197120 kb
Host smart-bfd0addf-607f-4052-bb04-6abc720d70e9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657499677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.1657499677
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.1130624950
Short name T544
Test name
Test status
Simulation time 61213668 ps
CPU time 0.85 seconds
Started Aug 17 05:33:15 PM PDT 24
Finished Aug 17 05:33:16 PM PDT 24
Peak memory 196016 kb
Host smart-0a378a2c-dc56-4f83-9df9-62119ffd0a5e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130624950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.1130624950
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.697366357
Short name T318
Test name
Test status
Simulation time 422879783 ps
CPU time 1.23 seconds
Started Aug 17 05:33:15 PM PDT 24
Finished Aug 17 05:33:16 PM PDT 24
Peak memory 197236 kb
Host smart-420a9a8e-a2da-4c2f-99a9-2e723211a288
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697366357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.697366357
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.304289916
Short name T710
Test name
Test status
Simulation time 105240615 ps
CPU time 1.16 seconds
Started Aug 17 05:33:17 PM PDT 24
Finished Aug 17 05:33:18 PM PDT 24
Peak memory 196908 kb
Host smart-a1cbe463-b1bb-4365-af5d-8d09f33de61c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304289916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 9.gpio_intr_with_filter_rand_intr_event.304289916
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.3413514024
Short name T346
Test name
Test status
Simulation time 207466093 ps
CPU time 2.04 seconds
Started Aug 17 05:33:15 PM PDT 24
Finished Aug 17 05:33:17 PM PDT 24
Peak memory 195904 kb
Host smart-7ad999d0-ad4c-4978-b5b6-5d71fd874b6c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413514024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
3413514024
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.1132946760
Short name T212
Test name
Test status
Simulation time 307905552 ps
CPU time 1.03 seconds
Started Aug 17 05:33:18 PM PDT 24
Finished Aug 17 05:33:19 PM PDT 24
Peak memory 196092 kb
Host smart-d03fdc3c-7749-4eb5-9163-1f711ddea539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132946760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.1132946760
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.4127399028
Short name T706
Test name
Test status
Simulation time 25390103 ps
CPU time 0.73 seconds
Started Aug 17 05:33:14 PM PDT 24
Finished Aug 17 05:33:14 PM PDT 24
Peak memory 195532 kb
Host smart-bb134d11-451f-4204-90be-bc8c66d2d1b3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127399028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.4127399028
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.349668859
Short name T439
Test name
Test status
Simulation time 346048274 ps
CPU time 3.79 seconds
Started Aug 17 05:33:12 PM PDT 24
Finished Aug 17 05:33:16 PM PDT 24
Peak memory 198036 kb
Host smart-61bc550d-12be-4ebf-a8f3-d2713b9ca33f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349668859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand
om_long_reg_writes_reg_reads.349668859
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.3482035943
Short name T268
Test name
Test status
Simulation time 28725475 ps
CPU time 0.88 seconds
Started Aug 17 05:33:17 PM PDT 24
Finished Aug 17 05:33:18 PM PDT 24
Peak memory 195892 kb
Host smart-8cbba67f-4bea-45f8-8b5d-fdbcb477a678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482035943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.3482035943
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.1654151726
Short name T378
Test name
Test status
Simulation time 54787617 ps
CPU time 0.87 seconds
Started Aug 17 05:33:15 PM PDT 24
Finished Aug 17 05:33:16 PM PDT 24
Peak memory 196568 kb
Host smart-ae754bf4-cafe-4224-89ae-54d1470added
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654151726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.1654151726
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.2829591156
Short name T406
Test name
Test status
Simulation time 1990860422 ps
CPU time 26.59 seconds
Started Aug 17 05:33:21 PM PDT 24
Finished Aug 17 05:33:48 PM PDT 24
Peak memory 198232 kb
Host smart-0672c9de-760b-4984-b0cd-ff95315de8a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829591156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.2829591156
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.2627872192
Short name T849
Test name
Test status
Simulation time 100774524 ps
CPU time 1.52 seconds
Started Aug 17 05:27:59 PM PDT 24
Finished Aug 17 05:28:01 PM PDT 24
Peak memory 191404 kb
Host smart-91f6ff88-b658-49a3-96b1-40254444e445
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2627872192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.2627872192
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1289114079
Short name T850
Test name
Test status
Simulation time 91638475 ps
CPU time 1.05 seconds
Started Aug 17 05:27:39 PM PDT 24
Finished Aug 17 05:27:40 PM PDT 24
Peak memory 197680 kb
Host smart-8e4be3b5-a050-4ed6-804b-92144438eff7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289114079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1289114079
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.1223816150
Short name T899
Test name
Test status
Simulation time 99567267 ps
CPU time 1.09 seconds
Started Aug 17 05:27:33 PM PDT 24
Finished Aug 17 05:27:34 PM PDT 24
Peak memory 191288 kb
Host smart-49c8c754-c89f-4996-bfff-a535d72c02e1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1223816150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.1223816150
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3923653523
Short name T903
Test name
Test status
Simulation time 64599899 ps
CPU time 1.09 seconds
Started Aug 17 05:27:57 PM PDT 24
Finished Aug 17 05:27:58 PM PDT 24
Peak memory 191372 kb
Host smart-a9dcf1c0-3096-47dd-9cc8-ab8a9091d2ec
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923653523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3923653523
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.552794816
Short name T879
Test name
Test status
Simulation time 189284287 ps
CPU time 1.51 seconds
Started Aug 17 05:27:59 PM PDT 24
Finished Aug 17 05:28:01 PM PDT 24
Peak memory 197728 kb
Host smart-52be3208-8e8b-4782-8a42-e52defedb07e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=552794816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.552794816
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.930533976
Short name T875
Test name
Test status
Simulation time 143408622 ps
CPU time 1.03 seconds
Started Aug 17 05:27:58 PM PDT 24
Finished Aug 17 05:27:59 PM PDT 24
Peak memory 191372 kb
Host smart-7266006d-e69f-4bde-9a6f-8d79b04528b5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930533976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.930533976
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.328457614
Short name T919
Test name
Test status
Simulation time 168061469 ps
CPU time 1.28 seconds
Started Aug 17 05:27:53 PM PDT 24
Finished Aug 17 05:27:55 PM PDT 24
Peak memory 196936 kb
Host smart-792a4a70-4488-451a-b345-435545b39354
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=328457614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.328457614
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2657561137
Short name T888
Test name
Test status
Simulation time 262392393 ps
CPU time 1.17 seconds
Started Aug 17 05:27:59 PM PDT 24
Finished Aug 17 05:28:01 PM PDT 24
Peak memory 191404 kb
Host smart-47d38282-4f26-469a-b5a4-d11a2d09a969
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657561137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2657561137
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.3097759331
Short name T856
Test name
Test status
Simulation time 167924044 ps
CPU time 1.33 seconds
Started Aug 17 05:27:53 PM PDT 24
Finished Aug 17 05:27:55 PM PDT 24
Peak memory 191404 kb
Host smart-976b9d33-fbca-41f9-8a74-db4d794c2939
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3097759331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.3097759331
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1925312058
Short name T857
Test name
Test status
Simulation time 187066628 ps
CPU time 1.14 seconds
Started Aug 17 05:27:53 PM PDT 24
Finished Aug 17 05:27:54 PM PDT 24
Peak memory 191284 kb
Host smart-de4c10ba-9716-46cb-96b5-8febcd80b191
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925312058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1925312058
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.1525568784
Short name T840
Test name
Test status
Simulation time 43611967 ps
CPU time 1.14 seconds
Started Aug 17 05:27:47 PM PDT 24
Finished Aug 17 05:27:48 PM PDT 24
Peak memory 197672 kb
Host smart-b323ba26-c25f-4a0d-8528-6fc675ae084b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1525568784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.1525568784
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3001574187
Short name T913
Test name
Test status
Simulation time 32007247 ps
CPU time 1 seconds
Started Aug 17 05:27:40 PM PDT 24
Finished Aug 17 05:27:41 PM PDT 24
Peak memory 191400 kb
Host smart-99418aaf-17be-41e3-bb36-d752543c27d2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001574187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3001574187
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.4101260676
Short name T884
Test name
Test status
Simulation time 109155638 ps
CPU time 1.13 seconds
Started Aug 17 05:27:43 PM PDT 24
Finished Aug 17 05:27:44 PM PDT 24
Peak memory 191404 kb
Host smart-bf904e4d-ad0a-490b-9681-f4f86d46962f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4101260676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.4101260676
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2955132632
Short name T867
Test name
Test status
Simulation time 59666087 ps
CPU time 1.22 seconds
Started Aug 17 05:27:52 PM PDT 24
Finished Aug 17 05:27:53 PM PDT 24
Peak memory 191248 kb
Host smart-c66c37b3-6eae-4871-a27d-9c8caa75a40f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955132632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2955132632
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.2734830436
Short name T872
Test name
Test status
Simulation time 88557742 ps
CPU time 0.84 seconds
Started Aug 17 05:27:52 PM PDT 24
Finished Aug 17 05:27:53 PM PDT 24
Peak memory 195552 kb
Host smart-4bce66b7-f3f4-4f3d-a661-866a3071fd52
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2734830436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.2734830436
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.501913493
Short name T880
Test name
Test status
Simulation time 172378691 ps
CPU time 0.95 seconds
Started Aug 17 05:27:56 PM PDT 24
Finished Aug 17 05:27:57 PM PDT 24
Peak memory 191168 kb
Host smart-97223ab8-225b-4d89-9b76-61f1e0505c82
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501913493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.501913493
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.3151851061
Short name T871
Test name
Test status
Simulation time 99479282 ps
CPU time 0.94 seconds
Started Aug 17 05:27:47 PM PDT 24
Finished Aug 17 05:27:48 PM PDT 24
Peak memory 191172 kb
Host smart-beb64652-c01b-4992-ab4b-cde3f6cd24b9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3151851061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.3151851061
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3059981472
Short name T920
Test name
Test status
Simulation time 47910820 ps
CPU time 1.13 seconds
Started Aug 17 05:27:35 PM PDT 24
Finished Aug 17 05:27:36 PM PDT 24
Peak memory 191296 kb
Host smart-1d98bbec-20ab-41b6-bb1d-24ded3300de9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059981472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3059981472
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.2343845423
Short name T914
Test name
Test status
Simulation time 442799462 ps
CPU time 0.81 seconds
Started Aug 17 05:27:41 PM PDT 24
Finished Aug 17 05:27:42 PM PDT 24
Peak memory 195820 kb
Host smart-1d8ebe07-3243-486d-8f18-3dc5a7c70f7c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2343845423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.2343845423
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4135378861
Short name T907
Test name
Test status
Simulation time 233620073 ps
CPU time 1.27 seconds
Started Aug 17 05:27:59 PM PDT 24
Finished Aug 17 05:28:00 PM PDT 24
Peak memory 191412 kb
Host smart-95c2f598-fdfa-45c4-b3dc-f28a248c38d4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135378861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4135378861
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.3408616488
Short name T864
Test name
Test status
Simulation time 40822456 ps
CPU time 0.89 seconds
Started Aug 17 05:27:38 PM PDT 24
Finished Aug 17 05:27:39 PM PDT 24
Peak memory 197024 kb
Host smart-da7d9b14-bf15-4183-88f9-9eb482c80c46
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3408616488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.3408616488
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2174596353
Short name T934
Test name
Test status
Simulation time 56712801 ps
CPU time 1.21 seconds
Started Aug 17 05:28:01 PM PDT 24
Finished Aug 17 05:28:03 PM PDT 24
Peak memory 197696 kb
Host smart-0e3d789f-862b-425f-b47c-6ade1e1b5086
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174596353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2174596353
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.4281938872
Short name T878
Test name
Test status
Simulation time 341108000 ps
CPU time 1.49 seconds
Started Aug 17 05:27:45 PM PDT 24
Finished Aug 17 05:27:46 PM PDT 24
Peak memory 197644 kb
Host smart-0c7ff6ce-533b-4aba-b365-27e5d2568ad0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4281938872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.4281938872
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2579982523
Short name T835
Test name
Test status
Simulation time 26803641 ps
CPU time 0.82 seconds
Started Aug 17 05:27:56 PM PDT 24
Finished Aug 17 05:27:56 PM PDT 24
Peak memory 191172 kb
Host smart-317de5fa-9455-49a6-9948-3784acf76cf4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579982523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2579982523
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.3107272114
Short name T874
Test name
Test status
Simulation time 45211362 ps
CPU time 1.33 seconds
Started Aug 17 05:27:37 PM PDT 24
Finished Aug 17 05:27:38 PM PDT 24
Peak memory 191404 kb
Host smart-0c9d549b-9d16-4288-ad37-c40dabc2f829
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3107272114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.3107272114
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2598134817
Short name T869
Test name
Test status
Simulation time 118308682 ps
CPU time 0.99 seconds
Started Aug 17 05:27:34 PM PDT 24
Finished Aug 17 05:27:35 PM PDT 24
Peak memory 191372 kb
Host smart-03d1aa9a-08e8-4868-92d6-9e650fe956b6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598134817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2598134817
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.3006427025
Short name T918
Test name
Test status
Simulation time 58655530 ps
CPU time 0.92 seconds
Started Aug 17 05:27:45 PM PDT 24
Finished Aug 17 05:27:46 PM PDT 24
Peak memory 195772 kb
Host smart-2b2e59f0-54d8-4bb1-a7fa-3ab9920954f1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3006427025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.3006427025
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.694483508
Short name T845
Test name
Test status
Simulation time 59088399 ps
CPU time 0.97 seconds
Started Aug 17 05:27:47 PM PDT 24
Finished Aug 17 05:27:48 PM PDT 24
Peak memory 197660 kb
Host smart-9362bec3-57b7-40c6-a2cd-57271d0190f7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694483508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.694483508
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.922779505
Short name T895
Test name
Test status
Simulation time 18729474 ps
CPU time 0.77 seconds
Started Aug 17 05:27:53 PM PDT 24
Finished Aug 17 05:27:54 PM PDT 24
Peak memory 191160 kb
Host smart-9d000e23-7533-46b5-af5d-ddbc86f095c5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=922779505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.922779505
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1449992735
Short name T847
Test name
Test status
Simulation time 51532678 ps
CPU time 1.33 seconds
Started Aug 17 05:27:59 PM PDT 24
Finished Aug 17 05:28:00 PM PDT 24
Peak memory 191320 kb
Host smart-e9103f42-4199-4ab4-8fab-b7fe662ee636
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449992735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1449992735
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.3982101298
Short name T843
Test name
Test status
Simulation time 69915878 ps
CPU time 1.13 seconds
Started Aug 17 05:27:58 PM PDT 24
Finished Aug 17 05:27:59 PM PDT 24
Peak memory 191360 kb
Host smart-fbdfac7e-30ba-4fbb-984c-706465a0b64c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3982101298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.3982101298
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2996026958
Short name T910
Test name
Test status
Simulation time 52773553 ps
CPU time 1.32 seconds
Started Aug 17 05:27:48 PM PDT 24
Finished Aug 17 05:27:50 PM PDT 24
Peak memory 197684 kb
Host smart-e0d45ddb-2cbb-4d4d-9382-e636f6b4f21f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996026958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2996026958
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.789259200
Short name T923
Test name
Test status
Simulation time 35339453 ps
CPU time 0.79 seconds
Started Aug 17 05:27:56 PM PDT 24
Finished Aug 17 05:27:57 PM PDT 24
Peak memory 191096 kb
Host smart-c7f2ac37-dc85-4ba8-b9e3-0b9d4dfc7a3b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=789259200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.789259200
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1535544
Short name T908
Test name
Test status
Simulation time 281500406 ps
CPU time 1.37 seconds
Started Aug 17 05:27:45 PM PDT 24
Finished Aug 17 05:27:46 PM PDT 24
Peak memory 197744 kb
Host smart-39160a90-e0aa-47bb-8eec-8d28b599b852
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown_en
_cdc_prim.1535544
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.1974129705
Short name T848
Test name
Test status
Simulation time 65354812 ps
CPU time 1.29 seconds
Started Aug 17 05:27:59 PM PDT 24
Finished Aug 17 05:28:00 PM PDT 24
Peak memory 191352 kb
Host smart-0bdbdc4b-c8ab-4557-94c2-a4dc7dd0d90c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1974129705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.1974129705
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.302062591
Short name T882
Test name
Test status
Simulation time 149332408 ps
CPU time 1.18 seconds
Started Aug 17 05:27:48 PM PDT 24
Finished Aug 17 05:27:49 PM PDT 24
Peak memory 191352 kb
Host smart-02bc8e20-d4bc-4b5e-afc8-ac09c1aa5f42
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302062591 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.302062591
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.863682971
Short name T922
Test name
Test status
Simulation time 92236603 ps
CPU time 1.24 seconds
Started Aug 17 05:28:02 PM PDT 24
Finished Aug 17 05:28:03 PM PDT 24
Peak memory 197724 kb
Host smart-d9124c58-9ca1-48c0-b1c3-9ce70b28f606
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=863682971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.863682971
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.885874355
Short name T839
Test name
Test status
Simulation time 21529168 ps
CPU time 0.78 seconds
Started Aug 17 05:27:56 PM PDT 24
Finished Aug 17 05:27:57 PM PDT 24
Peak memory 195772 kb
Host smart-69a679c7-bafb-453c-85ef-5ab298f4a4d3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885874355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.885874355
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.2673879551
Short name T894
Test name
Test status
Simulation time 76940756 ps
CPU time 1.34 seconds
Started Aug 17 05:27:50 PM PDT 24
Finished Aug 17 05:27:51 PM PDT 24
Peak memory 191344 kb
Host smart-5e7a7997-c682-41ae-94be-760bddf4d0e9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2673879551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.2673879551
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1207559048
Short name T851
Test name
Test status
Simulation time 28047276 ps
CPU time 0.82 seconds
Started Aug 17 05:28:01 PM PDT 24
Finished Aug 17 05:28:02 PM PDT 24
Peak memory 191168 kb
Host smart-d54674fa-f2fe-49bc-aaa7-a1df5e5481f6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207559048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1207559048
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.3110450973
Short name T890
Test name
Test status
Simulation time 92833640 ps
CPU time 1.39 seconds
Started Aug 17 05:27:58 PM PDT 24
Finished Aug 17 05:27:59 PM PDT 24
Peak memory 191364 kb
Host smart-19e77d78-570c-4434-91d2-f71ccdfe4fbd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3110450973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.3110450973
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3409994901
Short name T906
Test name
Test status
Simulation time 267690996 ps
CPU time 1.07 seconds
Started Aug 17 05:28:00 PM PDT 24
Finished Aug 17 05:28:01 PM PDT 24
Peak memory 191424 kb
Host smart-3a31d0d8-8759-44ef-a404-3a9defc2105b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409994901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3409994901
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.2112579
Short name T885
Test name
Test status
Simulation time 806949935 ps
CPU time 1.2 seconds
Started Aug 17 05:27:59 PM PDT 24
Finished Aug 17 05:28:00 PM PDT 24
Peak memory 191368 kb
Host smart-51ee31b1-f013-44de-a485-df41ec015112
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2112579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.2112579
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.61459344
Short name T868
Test name
Test status
Simulation time 71846200 ps
CPU time 0.89 seconds
Started Aug 17 05:27:49 PM PDT 24
Finished Aug 17 05:27:50 PM PDT 24
Peak memory 191168 kb
Host smart-f22e39b5-d648-41af-b5f3-9d7362728c5c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61459344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.61459344
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.2789724963
Short name T876
Test name
Test status
Simulation time 81519537 ps
CPU time 1.43 seconds
Started Aug 17 05:27:48 PM PDT 24
Finished Aug 17 05:27:50 PM PDT 24
Peak memory 191400 kb
Host smart-a4dffa98-5442-4694-baea-c53929b1ac0a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2789724963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.2789724963
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3500060316
Short name T927
Test name
Test status
Simulation time 61816384 ps
CPU time 1.03 seconds
Started Aug 17 05:27:59 PM PDT 24
Finished Aug 17 05:28:01 PM PDT 24
Peak memory 191260 kb
Host smart-53fd707d-148d-4f88-a9d4-30c727f6767d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500060316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3500060316
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.1858747183
Short name T873
Test name
Test status
Simulation time 67220707 ps
CPU time 1.19 seconds
Started Aug 17 05:27:56 PM PDT 24
Finished Aug 17 05:27:58 PM PDT 24
Peak memory 191304 kb
Host smart-968fbc9b-c266-4129-9b8c-cf93951c3872
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1858747183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.1858747183
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.43120846
Short name T930
Test name
Test status
Simulation time 583354011 ps
CPU time 1.32 seconds
Started Aug 17 05:27:53 PM PDT 24
Finished Aug 17 05:27:54 PM PDT 24
Peak memory 197656 kb
Host smart-873331de-2a28-4a11-9c29-b20a9dbf7173
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43120846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_en
_cdc_prim.43120846
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.2622697858
Short name T891
Test name
Test status
Simulation time 51209524 ps
CPU time 0.89 seconds
Started Aug 17 05:28:00 PM PDT 24
Finished Aug 17 05:28:01 PM PDT 24
Peak memory 191136 kb
Host smart-11d0262a-b65b-4474-b0f8-c69530960082
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2622697858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.2622697858
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.929255060
Short name T877
Test name
Test status
Simulation time 51934068 ps
CPU time 0.94 seconds
Started Aug 17 05:27:53 PM PDT 24
Finished Aug 17 05:27:54 PM PDT 24
Peak memory 191140 kb
Host smart-2cb136b7-9d39-4b86-9747-6f9ec5d12d42
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929255060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.929255060
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.2283079459
Short name T931
Test name
Test status
Simulation time 40766626 ps
CPU time 0.95 seconds
Started Aug 17 05:28:01 PM PDT 24
Finished Aug 17 05:28:02 PM PDT 24
Peak memory 191196 kb
Host smart-974e12e9-f649-424f-a300-f7d583fae79d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2283079459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.2283079459
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3991019054
Short name T852
Test name
Test status
Simulation time 296813307 ps
CPU time 1.37 seconds
Started Aug 17 05:27:57 PM PDT 24
Finished Aug 17 05:27:58 PM PDT 24
Peak memory 191392 kb
Host smart-339da324-6865-4912-8a9d-60f46d36a4f1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991019054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3991019054
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.1144278530
Short name T844
Test name
Test status
Simulation time 31465327 ps
CPU time 0.91 seconds
Started Aug 17 05:28:05 PM PDT 24
Finished Aug 17 05:28:11 PM PDT 24
Peak memory 195816 kb
Host smart-2ee075ea-1f25-4086-81b0-401e9f6bfd97
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1144278530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.1144278530
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4002989793
Short name T837
Test name
Test status
Simulation time 173094128 ps
CPU time 1.31 seconds
Started Aug 17 05:27:51 PM PDT 24
Finished Aug 17 05:27:53 PM PDT 24
Peak memory 191380 kb
Host smart-5bda1a59-1487-4675-b0df-cb6dc53c2716
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002989793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4002989793
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.2289412328
Short name T838
Test name
Test status
Simulation time 64064712 ps
CPU time 1.26 seconds
Started Aug 17 05:27:53 PM PDT 24
Finished Aug 17 05:27:54 PM PDT 24
Peak memory 196064 kb
Host smart-0fd166f6-bd45-4aa0-bc62-c1f0aae4a8d0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2289412328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.2289412328
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.683020250
Short name T909
Test name
Test status
Simulation time 103092581 ps
CPU time 1.33 seconds
Started Aug 17 05:27:51 PM PDT 24
Finished Aug 17 05:27:53 PM PDT 24
Peak memory 191400 kb
Host smart-cf864080-2f13-4839-bd27-66c71a045fec
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683020250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.683020250
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.1546897947
Short name T926
Test name
Test status
Simulation time 252113447 ps
CPU time 1.17 seconds
Started Aug 17 05:27:42 PM PDT 24
Finished Aug 17 05:27:43 PM PDT 24
Peak memory 191392 kb
Host smart-4fe74ce4-8852-4b49-bd00-b24f93f146fe
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1546897947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.1546897947
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2833563451
Short name T859
Test name
Test status
Simulation time 52002598 ps
CPU time 0.81 seconds
Started Aug 17 05:27:55 PM PDT 24
Finished Aug 17 05:27:56 PM PDT 24
Peak memory 195892 kb
Host smart-dbf2b5b1-6b67-4d2f-9802-75fb1612e632
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833563451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2833563451
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.3015616154
Short name T853
Test name
Test status
Simulation time 95157146 ps
CPU time 1.26 seconds
Started Aug 17 05:27:58 PM PDT 24
Finished Aug 17 05:28:00 PM PDT 24
Peak memory 191372 kb
Host smart-c2c579cf-6f96-4226-8438-dba2a703f82a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3015616154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.3015616154
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2573291808
Short name T836
Test name
Test status
Simulation time 56328146 ps
CPU time 1.06 seconds
Started Aug 17 05:27:48 PM PDT 24
Finished Aug 17 05:27:49 PM PDT 24
Peak memory 191404 kb
Host smart-61fe20e3-bd90-4202-9a9d-d1e17947cac5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573291808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2573291808
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.2427678968
Short name T870
Test name
Test status
Simulation time 106687145 ps
CPU time 1.06 seconds
Started Aug 17 05:27:51 PM PDT 24
Finished Aug 17 05:27:52 PM PDT 24
Peak memory 191400 kb
Host smart-8415fae5-c69e-49ff-b317-eb8ff604ee87
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2427678968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.2427678968
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2133955397
Short name T893
Test name
Test status
Simulation time 320108045 ps
CPU time 1.33 seconds
Started Aug 17 05:27:53 PM PDT 24
Finished Aug 17 05:27:54 PM PDT 24
Peak memory 191376 kb
Host smart-234808c2-9363-4f2f-ae1c-fb99449677e6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133955397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2133955397
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.1771979233
Short name T924
Test name
Test status
Simulation time 41672071 ps
CPU time 0.96 seconds
Started Aug 17 05:28:01 PM PDT 24
Finished Aug 17 05:28:02 PM PDT 24
Peak memory 191376 kb
Host smart-186ee00c-3961-45ee-a960-b3dd153b2ebb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1771979233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.1771979233
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.40233950
Short name T896
Test name
Test status
Simulation time 70933262 ps
CPU time 1.28 seconds
Started Aug 17 05:27:54 PM PDT 24
Finished Aug 17 05:27:55 PM PDT 24
Peak memory 191256 kb
Host smart-de58e1e5-eda1-46a4-973c-ce616a3ef267
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40233950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.40233950
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.1218867296
Short name T858
Test name
Test status
Simulation time 524807347 ps
CPU time 1.05 seconds
Started Aug 17 05:27:55 PM PDT 24
Finished Aug 17 05:27:57 PM PDT 24
Peak memory 191364 kb
Host smart-fe053c74-313f-43ad-9ee4-ac0ba7039feb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1218867296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.1218867296
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2471164936
Short name T892
Test name
Test status
Simulation time 42685881 ps
CPU time 0.89 seconds
Started Aug 17 05:28:01 PM PDT 24
Finished Aug 17 05:28:02 PM PDT 24
Peak memory 191128 kb
Host smart-9e624ea1-3e8d-405f-87c1-25766cb5a9d7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471164936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2471164936
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.3672112129
Short name T915
Test name
Test status
Simulation time 171188364 ps
CPU time 1.33 seconds
Started Aug 17 05:27:59 PM PDT 24
Finished Aug 17 05:28:00 PM PDT 24
Peak memory 197716 kb
Host smart-bfb1419b-e2c1-4166-9cd3-1a01d4d05088
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3672112129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.3672112129
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2017113107
Short name T889
Test name
Test status
Simulation time 34722676 ps
CPU time 0.92 seconds
Started Aug 17 05:27:51 PM PDT 24
Finished Aug 17 05:27:52 PM PDT 24
Peak memory 191168 kb
Host smart-df847f7e-50b4-4b59-ab87-7d7b86a43735
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017113107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2017113107
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.91348437
Short name T932
Test name
Test status
Simulation time 60537875 ps
CPU time 1.04 seconds
Started Aug 17 05:27:41 PM PDT 24
Finished Aug 17 05:27:43 PM PDT 24
Peak memory 191184 kb
Host smart-7628c39f-cca5-44ab-bd13-7623bbe6d355
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=91348437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.91348437
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3276738896
Short name T887
Test name
Test status
Simulation time 79956461 ps
CPU time 0.67 seconds
Started Aug 17 05:27:56 PM PDT 24
Finished Aug 17 05:27:57 PM PDT 24
Peak memory 194632 kb
Host smart-0f7c28f3-3864-4c20-8213-8779e5d78a3c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276738896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3276738896
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.1492158781
Short name T904
Test name
Test status
Simulation time 55667370 ps
CPU time 1.14 seconds
Started Aug 17 05:27:55 PM PDT 24
Finished Aug 17 05:27:56 PM PDT 24
Peak memory 197708 kb
Host smart-d6683053-0d84-4331-b1c2-46a4d7895027
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1492158781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.1492158781
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1830973341
Short name T865
Test name
Test status
Simulation time 32769163 ps
CPU time 0.94 seconds
Started Aug 17 05:27:59 PM PDT 24
Finished Aug 17 05:28:00 PM PDT 24
Peak memory 196660 kb
Host smart-a1f8766f-897d-4cae-a3d5-22d8b40c2a7d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830973341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1830973341
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.3797378314
Short name T902
Test name
Test status
Simulation time 155012152 ps
CPU time 0.98 seconds
Started Aug 17 05:27:45 PM PDT 24
Finished Aug 17 05:27:46 PM PDT 24
Peak memory 191392 kb
Host smart-ae60adfb-92c0-4b01-be96-7aba3a0dd5c3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3797378314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.3797378314
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2575904089
Short name T861
Test name
Test status
Simulation time 128793656 ps
CPU time 1.02 seconds
Started Aug 17 05:27:58 PM PDT 24
Finished Aug 17 05:27:59 PM PDT 24
Peak memory 191404 kb
Host smart-72896a14-59ef-4ab0-8e90-25de4b48426f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575904089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2575904089
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.3019451817
Short name T883
Test name
Test status
Simulation time 461417526 ps
CPU time 1.27 seconds
Started Aug 17 05:27:50 PM PDT 24
Finished Aug 17 05:27:52 PM PDT 24
Peak memory 196256 kb
Host smart-dfb76b03-cd2f-424a-8995-43cbad8abfd6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3019451817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.3019451817
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1262260520
Short name T911
Test name
Test status
Simulation time 53039552 ps
CPU time 0.9 seconds
Started Aug 17 05:28:00 PM PDT 24
Finished Aug 17 05:28:01 PM PDT 24
Peak memory 191200 kb
Host smart-5fb0ed9e-08e5-4824-96e3-cedbf0202040
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262260520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1262260520
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.1607495251
Short name T841
Test name
Test status
Simulation time 73223805 ps
CPU time 1.48 seconds
Started Aug 17 05:27:55 PM PDT 24
Finished Aug 17 05:27:56 PM PDT 24
Peak memory 191304 kb
Host smart-ed7ac235-2aa8-4752-8794-2109ce5af37c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1607495251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.1607495251
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1523600631
Short name T886
Test name
Test status
Simulation time 93664864 ps
CPU time 0.87 seconds
Started Aug 17 05:27:51 PM PDT 24
Finished Aug 17 05:27:52 PM PDT 24
Peak memory 195744 kb
Host smart-57c262c4-7e54-48dd-b558-b6ed1a2a02c6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523600631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1523600631
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.1043796512
Short name T921
Test name
Test status
Simulation time 321080937 ps
CPU time 1.46 seconds
Started Aug 17 05:28:01 PM PDT 24
Finished Aug 17 05:28:03 PM PDT 24
Peak memory 191404 kb
Host smart-4900f36f-3063-416b-8dca-c1b19f39b51b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1043796512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.1043796512
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.457464768
Short name T860
Test name
Test status
Simulation time 45845572 ps
CPU time 1.34 seconds
Started Aug 17 05:28:01 PM PDT 24
Finished Aug 17 05:28:03 PM PDT 24
Peak memory 191404 kb
Host smart-9602edc1-7bf4-48f6-b5c5-fd21798ce640
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457464768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.457464768
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.22000261
Short name T900
Test name
Test status
Simulation time 122318533 ps
CPU time 1.34 seconds
Started Aug 17 05:27:54 PM PDT 24
Finished Aug 17 05:27:56 PM PDT 24
Peak memory 191396 kb
Host smart-c02d0412-3112-49ec-83ab-a9627576516f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=22000261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.22000261
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2487315213
Short name T855
Test name
Test status
Simulation time 91460346 ps
CPU time 1.38 seconds
Started Aug 17 05:27:57 PM PDT 24
Finished Aug 17 05:27:59 PM PDT 24
Peak memory 191400 kb
Host smart-adde325d-34b4-4170-a5c5-2c59d178bcb6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487315213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2487315213
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.1840502252
Short name T912
Test name
Test status
Simulation time 244041366 ps
CPU time 1.03 seconds
Started Aug 17 05:27:57 PM PDT 24
Finished Aug 17 05:27:58 PM PDT 24
Peak memory 191364 kb
Host smart-0f546642-6b17-4db3-8fa4-eef50b93d63c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1840502252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.1840502252
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3029118211
Short name T933
Test name
Test status
Simulation time 63765634 ps
CPU time 1.13 seconds
Started Aug 17 05:27:47 PM PDT 24
Finished Aug 17 05:27:49 PM PDT 24
Peak memory 191340 kb
Host smart-39938a8e-bced-4eef-ae2e-ee805ec1cf85
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029118211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3029118211
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.798255464
Short name T897
Test name
Test status
Simulation time 512165800 ps
CPU time 1.01 seconds
Started Aug 17 05:28:01 PM PDT 24
Finished Aug 17 05:28:02 PM PDT 24
Peak memory 191364 kb
Host smart-aa8c59eb-c813-45df-967c-99916aefdd19
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=798255464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.798255464
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1748606844
Short name T928
Test name
Test status
Simulation time 103903062 ps
CPU time 1.1 seconds
Started Aug 17 05:27:54 PM PDT 24
Finished Aug 17 05:27:56 PM PDT 24
Peak memory 197704 kb
Host smart-54fa0852-ac53-452f-a6b4-a0a9764d1d1f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748606844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1748606844
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.1320114821
Short name T881
Test name
Test status
Simulation time 248122810 ps
CPU time 1.26 seconds
Started Aug 17 05:27:50 PM PDT 24
Finished Aug 17 05:27:51 PM PDT 24
Peak memory 191308 kb
Host smart-93d671a4-97b7-43ee-b19d-ac96d4cec861
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1320114821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.1320114821
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1291871304
Short name T925
Test name
Test status
Simulation time 42920491 ps
CPU time 0.91 seconds
Started Aug 17 05:28:04 PM PDT 24
Finished Aug 17 05:28:05 PM PDT 24
Peak memory 195812 kb
Host smart-2bd55d62-9c2a-42d8-bb37-706bbbab5c0a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291871304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1291871304
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.1354753921
Short name T929
Test name
Test status
Simulation time 86169794 ps
CPU time 0.84 seconds
Started Aug 17 05:27:58 PM PDT 24
Finished Aug 17 05:27:59 PM PDT 24
Peak memory 191140 kb
Host smart-c8996a66-770d-4988-8baf-29daaf8a09a7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1354753921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.1354753921
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1400744131
Short name T854
Test name
Test status
Simulation time 67674562 ps
CPU time 1.13 seconds
Started Aug 17 05:27:58 PM PDT 24
Finished Aug 17 05:28:00 PM PDT 24
Peak memory 191396 kb
Host smart-d8a654c1-dfe9-4687-bb24-c1ab32708e7c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400744131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1400744131
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.3510542280
Short name T846
Test name
Test status
Simulation time 99918563 ps
CPU time 0.97 seconds
Started Aug 17 05:27:32 PM PDT 24
Finished Aug 17 05:27:33 PM PDT 24
Peak memory 197680 kb
Host smart-5d626ab6-972b-4d4f-adea-9e024e5a8c26
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3510542280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.3510542280
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3452408217
Short name T917
Test name
Test status
Simulation time 695152849 ps
CPU time 1.25 seconds
Started Aug 17 05:28:00 PM PDT 24
Finished Aug 17 05:28:02 PM PDT 24
Peak memory 196384 kb
Host smart-592fa2fa-79fb-44f0-9423-522badc4b3de
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452408217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3452408217
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.2021412300
Short name T905
Test name
Test status
Simulation time 31199193 ps
CPU time 0.7 seconds
Started Aug 17 05:27:53 PM PDT 24
Finished Aug 17 05:27:54 PM PDT 24
Peak memory 191172 kb
Host smart-5149ef02-8825-4a24-a826-6f3804dbb512
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2021412300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.2021412300
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2720181909
Short name T901
Test name
Test status
Simulation time 171121881 ps
CPU time 1.11 seconds
Started Aug 17 05:27:34 PM PDT 24
Finished Aug 17 05:27:36 PM PDT 24
Peak memory 191356 kb
Host smart-7d445e21-aceb-45b2-b275-56ebf3ba3ca4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720181909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2720181909
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.3727455265
Short name T916
Test name
Test status
Simulation time 498101935 ps
CPU time 0.88 seconds
Started Aug 17 05:27:53 PM PDT 24
Finished Aug 17 05:27:55 PM PDT 24
Peak memory 191184 kb
Host smart-697d31ab-b663-463e-9042-d31a18e3d295
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3727455265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.3727455265
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.69576614
Short name T863
Test name
Test status
Simulation time 158782676 ps
CPU time 1.53 seconds
Started Aug 17 05:27:59 PM PDT 24
Finished Aug 17 05:28:00 PM PDT 24
Peak memory 197692 kb
Host smart-997aebe8-f07c-4a8b-8fde-4759b60be8fc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69576614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_en
_cdc_prim.69576614
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.54119123
Short name T866
Test name
Test status
Simulation time 64704426 ps
CPU time 1.22 seconds
Started Aug 17 05:27:41 PM PDT 24
Finished Aug 17 05:27:42 PM PDT 24
Peak memory 191340 kb
Host smart-b1603c9e-d442-40ee-88d4-2577c1c441dc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=54119123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.54119123
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.525440901
Short name T898
Test name
Test status
Simulation time 69929724 ps
CPU time 0.77 seconds
Started Aug 17 05:27:59 PM PDT 24
Finished Aug 17 05:27:59 PM PDT 24
Peak memory 191156 kb
Host smart-b4122a57-5587-4ef1-bdab-030c62d224e1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525440901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.525440901
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.1760876450
Short name T862
Test name
Test status
Simulation time 290174810 ps
CPU time 1.27 seconds
Started Aug 17 05:28:04 PM PDT 24
Finished Aug 17 05:28:05 PM PDT 24
Peak memory 191400 kb
Host smart-1883614f-2b68-4f98-9117-fc3443c8e31a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1760876450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.1760876450
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1779282894
Short name T842
Test name
Test status
Simulation time 28779074 ps
CPU time 0.75 seconds
Started Aug 17 05:27:54 PM PDT 24
Finished Aug 17 05:27:55 PM PDT 24
Peak memory 194684 kb
Host smart-47196571-8651-47fb-b9bc-aa4eda907b43
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779282894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1779282894
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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