Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	1447656	1			T25	87		T26	1		T27	1
all_pins[1]	1447656	1			T25	87		T26	1		T27	1
all_pins[2]	1447656	1			T25	87		T26	1		T27	1
all_pins[3]	1447656	1			T25	87		T26	1		T27	1
all_pins[4]	1447656	1			T25	87		T26	1		T27	1
all_pins[5]	1447656	1			T25	87		T26	1		T27	1
all_pins[6]	1447656	1			T25	87		T26	1		T27	1
all_pins[7]	1447656	1			T25	87		T26	1		T27	1
all_pins[8]	1447656	1			T25	87		T26	1		T27	1
all_pins[9]	1447656	1			T25	87		T26	1		T27	1
all_pins[10]	1447656	1			T25	87		T26	1		T27	1
all_pins[11]	1447656	1			T25	87		T26	1		T27	1
all_pins[12]	1447656	1			T25	87		T26	1		T27	1
all_pins[13]	1447656	1			T25	87		T26	1		T27	1
all_pins[14]	1447656	1			T25	87		T26	1		T27	1
all_pins[15]	1447656	1			T25	87		T26	1		T27	1
all_pins[16]	1447656	1			T25	87		T26	1		T27	1
all_pins[17]	1447656	1			T25	87		T26	1		T27	1
all_pins[18]	1447656	1			T25	87		T26	1		T27	1
all_pins[19]	1447656	1			T25	87		T26	1		T27	1
all_pins[20]	1447656	1			T25	87		T26	1		T27	1
all_pins[21]	1447656	1			T25	87		T26	1		T27	1
all_pins[22]	1447656	1			T25	87		T26	1		T27	1
all_pins[23]	1447656	1			T25	87		T26	1		T27	1
all_pins[24]	1447656	1			T25	87		T26	1		T27	1
all_pins[25]	1447656	1			T25	87		T26	1		T27	1
all_pins[26]	1447656	1			T25	87		T26	1		T27	1
all_pins[27]	1447656	1			T25	87		T26	1		T27	1
all_pins[28]	1447656	1			T25	87		T26	1		T27	1
all_pins[29]	1447656	1			T25	87		T26	1		T27	1
all_pins[30]	1447656	1			T25	87		T26	1		T27	1
all_pins[31]	1447656	1			T25	87		T26	1		T27	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	28831642	1			T25	1484		T26	32		T27	32
values[0x1]	17493350	1			T25	1300		T28	326		T1	254524
transitions[0x0=>0x1]	10483770	1			T25	683		T28	218		T1	152142
transitions[0x1=>0x0]	10483622	1			T25	682		T28	218		T1	152142

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	902177	1			T25	41		T26	1		T27	1
all_pins[0]	values[0x1]	545479	1			T25	46		T28	9		T1	7677
all_pins[0]	transitions[0x0=>0x1]	337734	1			T25	28		T28	6		T1	4708
all_pins[0]	transitions[0x1=>0x0]	336708	1			T25	20		T28	4		T1	4882
all_pins[1]	values[0x0]	902529	1			T25	46		T26	1		T27	1
all_pins[1]	values[0x1]	545127	1			T25	41		T28	11		T1	7864
all_pins[1]	transitions[0x0=>0x1]	327083	1			T25	18		T28	8		T1	4789
all_pins[1]	transitions[0x1=>0x0]	327435	1			T25	23		T28	6		T1	4602
all_pins[2]	values[0x0]	898814	1			T25	45		T26	1		T27	1
all_pins[2]	values[0x1]	548842	1			T25	42		T28	13		T1	7951
all_pins[2]	transitions[0x0=>0x1]	330455	1			T25	21		T28	9		T1	4873
all_pins[2]	transitions[0x1=>0x0]	326740	1			T25	20		T28	7		T1	4786
all_pins[3]	values[0x0]	902633	1			T25	52		T26	1		T27	1
all_pins[3]	values[0x1]	545023	1			T25	35		T28	15		T1	7928
all_pins[3]	transitions[0x0=>0x1]	325157	1			T25	16		T28	5		T1	4807
all_pins[3]	transitions[0x1=>0x0]	328976	1			T25	23		T28	3		T1	4830
all_pins[4]	values[0x0]	902591	1			T25	44		T26	1		T27	1
all_pins[4]	values[0x1]	545065	1			T25	43		T28	16		T1	8011
all_pins[4]	transitions[0x0=>0x1]	326612	1			T25	28		T28	12		T1	4769
all_pins[4]	transitions[0x1=>0x0]	326570	1			T25	20		T28	11		T1	4686
all_pins[5]	values[0x0]	900931	1			T25	53		T26	1		T27	1
all_pins[5]	values[0x1]	546725	1			T25	34		T28	9		T1	8381
all_pins[5]	transitions[0x0=>0x1]	328373	1			T25	17		T28	1		T1	4929
all_pins[5]	transitions[0x1=>0x0]	326713	1			T25	26		T28	8		T1	4559
all_pins[6]	values[0x0]	897553	1			T25	53		T26	1		T27	1
all_pins[6]	values[0x1]	550103	1			T25	34		T28	10		T1	7687
all_pins[6]	transitions[0x0=>0x1]	329781	1			T25	19		T28	3		T1	4335
all_pins[6]	transitions[0x1=>0x0]	326403	1			T25	19		T28	2		T1	5029
all_pins[7]	values[0x0]	902123	1			T25	35		T26	1		T27	1
all_pins[7]	values[0x1]	545533	1			T25	52		T28	11		T1	8067
all_pins[7]	transitions[0x0=>0x1]	324334	1			T25	33		T28	10		T1	4823
all_pins[7]	transitions[0x1=>0x0]	328904	1			T25	15		T28	9		T1	4443
all_pins[8]	values[0x0]	902624	1			T25	42		T26	1		T27	1
all_pins[8]	values[0x1]	545032	1			T25	45		T28	7		T1	7735
all_pins[8]	transitions[0x0=>0x1]	325376	1			T25	18		T28	1		T1	4716
all_pins[8]	transitions[0x1=>0x0]	325877	1			T25	25		T28	5		T1	5048
all_pins[9]	values[0x0]	902761	1			T25	40		T26	1		T27	1
all_pins[9]	values[0x1]	544895	1			T25	47		T28	5		T1	8379
all_pins[9]	transitions[0x0=>0x1]	326978	1			T25	23		T28	5		T1	4922
all_pins[9]	transitions[0x1=>0x0]	327115	1			T25	21		T28	7		T1	4278
all_pins[10]	values[0x0]	901223	1			T25	47		T26	1		T27	1
all_pins[10]	values[0x1]	546433	1			T25	40		T28	8		T1	7878
all_pins[10]	transitions[0x0=>0x1]	327268	1			T25	18		T28	8		T1	4485
all_pins[10]	transitions[0x1=>0x0]	325730	1			T25	25		T28	5		T1	4986
all_pins[11]	values[0x0]	901831	1			T25	55		T26	1		T27	1
all_pins[11]	values[0x1]	545825	1			T25	32		T28	18		T1	8254
all_pins[11]	transitions[0x0=>0x1]	326310	1			T25	17		T28	18		T1	5007
all_pins[11]	transitions[0x1=>0x0]	326918	1			T25	25		T28	8		T1	4631
all_pins[12]	values[0x0]	901696	1			T25	44		T26	1		T27	1
all_pins[12]	values[0x1]	545960	1			T25	43		T28	8		T1	7867
all_pins[12]	transitions[0x0=>0x1]	327020	1			T25	32		T28	5		T1	4406
all_pins[12]	transitions[0x1=>0x0]	326885	1			T25	21		T28	15		T1	4793
all_pins[13]	values[0x0]	901371	1			T25	54		T26	1		T27	1
all_pins[13]	values[0x1]	546285	1			T25	33		T28	4		T1	7930
all_pins[13]	transitions[0x0=>0x1]	328071	1			T25	17		T28	1		T1	4783
all_pins[13]	transitions[0x1=>0x0]	327746	1			T25	27		T28	5		T1	4720
all_pins[14]	values[0x0]	901357	1			T25	47		T26	1		T27	1
all_pins[14]	values[0x1]	546299	1			T25	40		T1	8197		T12	55
all_pins[14]	transitions[0x0=>0x1]	328491	1			T25	20		T1	4950		T12	34
all_pins[14]	transitions[0x1=>0x0]	328477	1			T25	13		T28	4		T1	4683
all_pins[15]	values[0x0]	900851	1			T25	51		T26	1		T27	1
all_pins[15]	values[0x1]	546805	1			T25	36		T28	6		T1	8002
all_pins[15]	transitions[0x0=>0x1]	327455	1			T25	21		T28	6		T1	4755
all_pins[15]	transitions[0x1=>0x0]	326949	1			T25	25		T1	4950		T12	28
all_pins[16]	values[0x0]	900561	1			T25	51		T26	1		T27	1
all_pins[16]	values[0x1]	547095	1			T25	36		T28	17		T1	7929
all_pins[16]	transitions[0x0=>0x1]	327168	1			T25	22		T28	14		T1	4777
all_pins[16]	transitions[0x1=>0x0]	326878	1			T25	22		T28	3		T1	4850
all_pins[17]	values[0x0]	903938	1			T25	40		T26	1		T27	1
all_pins[17]	values[0x1]	543718	1			T25	47		T28	6		T1	7808
all_pins[17]	transitions[0x0=>0x1]	324769	1			T25	28		T28	1		T1	4646
all_pins[17]	transitions[0x1=>0x0]	328146	1			T25	17		T28	12		T1	4767
all_pins[18]	values[0x0]	898604	1			T25	41		T26	1		T27	1
all_pins[18]	values[0x1]	549052	1			T25	46		T28	14		T1	7676
all_pins[18]	transitions[0x0=>0x1]	329326	1			T25	23		T28	13		T1	4537
all_pins[18]	transitions[0x1=>0x0]	323992	1			T25	24		T28	5		T1	4669
all_pins[19]	values[0x0]	902618	1			T25	50		T26	1		T27	1
all_pins[19]	values[0x1]	545038	1			T25	37		T28	18		T1	8082
all_pins[19]	transitions[0x0=>0x1]	324631	1			T25	13		T28	13		T1	4974
all_pins[19]	transitions[0x1=>0x0]	328645	1			T25	22		T28	9		T1	4568
all_pins[20]	values[0x0]	901779	1			T25	38		T26	1		T27	1
all_pins[20]	values[0x1]	545877	1			T25	49		T28	16		T1	8176
all_pins[20]	transitions[0x0=>0x1]	327445	1			T25	29		T28	6		T1	4882
all_pins[20]	transitions[0x1=>0x0]	326606	1			T25	17		T28	8		T1	4788
all_pins[21]	values[0x0]	899936	1			T25	55		T26	1		T27	1
all_pins[21]	values[0x1]	547720	1			T25	32		T28	9		T1	8000
all_pins[21]	transitions[0x0=>0x1]	329227	1			T25	14		T28	2		T1	4825
all_pins[21]	transitions[0x1=>0x0]	327384	1			T25	31		T28	9		T1	5001
all_pins[22]	values[0x0]	900591	1			T25	39		T26	1		T27	1
all_pins[22]	values[0x1]	547065	1			T25	48		T28	4		T1	7563
all_pins[22]	transitions[0x0=>0x1]	326671	1			T25	33		T28	3		T1	4513
all_pins[22]	transitions[0x1=>0x0]	327326	1			T25	17		T28	8		T1	4950
all_pins[23]	values[0x0]	900184	1			T25	42		T26	1		T27	1
all_pins[23]	values[0x1]	547472	1			T25	45		T28	10		T1	8005
all_pins[23]	transitions[0x0=>0x1]	327779	1			T25	20		T28	10		T1	4826
all_pins[23]	transitions[0x1=>0x0]	327372	1			T25	23		T28	4		T1	4384
all_pins[24]	values[0x0]	901446	1			T25	52		T26	1		T27	1
all_pins[24]	values[0x1]	546210	1			T25	35		T28	5		T1	8051
all_pins[24]	transitions[0x0=>0x1]	326822	1			T25	16		T28	5		T1	4813
all_pins[24]	transitions[0x1=>0x0]	328084	1			T25	26		T28	10		T1	4767
all_pins[25]	values[0x0]	897614	1			T25	42		T26	1		T27	1
all_pins[25]	values[0x1]	550042	1			T25	45		T28	14		T1	7899
all_pins[25]	transitions[0x0=>0x1]	328309	1			T25	21		T28	14		T1	4738
all_pins[25]	transitions[0x1=>0x0]	324477	1			T25	11		T28	5		T1	4890
all_pins[26]	values[0x0]	898181	1			T25	47		T26	1		T27	1
all_pins[26]	values[0x1]	549475	1			T25	40		T28	13		T1	7840
all_pins[26]	transitions[0x0=>0x1]	327894	1			T25	16		T28	9		T1	4686
all_pins[26]	transitions[0x1=>0x0]	328461	1			T25	21		T28	10		T1	4745
all_pins[27]	values[0x0]	900901	1			T25	48		T26	1		T27	1
all_pins[27]	values[0x1]	546755	1			T25	39		T28	12		T1	7933
all_pins[27]	transitions[0x0=>0x1]	326294	1			T25	20		T28	9		T1	4738
all_pins[27]	transitions[0x1=>0x0]	329014	1			T25	21		T28	10		T1	4645
all_pins[28]	values[0x0]	898490	1			T25	47		T26	1		T27	1
all_pins[28]	values[0x1]	549166	1			T25	40		T28	10		T1	8163
all_pins[28]	transitions[0x0=>0x1]	330383	1			T25	20		T28	2		T1	4991
all_pins[28]	transitions[0x1=>0x0]	327972	1			T25	19		T28	4		T1	4761
all_pins[29]	values[0x0]	900142	1			T25	52		T26	1		T27	1
all_pins[29]	values[0x1]	547514	1			T25	35		T28	13		T1	7997
all_pins[29]	transitions[0x0=>0x1]	326823	1			T25	18		T28	9		T1	4752
all_pins[29]	transitions[0x1=>0x0]	328475	1			T25	23		T28	6		T1	4918
all_pins[30]	values[0x0]	900537	1			T25	43		T26	1		T27	1
all_pins[30]	values[0x1]	547119	1			T25	44		T28	8		T1	7743
all_pins[30]	transitions[0x0=>0x1]	328039	1			T25	27		T28	6		T1	4594
all_pins[30]	transitions[0x1=>0x0]	328434	1			T25	18		T28	11		T1	4848
all_pins[31]	values[0x0]	903055	1			T25	48		T26	1		T27	1
all_pins[31]	values[0x1]	544601	1			T25	39		T28	7		T1	7851
all_pins[31]	transitions[0x0=>0x1]	325692	1			T25	17		T28	4		T1	4793
all_pins[31]	transitions[0x1=>0x0]	328210	1			T25	22		T28	5		T1	4685