Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	5977136	1			T25	39876		T26	131		T27	21
all_values[1]	5977136	1			T25	39876		T26	131		T27	21
all_values[2]	5977136	1			T25	39876		T26	131		T27	21
all_values[3]	5977136	1			T25	39876		T26	131		T27	21
all_values[4]	5977136	1			T25	39876		T26	131		T27	21
all_values[5]	5977136	1			T25	39876		T26	131		T27	21
all_values[6]	5977136	1			T25	39876		T26	131		T27	21
all_values[7]	5977136	1			T25	39876		T26	131		T27	21
all_values[8]	5977136	1			T25	39876		T26	131		T27	21
all_values[9]	5977136	1			T25	39876		T26	131		T27	21
all_values[10]	5977136	1			T25	39876		T26	131		T27	21
all_values[11]	5977136	1			T25	39876		T26	131		T27	21
all_values[12]	5977136	1			T25	39876		T26	131		T27	21
all_values[13]	5977136	1			T25	39876		T26	131		T27	21
all_values[14]	5977136	1			T25	39876		T26	131		T27	21
all_values[15]	5977136	1			T25	39876		T26	131		T27	21
all_values[16]	5977136	1			T25	39876		T26	131		T27	21
all_values[17]	5977136	1			T25	39876		T26	131		T27	21
all_values[18]	5977136	1			T25	39876		T26	131		T27	21
all_values[19]	5977136	1			T25	39876		T26	131		T27	21
all_values[20]	5977136	1			T25	39876		T26	131		T27	21
all_values[21]	5977136	1			T25	39876		T26	131		T27	21
all_values[22]	5977136	1			T25	39876		T26	131		T27	21
all_values[23]	5977136	1			T25	39876		T26	131		T27	21
all_values[24]	5977136	1			T25	39876		T26	131		T27	21
all_values[25]	5977136	1			T25	39876		T26	131		T27	21
all_values[26]	5977136	1			T25	39876		T26	131		T27	21
all_values[27]	5977136	1			T25	39876		T26	131		T27	21
all_values[28]	5977136	1			T25	39876		T26	131		T27	21
all_values[29]	5977136	1			T25	39876		T26	131		T27	21
all_values[30]	5977136	1			T25	39876		T26	131		T27	21
all_values[31]	5977136	1			T25	39876		T26	131		T27	21

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

129162451

1

T25

127603

T26

4192

T27

672

auto[1]

62105901

1

T28

964

T1

971632

T13

1903

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

79394535

1

T25

127603

T26

4192

T27

672

auto[1]

111873817

1

T28

912

T1

176008

T13

3670

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

189497551

1

T25

127603

T26

4192

T27

672

auto[1]

1770801

1

T28

102

T1

37149

T38

2406

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	2281714	1			T25	39876		T26	131		T27	21
all_values[0]	auto[0]	auto[0]	auto[1]	1730633	1			T28	6		T1	27341		T13	102
all_values[0]	auto[0]	auto[1]	auto[0]	198185	1			T28	14		T1	3171		T13	5
all_values[0]	auto[0]	auto[1]	auto[1]	1711030	1			T28	14		T1	26292		T18	488
all_values[0]	auto[1]	auto[0]	auto[1]	28197	1			T28	2		T1	593		T38	41
all_values[0]	auto[1]	auto[1]	auto[1]	27377	1			T28	2		T1	529		T38	28
all_values[1]	auto[0]	auto[0]	auto[0]	2281766	1			T25	39876		T26	131		T27	21
all_values[1]	auto[0]	auto[0]	auto[1]	1722804	1			T28	8		T1	26675		T13	26
all_values[1]	auto[0]	auto[1]	auto[0]	196515	1			T28	32		T1	3024		T13	21
all_values[1]	auto[0]	auto[1]	auto[1]	1720756	1			T28	13		T1	27319		T13	88
all_values[1]	auto[1]	auto[0]	auto[1]	27812	1			T28	1		T1	558		T38	40
all_values[1]	auto[1]	auto[1]	auto[1]	27483	1			T28	3		T1	593		T38	44
all_values[2]	auto[0]	auto[0]	auto[0]	2280086	1			T25	39876		T26	131		T27	21
all_values[2]	auto[0]	auto[0]	auto[1]	1721588	1			T28	5		T1	27408		T13	66
all_values[2]	auto[0]	auto[1]	auto[0]	199901	1			T28	17		T1	3369		T13	5
all_values[2]	auto[0]	auto[1]	auto[1]	1720235	1			T28	20		T1	26284		T13	57
all_values[2]	auto[1]	auto[0]	auto[1]	27770	1			T28	1		T1	564		T38	40
all_values[2]	auto[1]	auto[1]	auto[1]	27556	1			T28	1		T1	571		T38	32
all_values[3]	auto[0]	auto[0]	auto[0]	2287976	1			T25	39876		T26	131		T27	21
all_values[3]	auto[0]	auto[0]	auto[1]	1727732	1			T28	11		T1	26511		T13	98
all_values[3]	auto[0]	auto[1]	auto[0]	200734	1			T28	15		T1	3007		T18	32
all_values[3]	auto[0]	auto[1]	auto[1]	1705173	1			T28	19		T1	27166		T13	32
all_values[3]	auto[1]	auto[0]	auto[1]	27965	1			T28	2		T1	577		T38	30
all_values[3]	auto[1]	auto[1]	auto[1]	27556	1			T28	2		T1	595		T38	34
all_values[4]	auto[0]	auto[0]	auto[0]	2280298	1			T25	39876		T26	131		T27	21
all_values[4]	auto[0]	auto[0]	auto[1]	1734598	1			T28	12		T1	26957		T13	70
all_values[4]	auto[0]	auto[1]	auto[0]	201794	1			T28	19		T1	3046		T13	10
all_values[4]	auto[0]	auto[1]	auto[1]	1705460	1			T28	21		T1	26949		T13	30
all_values[4]	auto[1]	auto[0]	auto[1]	27704	1			T28	1		T1	596		T38	42
all_values[4]	auto[1]	auto[1]	auto[1]	27282	1			T28	3		T1	559		T38	23
all_values[5]	auto[0]	auto[0]	auto[0]	2280902	1			T25	39876		T26	131		T27	21
all_values[5]	auto[0]	auto[0]	auto[1]	1725558	1			T28	9		T1	25639		T13	26
all_values[5]	auto[0]	auto[1]	auto[0]	200322	1			T28	28		T1	2914		T13	7
all_values[5]	auto[0]	auto[1]	auto[1]	1715099	1			T28	15		T1	27825		T13	93
all_values[5]	auto[1]	auto[0]	auto[1]	27403	1			T1	533		T38	43		T30	405
all_values[5]	auto[1]	auto[1]	auto[1]	27852	1			T1	623		T38	40		T30	404
all_values[6]	auto[0]	auto[0]	auto[0]	2280767	1			T25	39876		T26	131		T27	21
all_values[6]	auto[0]	auto[0]	auto[1]	1722067	1			T28	11		T1	27837		T13	83
all_values[6]	auto[0]	auto[1]	auto[0]	195897	1			T28	18		T1	3005		T13	5
all_values[6]	auto[0]	auto[1]	auto[1]	1723184	1			T28	15		T1	25939		T13	34
all_values[6]	auto[1]	auto[0]	auto[1]	27898	1			T1	574		T38	38		T30	370
all_values[6]	auto[1]	auto[1]	auto[1]	27323	1			T28	4		T1	571		T38	27
all_values[7]	auto[0]	auto[0]	auto[0]	2283655	1			T25	39876		T26	131		T27	21
all_values[7]	auto[0]	auto[0]	auto[1]	1722569	1			T28	6		T1	26851		T13	55
all_values[7]	auto[0]	auto[1]	auto[0]	195545	1			T28	19		T1	2735		T13	6
all_values[7]	auto[0]	auto[1]	auto[1]	1719870	1			T28	9		T1	27421		T13	53
all_values[7]	auto[1]	auto[0]	auto[1]	27878	1			T1	623		T38	40		T30	417
all_values[7]	auto[1]	auto[1]	auto[1]	27619	1			T28	2		T1	582		T38	39
all_values[8]	auto[0]	auto[0]	auto[0]	2282891	1			T25	39876		T26	131		T27	21
all_values[8]	auto[0]	auto[0]	auto[1]	1725124	1			T28	19		T1	27185		T13	93
all_values[8]	auto[0]	auto[1]	auto[0]	197520	1			T28	19		T1	3242		T13	7
all_values[8]	auto[0]	auto[1]	auto[1]	1716372	1			T28	5		T1	26631		T13	24
all_values[8]	auto[1]	auto[0]	auto[1]	28143	1			T28	3		T1	615		T38	29
all_values[8]	auto[1]	auto[1]	auto[1]	27086	1			T28	2		T1	546		T38	41
all_values[9]	auto[0]	auto[0]	auto[0]	2283873	1			T25	39876		T26	131		T27	21
all_values[9]	auto[0]	auto[0]	auto[1]	1718897	1			T28	21		T1	26932		T13	95
all_values[9]	auto[0]	auto[1]	auto[0]	197523	1			T28	10		T1	2931		T18	29
all_values[9]	auto[0]	auto[1]	auto[1]	1721331	1			T28	4		T1	26693		T13	26
all_values[9]	auto[1]	auto[0]	auto[1]	27995	1			T28	3		T1	581		T38	46
all_values[9]	auto[1]	auto[1]	auto[1]	27517	1			T1	605		T38	28		T30	361
all_values[10]	auto[0]	auto[0]	auto[0]	2282456	1			T25	39876		T26	131		T27	21
all_values[10]	auto[0]	auto[0]	auto[1]	1741444	1			T28	24		T1	28790		T13	79
all_values[10]	auto[0]	auto[1]	auto[0]	197983	1			T28	11		T1	2885		T13	32
all_values[10]	auto[0]	auto[1]	auto[1]	1699921	1			T28	7		T1	25560		T13	19
all_values[10]	auto[1]	auto[0]	auto[1]	27952	1			T28	3		T1	631		T38	38
all_values[10]	auto[1]	auto[1]	auto[1]	27380	1			T28	2		T1	547		T38	42
all_values[11]	auto[0]	auto[0]	auto[0]	2283964	1			T25	39876		T26	131		T27	21
all_values[11]	auto[0]	auto[0]	auto[1]	1718809	1			T28	9		T1	26337		T13	79
all_values[11]	auto[0]	auto[1]	auto[0]	201815	1			T28	14		T1	3270		T13	7
all_values[11]	auto[0]	auto[1]	auto[1]	1717517	1			T28	24		T1	27570		T13	38
all_values[11]	auto[1]	auto[0]	auto[1]	27340	1			T28	1		T1	571		T38	31
all_values[11]	auto[1]	auto[1]	auto[1]	27691	1			T28	2		T1	634		T38	37
all_values[12]	auto[0]	auto[0]	auto[0]	2280055	1			T25	39876		T26	131		T27	21
all_values[12]	auto[0]	auto[0]	auto[1]	1731692	1			T28	22		T1	27347		T13	45
all_values[12]	auto[0]	auto[1]	auto[0]	196263	1			T28	9		T1	3233		T13	4
all_values[12]	auto[0]	auto[1]	auto[1]	1713752	1			T28	8		T1	26608		T13	67
all_values[12]	auto[1]	auto[0]	auto[1]	27854	1			T28	2		T1	592		T38	33
all_values[12]	auto[1]	auto[1]	auto[1]	27520	1			T28	1		T1	564		T38	41
all_values[13]	auto[0]	auto[0]	auto[0]	2278656	1			T25	39876		T26	131		T27	21
all_values[13]	auto[0]	auto[0]	auto[1]	1720056	1			T28	26		T1	26968		T13	49
all_values[13]	auto[0]	auto[1]	auto[0]	200157	1			T28	9		T1	2689		T13	25
all_values[13]	auto[0]	auto[1]	auto[1]	1722802	1			T28	4		T1	27212		T13	61
all_values[13]	auto[1]	auto[0]	auto[1]	27963	1			T28	4		T1	563		T38	38
all_values[13]	auto[1]	auto[1]	auto[1]	27502	1			T28	1		T1	594		T38	40
all_values[14]	auto[0]	auto[0]	auto[0]	2286288	1			T25	39876		T26	131		T27	21
all_values[14]	auto[0]	auto[0]	auto[1]	1721087	1			T28	23		T1	26733		T13	58
all_values[14]	auto[0]	auto[1]	auto[0]	202688	1			T28	10		T1	2704		T13	32
all_values[14]	auto[0]	auto[1]	auto[1]	1712010	1			T1	27515		T13	37		T18	707
all_values[14]	auto[1]	auto[0]	auto[1]	27870	1			T28	2		T1	577		T38	40
all_values[14]	auto[1]	auto[1]	auto[1]	27193	1			T1	580		T38	48		T30	382
all_values[15]	auto[0]	auto[0]	auto[0]	2284363	1			T25	39876		T26	131		T27	21
all_values[15]	auto[0]	auto[0]	auto[1]	1723597	1			T28	19		T1	28067		T13	54
all_values[15]	auto[0]	auto[1]	auto[0]	200379	1			T28	17		T1	3082		T18	37
all_values[15]	auto[0]	auto[1]	auto[1]	1713533	1			T28	7		T1	26179		T13	61
all_values[15]	auto[1]	auto[0]	auto[1]	27797	1			T28	2		T1	586		T38	47
all_values[15]	auto[1]	auto[1]	auto[1]	27467	1			T1	583		T38	34		T30	380
all_values[16]	auto[0]	auto[0]	auto[0]	2277788	1			T25	39876		T26	131		T27	21
all_values[16]	auto[0]	auto[0]	auto[1]	1739401	1			T28	8		T1	26351		T13	62
all_values[16]	auto[0]	auto[1]	auto[0]	197110	1			T28	12		T1	3355		T13	21
all_values[16]	auto[0]	auto[1]	auto[1]	1707300	1			T28	23		T1	27055		T13	51
all_values[16]	auto[1]	auto[0]	auto[1]	27650	1			T28	1		T1	581		T38	52
all_values[16]	auto[1]	auto[1]	auto[1]	27887	1			T28	2		T1	562		T38	36
all_values[17]	auto[0]	auto[0]	auto[0]	2288905	1			T25	39876		T26	131		T27	21
all_values[17]	auto[0]	auto[0]	auto[1]	1741789	1			T28	22		T1	27559		T13	47
all_values[17]	auto[0]	auto[1]	auto[0]	201832	1			T28	19		T1	3739		T13	12
all_values[17]	auto[0]	auto[1]	auto[1]	1689179	1			T28	5		T1	25704		T13	74
all_values[17]	auto[1]	auto[0]	auto[1]	28085	1			T1	587		T38	42		T30	394
all_values[17]	auto[1]	auto[1]	auto[1]	27346	1			T1	577		T38	39		T30	428
all_values[18]	auto[0]	auto[0]	auto[0]	2279520	1			T25	39876		T26	131		T27	21
all_values[18]	auto[0]	auto[0]	auto[1]	1717266	1			T28	12		T1	28482		T13	113
all_values[18]	auto[0]	auto[1]	auto[0]	200568	1			T28	16		T1	2923		T13	1
all_values[18]	auto[0]	auto[1]	auto[1]	1724193	1			T28	12		T1	25826		T13	13
all_values[18]	auto[1]	auto[0]	auto[1]	28076	1			T28	3		T1	597		T38	51
all_values[18]	auto[1]	auto[1]	auto[1]	27513	1			T28	1		T1	553		T38	28
all_values[19]	auto[0]	auto[0]	auto[0]	2281379	1			T25	39876		T26	131		T27	21
all_values[19]	auto[0]	auto[0]	auto[1]	1725125	1			T28	7		T1	26911		T13	87
all_values[19]	auto[0]	auto[1]	auto[0]	192620	1			T28	32		T1	3104		T13	6
all_values[19]	auto[0]	auto[1]	auto[1]	1722691	1			T28	21		T1	27086		T13	35
all_values[19]	auto[1]	auto[0]	auto[1]	28213	1			T1	546		T38	42		T30	408
all_values[19]	auto[1]	auto[1]	auto[1]	27108	1			T28	3		T1	592		T38	35
all_values[20]	auto[0]	auto[0]	auto[0]	2281606	1			T25	39876		T26	131		T27	21
all_values[20]	auto[0]	auto[0]	auto[1]	1730897	1			T28	4		T1	26532		T13	58
all_values[20]	auto[0]	auto[1]	auto[0]	204084	1			T28	35		T1	3043		T13	13
all_values[20]	auto[0]	auto[1]	auto[1]	1704987	1			T28	18		T1	27401		T13	55
all_values[20]	auto[1]	auto[0]	auto[1]	27868	1			T1	598		T38	37		T30	446
all_values[20]	auto[1]	auto[1]	auto[1]	27694	1			T28	4		T1	552		T38	36
all_values[21]	auto[0]	auto[0]	auto[0]	2282179	1			T25	39876		T26	131		T27	21
all_values[21]	auto[0]	auto[0]	auto[1]	1723510	1			T28	12		T1	26832		T13	43
all_values[21]	auto[0]	auto[1]	auto[0]	200340	1			T28	10		T1	3059		T13	11
all_values[21]	auto[0]	auto[1]	auto[1]	1715904	1			T28	9		T1	26366		T13	74
all_values[21]	auto[1]	auto[0]	auto[1]	28075	1			T28	3		T1	577		T38	28
all_values[21]	auto[1]	auto[1]	auto[1]	27128	1			T1	572		T38	45		T30	395
all_values[22]	auto[0]	auto[0]	auto[0]	2282182	1			T25	39876		T26	131		T27	21
all_values[22]	auto[0]	auto[0]	auto[1]	1736140	1			T28	11		T1	27643		T13	54
all_values[22]	auto[0]	auto[1]	auto[0]	196855	1			T28	15		T1	3032		T13	1
all_values[22]	auto[0]	auto[1]	auto[1]	1706522	1			T28	4		T1	26351		T13	77
all_values[22]	auto[1]	auto[0]	auto[1]	27845	1			T28	1		T1	600		T38	32
all_values[22]	auto[1]	auto[1]	auto[1]	27592	1			T28	1		T1	552		T38	43
all_values[23]	auto[0]	auto[0]	auto[0]	2280215	1			T25	39876		T26	131		T27	21
all_values[23]	auto[0]	auto[0]	auto[1]	1729673	1			T28	14		T1	27040		T13	85
all_values[23]	auto[0]	auto[1]	auto[0]	197273	1			T28	14		T1	3070		T13	11
all_values[23]	auto[0]	auto[1]	auto[1]	1714782	1			T28	8		T1	26916		T13	28
all_values[23]	auto[1]	auto[0]	auto[1]	27574	1			T28	3		T1	531		T38	40
all_values[23]	auto[1]	auto[1]	auto[1]	27619	1			T1	585		T38	35		T30	426
all_values[24]	auto[0]	auto[0]	auto[0]	2282985	1			T25	39876		T26	131		T27	21
all_values[24]	auto[0]	auto[0]	auto[1]	1734677	1			T28	23		T1	26128		T13	59
all_values[24]	auto[0]	auto[1]	auto[0]	196864	1			T28	17		T1	3204		T13	4
all_values[24]	auto[0]	auto[1]	auto[1]	1707280	1			T28	2		T1	26843		T13	60
all_values[24]	auto[1]	auto[0]	auto[1]	28196	1			T28	2		T1	589		T38	46
all_values[24]	auto[1]	auto[1]	auto[1]	27134	1			T28	2		T1	604		T38	34
all_values[25]	auto[0]	auto[0]	auto[0]	2282007	1			T25	39876		T26	131		T27	21
all_values[25]	auto[0]	auto[0]	auto[1]	1717440	1			T28	11		T1	27821		T13	67
all_values[25]	auto[0]	auto[1]	auto[0]	195178	1			T28	9		T1	2935		T13	4
all_values[25]	auto[0]	auto[1]	auto[1]	1727126	1			T28	20		T1	26152		T13	44
all_values[25]	auto[1]	auto[0]	auto[1]	27779	1			T28	1		T1	618		T38	50
all_values[25]	auto[1]	auto[1]	auto[1]	27606	1			T28	2		T1	555		T38	25
all_values[26]	auto[0]	auto[0]	auto[0]	2279669	1			T25	39876		T26	131		T27	21
all_values[26]	auto[0]	auto[0]	auto[1]	1706311	1			T28	19		T1	27530		T13	38
all_values[26]	auto[0]	auto[1]	auto[0]	201531	1			T28	11		T1	2753		T13	20
all_values[26]	auto[0]	auto[1]	auto[1]	1734408	1			T28	13		T1	26765		T13	60
all_values[26]	auto[1]	auto[0]	auto[1]	27667	1			T28	2		T1	577		T38	24
all_values[26]	auto[1]	auto[1]	auto[1]	27550	1			T28	1		T1	594		T38	46
all_values[27]	auto[0]	auto[0]	auto[0]	2279969	1			T25	39876		T26	131		T27	21
all_values[27]	auto[0]	auto[0]	auto[1]	1730727	1			T28	11		T1	26549		T13	75
all_values[27]	auto[0]	auto[1]	auto[0]	196436	1			T28	14		T1	2703		T13	4
all_values[27]	auto[0]	auto[1]	auto[1]	1714672	1			T28	17		T1	27426		T13	29
all_values[27]	auto[1]	auto[0]	auto[1]	27913	1			T28	2		T1	585		T38	40
all_values[27]	auto[1]	auto[1]	auto[1]	27419	1			T28	2		T1	573		T38	33
all_values[28]	auto[0]	auto[0]	auto[0]	2280220	1			T25	39876		T26	131		T27	21
all_values[28]	auto[0]	auto[0]	auto[1]	1730763	1			T28	7		T1	27039		T13	25
all_values[28]	auto[0]	auto[1]	auto[0]	198126	1			T28	19		T1	3811		T13	15
all_values[28]	auto[0]	auto[1]	auto[1]	1712536	1			T28	15		T1	25913		T13	88
all_values[28]	auto[1]	auto[0]	auto[1]	27801	1			T28	1		T1	568		T38	34
all_values[28]	auto[1]	auto[1]	auto[1]	27690	1			T28	3		T1	625		T38	42
all_values[29]	auto[0]	auto[0]	auto[0]	2283021	1			T25	39876		T26	131		T27	21
all_values[29]	auto[0]	auto[0]	auto[1]	1723359	1			T28	2		T1	26869		T13	36
all_values[29]	auto[0]	auto[1]	auto[0]	202986	1			T28	15		T1	3137		T13	18
all_values[29]	auto[0]	auto[1]	auto[1]	1712398	1			T28	19		T1	27212		T13	76
all_values[29]	auto[1]	auto[0]	auto[1]	27839	1			T28	2		T1	566		T38	47
all_values[29]	auto[1]	auto[1]	auto[1]	27533	1			T28	2		T1	591		T38	27
all_values[30]	auto[0]	auto[0]	auto[0]	2285732	1			T25	39876		T26	131		T27	21
all_values[30]	auto[0]	auto[0]	auto[1]	1714248	1			T28	19		T1	28054		T13	47
all_values[30]	auto[0]	auto[1]	auto[0]	199503	1			T28	4		T1	2567		T13	1
all_values[30]	auto[0]	auto[1]	auto[1]	1722465	1			T28	8		T1	26374		T13	82
all_values[30]	auto[1]	auto[0]	auto[1]	27785	1			T1	601		T38	25		T30	418
all_values[30]	auto[1]	auto[1]	auto[1]	27403	1			T28	1		T1	553		T38	44
all_values[31]	auto[0]	auto[0]	auto[0]	2281994	1			T25	39876		T26	131		T27	21
all_values[31]	auto[0]	auto[0]	auto[1]	1731978	1			T28	5		T1	27042		T13	104
all_values[31]	auto[0]	auto[1]	auto[0]	200927	1			T28	17		T1	3391		T13	3
all_values[31]	auto[0]	auto[1]	auto[1]	1706969	1			T28	13		T1	26427		T13	26
all_values[31]	auto[1]	auto[0]	auto[1]	27904	1			T28	2		T1	575		T38	37
all_values[31]	auto[1]	auto[1]	auto[1]	27364	1			T28	3		T1	603		T38	37

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal