Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	5971308	1			T25	39876		T26	241		T27	38
bins_for_gpio_bits[1]	5971308	1			T25	39876		T26	241		T27	38
bins_for_gpio_bits[2]	5971308	1			T25	39876		T26	241		T27	38
bins_for_gpio_bits[3]	5971308	1			T25	39876		T26	241		T27	38
bins_for_gpio_bits[4]	5971308	1			T25	39876		T26	241		T27	38
bins_for_gpio_bits[5]	5971308	1			T25	39876		T26	241		T27	38
bins_for_gpio_bits[6]	5971308	1			T25	39876		T26	241		T27	38
bins_for_gpio_bits[7]	5971308	1			T25	39876		T26	241		T27	38
bins_for_gpio_bits[8]	5971308	1			T25	39876		T26	241		T27	38
bins_for_gpio_bits[9]	5971308	1			T25	39876		T26	241		T27	38
bins_for_gpio_bits[10]	5971308	1			T25	39876		T26	241		T27	38
bins_for_gpio_bits[11]	5971308	1			T25	39876		T26	241		T27	38
bins_for_gpio_bits[12]	5971308	1			T25	39876		T26	241		T27	38
bins_for_gpio_bits[13]	5971308	1			T25	39876		T26	241		T27	38
bins_for_gpio_bits[14]	5971308	1			T25	39876		T26	241		T27	38
bins_for_gpio_bits[15]	5971308	1			T25	39876		T26	241		T27	38
bins_for_gpio_bits[16]	5971308	1			T25	39876		T26	241		T27	38
bins_for_gpio_bits[17]	5971308	1			T25	39876		T26	241		T27	38
bins_for_gpio_bits[18]	5971308	1			T25	39876		T26	241		T27	38
bins_for_gpio_bits[19]	5971308	1			T25	39876		T26	241		T27	38
bins_for_gpio_bits[20]	5971308	1			T25	39876		T26	241		T27	38
bins_for_gpio_bits[21]	5971308	1			T25	39876		T26	241		T27	38
bins_for_gpio_bits[22]	5971308	1			T25	39876		T26	241		T27	38
bins_for_gpio_bits[23]	5971308	1			T25	39876		T26	241		T27	38
bins_for_gpio_bits[24]	5971308	1			T25	39876		T26	241		T27	38
bins_for_gpio_bits[25]	5971308	1			T25	39876		T26	241		T27	38
bins_for_gpio_bits[26]	5971308	1			T25	39876		T26	241		T27	38
bins_for_gpio_bits[27]	5971308	1			T25	39876		T26	241		T27	38
bins_for_gpio_bits[28]	5971308	1			T25	39876		T26	241		T27	38
bins_for_gpio_bits[29]	5971308	1			T25	39876		T26	241		T27	38
bins_for_gpio_bits[30]	5971308	1			T25	39876		T26	241		T27	38
bins_for_gpio_bits[31]	5971308	1			T25	39876		T26	241		T27	38

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

103186919

1

T25

647241

T26

1530

T27

175

auto[1]

87894937

1

T25

628791

T26

6182

T27

1041

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

158779350

1

T25

127603

T26

7297

T27

1140

auto[1]

32302506

1

T26

415

T27

76

T28

290

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

149169385

1

T25

127603

T26

3788

T27

572

auto[1]

41912471

1

T26

3924

T27

644

T28

909

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	2204781	1			T25	20147		T26	5		T27	4
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	1951803	1			T25	19729		T26	35		T27	34
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	505586	1			T1	8631		T11	12		T15	16
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	517847	1			T26	35		T28	11		T1	13897
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	285991	1			T26	162		T28	13		T1	979
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	505300	1			T26	4		T28	6		T1	9005
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	2193854	1			T25	21949		T26	40		T28	40
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	1954587	1			T25	17927		T26	145		T27	1
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	503792	1			T26	8		T28	5		T1	9196
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	523761	1			T26	9		T27	5		T28	11
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	290746	1			T26	35		T27	32		T28	6
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	504568	1			T26	4		T28	2		T1	8429
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	2189771	1			T25	20195		T26	31		T27	2
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	1960672	1			T25	19681		T26	125		T27	32
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	510555	1			T26	8		T27	4		T1	9158
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	515388	1			T26	10		T28	29		T1	13411
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	288693	1			T26	61		T28	2		T1	935
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	506229	1			T26	6		T28	3		T1	8897
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	2201460	1			T25	19152		T26	29		T27	3
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	1958426	1			T25	20724		T26	132		T27	14
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	508281	1			T26	10		T28	2		T1	9175
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	517609	1			T26	8		T27	2		T28	27
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	286498	1			T26	62		T27	17		T28	9
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	499034	1			T27	2		T28	3		T1	8664
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	2194021	1			T25	21018		T26	12		T28	53
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	1959890	1			T25	18858		T26	54		T27	1
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	511236	1			T26	4		T28	5		T1	8754
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	518137	1			T26	34		T27	2		T28	15
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	285347	1			T26	131		T27	33		T28	10
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	502677	1			T26	6		T27	2		T28	29
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	2199913	1			T25	19706		T26	30		T27	2
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	1951478	1			T25	20170		T26	155		T27	15
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	508321	1			T26	2		T1	9122		T11	10
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	520511	1			T26	7		T27	4		T28	18
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	287363	1			T26	47		T27	13		T28	18
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	503722	1			T27	4		T28	5		T1	8707
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	2200275	1			T25	20485		T26	26		T28	47
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	1956916	1			T25	19391		T26	141		T27	1
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	507052	1			T26	8		T28	1		T1	9307
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	518115	1			T26	14		T27	5		T28	21
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	287059	1			T26	50		T27	30		T28	11
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	501891	1			T26	2		T27	2		T28	10
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	2200355	1			T25	20391		T26	23		T27	1
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	1946878	1			T25	19485		T26	129		T27	16
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	510033	1			T26	6		T28	9		T1	8929
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	519720	1			T26	11		T27	4		T28	22
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	288389	1			T26	68		T27	15		T28	1
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	505933	1			T26	4		T27	2		T1	9074
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	2191748	1			T25	19714		T26	12		T27	2
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	1964276	1			T25	20162		T26	41		T27	15
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	506651	1			T26	2		T1	8954		T11	10
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	520990	1			T26	41		T27	2		T28	14
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	287951	1			T26	137		T27	17		T28	8
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	499692	1			T26	8		T27	2		T28	14
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	2194734	1			T25	21700		T26	32		T28	76
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	1957861	1			T25	18176		T26	117		T27	1
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	506912	1			T26	12		T28	8		T1	9257
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	518481	1			T26	14		T27	4		T28	29
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	288005	1			T26	58		T27	33		T28	1
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	505315	1			T26	8		T1	8771		T15	6
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	2205324	1			T25	21195		T26	22		T27	5
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	1953545	1			T25	18681		T26	91		T27	31
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	508445	1			T26	10		T27	2		T1	9229
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	515204	1			T26	21		T28	13		T1	13556
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	287115	1			T26	93		T28	1		T1	895
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	501675	1			T26	4		T1	8634		T11	28
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	2201207	1			T25	19780		T26	21		T27	3
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	1951264	1			T25	20096		T26	62		T27	35
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	505460	1			T26	4		T28	1		T1	9629
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	521319	1			T26	24		T28	9		T1	12933
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	289105	1			T26	126		T28	3		T1	907
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	502953	1			T26	4		T28	6		T1	8635
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	2199577	1			T25	21038		T26	28		T28	71
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	1949498	1			T25	18838		T26	71		T27	1
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	509803	1			T26	2		T28	2		T1	8810
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	517373	1			T26	15		T27	3		T28	17
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	290639	1			T26	117		T27	34		T28	13
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	504418	1			T26	8		T28	17		T1	8968
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	2191387	1			T25	19808		T26	16		T27	7
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	1961741	1			T25	20068		T26	53		T27	31
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	506613	1			T26	4		T28	7		T1	8953
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	520912	1			T26	23		T28	15		T1	13112
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	288555	1			T26	141		T28	2		T1	960
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	502100	1			T26	4		T28	3		T1	9151
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	2203939	1			T25	20258		T26	31		T27	6
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	1948477	1			T25	19618		T26	131		T27	30
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	506983	1			T26	6		T27	2		T1	8793
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	521180	1			T26	12		T28	5		T1	13821
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	289490	1			T26	57		T28	10		T1	914
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	501239	1			T26	4		T28	30		T1	8849
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	2197389	1			T25	19457		T26	39		T28	52
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	1954099	1			T25	20419		T26	115		T27	1
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	506730	1			T26	10		T1	8985		T11	13
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	521950	1			T26	9		T27	3		T28	28
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	288324	1			T26	66		T27	32		T28	4
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	502816	1			T26	2		T27	2		T28	2
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	2193546	1			T25	20718		T26	16		T27	6
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	1963167	1			T25	19158		T26	69		T27	30
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	509068	1			T26	12		T27	2		T28	1
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	518179	1			T26	28		T28	6		T1	12957
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	286830	1			T26	109		T28	13		T1	985
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	500518	1			T26	7		T28	10		T1	9321
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	2195157	1			T25	20275		T26	20		T28	70
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	1967083	1			T25	19601		T26	88		T27	5
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	508195	1			T26	4		T28	8		T1	8828
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	516761	1			T26	24		T27	2		T28	7
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	286009	1			T26	101		T27	27		T1	934
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	498103	1			T26	4		T27	4		T1	8991
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	2191754	1			T25	19224		T26	9		T28	64
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	1964277	1			T25	20652		T26	24		T27	1
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	504899	1			T26	2		T28	3		T1	9087
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	520296	1			T26	33		T27	5		T1	13167
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	287217	1			T26	157		T27	27		T28	8
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	502865	1			T26	16		T27	5		T28	2
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	2201098	1			T25	20549		T26	19		T27	4
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	1948683	1			T25	19327		T26	113		T27	32
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	507735	1			T26	4		T27	2		T1	8870
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	521893	1			T26	12		T28	37		T1	13400
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	288996	1			T26	81		T28	15		T1	928
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	502903	1			T26	12		T28	4		T1	8855
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	2197885	1			T25	20393		T26	22		T27	4
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	1955597	1			T25	19483		T26	77		T27	20
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	505311	1			T26	8		T27	6		T28	5
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	521850	1			T26	20		T27	1		T28	17
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	290377	1			T26	112		T27	4		T28	20
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	500288	1			T26	2		T27	3		T28	11
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	2192556	1			T25	19230		T26	6		T27	1
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	1964306	1			T25	20646		T26	45		T27	9
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	505985	1			T26	4		T27	3		T1	8798
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	521608	1			T26	31		T27	4		T28	10
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	288256	1			T26	148		T27	19		T28	6
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	498597	1			T26	7		T27	2		T1	8595
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	2196014	1			T25	20037		T26	14		T28	37
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	1960480	1			T25	19839		T26	59		T27	1
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	506632	1			T26	9		T28	3		T1	8998
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	520848	1			T26	29		T27	6		T28	14
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	287899	1			T26	120		T27	27		T28	3
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	499435	1			T26	10		T27	4		T1	8397
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	2201390	1			T25	21131		T26	31		T27	1
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	1954480	1			T25	18745		T26	116		T27	7
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	507536	1			T26	12		T27	1		T28	4
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	518791	1			T26	10		T27	7		T28	14
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	288626	1			T26	64		T27	18		T28	10
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	500485	1			T26	8		T27	4		T28	4
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	2193748	1			T25	19475		T26	12		T28	72
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	1960583	1			T25	20401		T26	41		T27	8
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	505480	1			T26	6		T27	1		T1	8785
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	522287	1			T26	30		T27	6		T28	14
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	288088	1			T26	138		T27	17		T28	6
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	501122	1			T26	14		T27	6		T28	6
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	2199013	1			T25	20583		T26	32		T28	65
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	1956050	1			T25	19293		T26	128		T27	1
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	505790	1			T26	16		T28	3		T1	9102
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	518753	1			T26	12		T27	4		T28	4
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	288396	1			T26	49		T27	33		T28	5
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	503306	1			T26	4		T28	1		T1	8819
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	2197120	1			T25	18866		T26	9		T27	4
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	1959141	1			T25	21010		T26	63		T27	32
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	504802	1			T26	4		T27	2		T28	2
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	519771	1			T26	19		T28	16		T1	13524
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	287916	1			T26	144		T28	4		T1	965
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	502558	1			T26	2		T1	8803		T11	4
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	2191725	1			T25	19942		T26	43		T27	4
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	1960672	1			T25	19934		T26	150		T27	34
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	508439	1			T26	16		T1	8983		T15	10
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	519520	1			T26	2		T28	13		T1	14165
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	288800	1			T26	30		T28	6		T1	958
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	502152	1			T1	9034		T11	37		T15	2
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	2203621	1			T25	18473		T26	30		T28	48
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	1949332	1			T25	21403		T26	171		T27	1
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	506115	1			T26	8		T28	13		T1	9069
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	521767	1			T26	3		T27	3		T28	15
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	288148	1			T26	29		T27	32		T28	7
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	502325	1			T27	2		T28	10		T1	8831
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	2198411	1			T25	20745		T26	5		T27	4
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	1957155	1			T25	19131		T26	41		T27	34
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	510419	1			T26	2		T28	7		T1	9243
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	517814	1			T26	35		T28	13		T1	13206
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	286144	1			T26	142		T28	6		T1	924
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	501365	1			T26	16		T1	8804		T11	20
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	2199671	1			T25	21016		T26	12		T28	50
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	1957504	1			T25	18860		T26	61		T27	1
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	508646	1			T26	2		T28	12		T1	9007
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	519468	1			T26	30		T27	6		T28	26
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	285174	1			T26	117		T27	31		T28	1
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	500845	1			T26	19		T1	9218		T11	13
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	2201157	1			T25	20591		T26	11		T28	85
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	1951694	1			T25	19285		T26	52		T27	6
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	506664	1			T27	3		T28	5		T1	8910
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	521046	1			T26	32		T27	6		T28	12
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	288839	1			T26	125		T27	21		T28	1
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	501908	1			T26	21		T27	2		T28	6

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal