Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	5971308	1			T25	39876		T26	241		T27	38
bins_for_gpio_bits[1]	5971308	1			T25	39876		T26	241		T27	38
bins_for_gpio_bits[2]	5971308	1			T25	39876		T26	241		T27	38
bins_for_gpio_bits[3]	5971308	1			T25	39876		T26	241		T27	38
bins_for_gpio_bits[4]	5971308	1			T25	39876		T26	241		T27	38
bins_for_gpio_bits[5]	5971308	1			T25	39876		T26	241		T27	38
bins_for_gpio_bits[6]	5971308	1			T25	39876		T26	241		T27	38
bins_for_gpio_bits[7]	5971308	1			T25	39876		T26	241		T27	38
bins_for_gpio_bits[8]	5971308	1			T25	39876		T26	241		T27	38
bins_for_gpio_bits[9]	5971308	1			T25	39876		T26	241		T27	38
bins_for_gpio_bits[10]	5971308	1			T25	39876		T26	241		T27	38
bins_for_gpio_bits[11]	5971308	1			T25	39876		T26	241		T27	38
bins_for_gpio_bits[12]	5971308	1			T25	39876		T26	241		T27	38
bins_for_gpio_bits[13]	5971308	1			T25	39876		T26	241		T27	38
bins_for_gpio_bits[14]	5971308	1			T25	39876		T26	241		T27	38
bins_for_gpio_bits[15]	5971308	1			T25	39876		T26	241		T27	38
bins_for_gpio_bits[16]	5971308	1			T25	39876		T26	241		T27	38
bins_for_gpio_bits[17]	5971308	1			T25	39876		T26	241		T27	38
bins_for_gpio_bits[18]	5971308	1			T25	39876		T26	241		T27	38
bins_for_gpio_bits[19]	5971308	1			T25	39876		T26	241		T27	38
bins_for_gpio_bits[20]	5971308	1			T25	39876		T26	241		T27	38
bins_for_gpio_bits[21]	5971308	1			T25	39876		T26	241		T27	38
bins_for_gpio_bits[22]	5971308	1			T25	39876		T26	241		T27	38
bins_for_gpio_bits[23]	5971308	1			T25	39876		T26	241		T27	38
bins_for_gpio_bits[24]	5971308	1			T25	39876		T26	241		T27	38
bins_for_gpio_bits[25]	5971308	1			T25	39876		T26	241		T27	38
bins_for_gpio_bits[26]	5971308	1			T25	39876		T26	241		T27	38
bins_for_gpio_bits[27]	5971308	1			T25	39876		T26	241		T27	38
bins_for_gpio_bits[28]	5971308	1			T25	39876		T26	241		T27	38
bins_for_gpio_bits[29]	5971308	1			T25	39876		T26	241		T27	38
bins_for_gpio_bits[30]	5971308	1			T25	39876		T26	241		T27	38
bins_for_gpio_bits[31]	5971308	1			T25	39876		T26	241		T27	38

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

103186919

1

T25

647241

T26

1530

T27

175

auto[1]

87894937

1

T25

628791

T26

6182

T27

1041

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

103178328

1

T25

647241

T26

1530

T27

179

auto[1]

87903528

1

T25

628791

T26

6182

T27

1037

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	3136723	1			T25	20147		T26	40		T27	4
bins_for_gpio_bits[0]	auto[0]	auto[1]	91216	1			T1	1572		T11	2		T15	2
bins_for_gpio_bits[0]	auto[1]	auto[0]	91491	1			T1	1579		T11	2		T15	2
bins_for_gpio_bits[0]	auto[1]	auto[1]	2651878	1			T25	19729		T26	201		T27	34
bins_for_gpio_bits[1]	auto[0]	auto[0]	3129966	1			T25	21949		T26	53		T27	5
bins_for_gpio_bits[1]	auto[0]	auto[1]	91152	1			T26	4		T1	1533		T11	1
bins_for_gpio_bits[1]	auto[1]	auto[0]	91441	1			T26	4		T1	1540		T11	2
bins_for_gpio_bits[1]	auto[1]	auto[1]	2658749	1			T25	17927		T26	180		T27	33
bins_for_gpio_bits[2]	auto[0]	auto[0]	3124491	1			T25	20195		T26	45		T27	4
bins_for_gpio_bits[2]	auto[0]	auto[1]	90962	1			T26	4		T27	2		T1	1543
bins_for_gpio_bits[2]	auto[1]	auto[0]	91223	1			T26	4		T27	2		T1	1551
bins_for_gpio_bits[2]	auto[1]	auto[1]	2664632	1			T25	19681		T26	188		T27	30
bins_for_gpio_bits[3]	auto[0]	auto[0]	3136501	1			T25	19152		T26	43		T27	5
bins_for_gpio_bits[3]	auto[0]	auto[1]	90558	1			T26	4		T1	1502		T11	3
bins_for_gpio_bits[3]	auto[1]	auto[0]	90849	1			T26	4		T1	1510		T11	4
bins_for_gpio_bits[3]	auto[1]	auto[1]	2653400	1			T25	20724		T26	190		T27	33
bins_for_gpio_bits[4]	auto[0]	auto[0]	3132061	1			T25	21018		T26	48		T27	2
bins_for_gpio_bits[4]	auto[0]	auto[1]	91058	1			T26	2		T1	1521		T11	1
bins_for_gpio_bits[4]	auto[1]	auto[0]	91333	1			T26	2		T1	1526		T11	1
bins_for_gpio_bits[4]	auto[1]	auto[1]	2656856	1			T25	18858		T26	189		T27	36
bins_for_gpio_bits[5]	auto[0]	auto[0]	3137607	1			T25	19706		T26	38		T27	6
bins_for_gpio_bits[5]	auto[0]	auto[1]	90853	1			T26	1		T1	1517		T11	2
bins_for_gpio_bits[5]	auto[1]	auto[0]	91138	1			T26	1		T1	1527		T11	3
bins_for_gpio_bits[5]	auto[1]	auto[1]	2651710	1			T25	20170		T26	201		T27	32
bins_for_gpio_bits[6]	auto[0]	auto[0]	3134278	1			T25	20485		T26	45		T27	5
bins_for_gpio_bits[6]	auto[0]	auto[1]	90937	1			T26	3		T1	1529		T11	4
bins_for_gpio_bits[6]	auto[1]	auto[0]	91164	1			T26	3		T1	1535		T11	4
bins_for_gpio_bits[6]	auto[1]	auto[1]	2654929	1			T25	19391		T26	190		T27	33
bins_for_gpio_bits[7]	auto[0]	auto[0]	3138608	1			T25	20391		T26	37		T27	5
bins_for_gpio_bits[7]	auto[0]	auto[1]	91243	1			T26	3		T1	1563		T11	3
bins_for_gpio_bits[7]	auto[1]	auto[0]	91500	1			T26	3		T1	1570		T11	3
bins_for_gpio_bits[7]	auto[1]	auto[1]	2649957	1			T25	19485		T26	198		T27	33
bins_for_gpio_bits[8]	auto[0]	auto[0]	3128261	1			T25	19714		T26	54		T27	4
bins_for_gpio_bits[8]	auto[0]	auto[1]	90873	1			T26	1		T1	1542		T11	1
bins_for_gpio_bits[8]	auto[1]	auto[0]	91128	1			T26	1		T1	1545		T11	1
bins_for_gpio_bits[8]	auto[1]	auto[1]	2661046	1			T25	20162		T26	185		T27	34
bins_for_gpio_bits[9]	auto[0]	auto[0]	3129018	1			T25	21700		T26	53		T27	4
bins_for_gpio_bits[9]	auto[0]	auto[1]	90850	1			T26	5		T1	1525		T15	3
bins_for_gpio_bits[9]	auto[1]	auto[0]	91109	1			T26	5		T1	1532		T15	3
bins_for_gpio_bits[9]	auto[1]	auto[1]	2660331	1			T25	18176		T26	178		T27	34
bins_for_gpio_bits[10]	auto[0]	auto[0]	3137731	1			T25	21195		T26	50		T27	6
bins_for_gpio_bits[10]	auto[0]	auto[1]	90957	1			T26	3		T27	1		T1	1502
bins_for_gpio_bits[10]	auto[1]	auto[0]	91242	1			T26	3		T27	1		T1	1508
bins_for_gpio_bits[10]	auto[1]	auto[1]	2651378	1			T25	18681		T26	185		T27	30
bins_for_gpio_bits[11]	auto[0]	auto[0]	3137056	1			T25	19780		T26	47		T27	3
bins_for_gpio_bits[11]	auto[0]	auto[1]	90646	1			T26	2		T1	1506		T11	3
bins_for_gpio_bits[11]	auto[1]	auto[0]	90930	1			T26	2		T1	1514		T11	3
bins_for_gpio_bits[11]	auto[1]	auto[1]	2652676	1			T25	20096		T26	190		T27	35
bins_for_gpio_bits[12]	auto[0]	auto[0]	3135814	1			T25	21038		T26	44		T27	3
bins_for_gpio_bits[12]	auto[0]	auto[1]	90656	1			T26	1		T1	1550		T11	2
bins_for_gpio_bits[12]	auto[1]	auto[0]	90939	1			T26	1		T1	1556		T11	2
bins_for_gpio_bits[12]	auto[1]	auto[1]	2653899	1			T25	18838		T26	195		T27	35
bins_for_gpio_bits[13]	auto[0]	auto[0]	3127672	1			T25	19808		T26	41		T27	7
bins_for_gpio_bits[13]	auto[0]	auto[1]	91000	1			T26	2		T1	1537		T11	1
bins_for_gpio_bits[13]	auto[1]	auto[0]	91240	1			T26	2		T1	1543		T11	1
bins_for_gpio_bits[13]	auto[1]	auto[1]	2661396	1			T25	20068		T26	196		T27	31
bins_for_gpio_bits[14]	auto[0]	auto[0]	3141115	1			T25	20258		T26	46		T27	7
bins_for_gpio_bits[14]	auto[0]	auto[1]	90701	1			T26	3		T27	1		T1	1576
bins_for_gpio_bits[14]	auto[1]	auto[0]	90987	1			T26	3		T27	1		T1	1584
bins_for_gpio_bits[14]	auto[1]	auto[1]	2648505	1			T25	19618		T26	189		T27	29
bins_for_gpio_bits[15]	auto[0]	auto[0]	3134623	1			T25	19457		T26	54		T27	3
bins_for_gpio_bits[15]	auto[0]	auto[1]	91185	1			T26	4		T1	1548		T11	2
bins_for_gpio_bits[15]	auto[1]	auto[0]	91446	1			T26	4		T1	1556		T11	3
bins_for_gpio_bits[15]	auto[1]	auto[1]	2654054	1			T25	20419		T26	179		T27	35
bins_for_gpio_bits[16]	auto[0]	auto[0]	3129393	1			T25	20718		T26	51		T27	7
bins_for_gpio_bits[16]	auto[0]	auto[1]	91114	1			T26	5		T27	1		T1	1536
bins_for_gpio_bits[16]	auto[1]	auto[0]	91400	1			T26	5		T27	1		T1	1544
bins_for_gpio_bits[16]	auto[1]	auto[1]	2659401	1			T25	19158		T26	180		T27	29
bins_for_gpio_bits[17]	auto[0]	auto[0]	3129044	1			T25	20275		T26	47		T27	2
bins_for_gpio_bits[17]	auto[0]	auto[1]	90816	1			T26	1		T1	1535		T11	1
bins_for_gpio_bits[17]	auto[1]	auto[0]	91069	1			T26	1		T1	1540		T11	1
bins_for_gpio_bits[17]	auto[1]	auto[1]	2660379	1			T25	19601		T26	192		T27	36
bins_for_gpio_bits[18]	auto[0]	auto[0]	3125833	1			T25	19224		T26	43		T27	5
bins_for_gpio_bits[18]	auto[0]	auto[1]	90857	1			T26	1		T1	1479		T11	1
bins_for_gpio_bits[18]	auto[1]	auto[0]	91116	1			T26	1		T1	1485		T11	1
bins_for_gpio_bits[18]	auto[1]	auto[1]	2663502	1			T25	20652		T26	196		T27	33
bins_for_gpio_bits[19]	auto[0]	auto[0]	3139191	1			T25	20549		T26	34		T27	5
bins_for_gpio_bits[19]	auto[0]	auto[1]	91272	1			T26	1		T27	1		T1	1483
bins_for_gpio_bits[19]	auto[1]	auto[0]	91535	1			T26	1		T27	1		T1	1486
bins_for_gpio_bits[19]	auto[1]	auto[1]	2649310	1			T25	19327		T26	205		T27	31
bins_for_gpio_bits[20]	auto[0]	auto[0]	3134050	1			T25	20393		T26	47		T27	9
bins_for_gpio_bits[20]	auto[0]	auto[1]	90742	1			T26	3		T27	2		T1	1505
bins_for_gpio_bits[20]	auto[1]	auto[0]	90996	1			T26	3		T27	2		T1	1509
bins_for_gpio_bits[20]	auto[1]	auto[1]	2655520	1			T25	19483		T26	188		T27	25
bins_for_gpio_bits[21]	auto[0]	auto[0]	3129213	1			T25	19230		T26	39		T27	8
bins_for_gpio_bits[21]	auto[0]	auto[1]	90659	1			T26	2		T27	1		T1	1495
bins_for_gpio_bits[21]	auto[1]	auto[0]	90936	1			T26	2		T1	1503		T11	3
bins_for_gpio_bits[21]	auto[1]	auto[1]	2660500	1			T25	20646		T26	198		T27	29
bins_for_gpio_bits[22]	auto[0]	auto[0]	3131909	1			T25	20037		T26	49		T27	6
bins_for_gpio_bits[22]	auto[0]	auto[1]	91296	1			T26	3		T1	1470		T11	2
bins_for_gpio_bits[22]	auto[1]	auto[0]	91585	1			T26	3		T1	1475		T11	2
bins_for_gpio_bits[22]	auto[1]	auto[1]	2656518	1			T25	19839		T26	186		T27	32
bins_for_gpio_bits[23]	auto[0]	auto[0]	3136606	1			T25	21131		T26	47		T27	9
bins_for_gpio_bits[23]	auto[0]	auto[1]	90807	1			T26	6		T27	1		T1	1500
bins_for_gpio_bits[23]	auto[1]	auto[0]	91111	1			T26	6		T1	1505		T11	4
bins_for_gpio_bits[23]	auto[1]	auto[1]	2652784	1			T25	18745		T26	182		T27	28
bins_for_gpio_bits[24]	auto[0]	auto[0]	3130543	1			T25	19475		T26	47		T27	7
bins_for_gpio_bits[24]	auto[0]	auto[1]	90731	1			T26	1		T27	1		T1	1522
bins_for_gpio_bits[24]	auto[1]	auto[0]	90972	1			T26	1		T1	1530		T11	1
bins_for_gpio_bits[24]	auto[1]	auto[1]	2659062	1			T25	20401		T26	192		T27	30
bins_for_gpio_bits[25]	auto[0]	auto[0]	3132533	1			T25	20583		T26	55		T27	4
bins_for_gpio_bits[25]	auto[0]	auto[1]	90755	1			T26	5		T1	1554		T11	2
bins_for_gpio_bits[25]	auto[1]	auto[0]	91023	1			T26	5		T1	1561		T11	2
bins_for_gpio_bits[25]	auto[1]	auto[1]	2656997	1			T25	19293		T26	176		T27	34
bins_for_gpio_bits[26]	auto[0]	auto[0]	3130693	1			T25	18866		T26	30		T27	5
bins_for_gpio_bits[26]	auto[0]	auto[1]	90720	1			T26	2		T27	1		T1	1486
bins_for_gpio_bits[26]	auto[1]	auto[0]	91000	1			T26	2		T27	1		T1	1495
bins_for_gpio_bits[26]	auto[1]	auto[1]	2658895	1			T25	21010		T26	207		T27	31
bins_for_gpio_bits[27]	auto[0]	auto[0]	3128153	1			T25	19942		T26	55		T27	4
bins_for_gpio_bits[27]	auto[0]	auto[1]	91299	1			T26	6		T1	1571		T11	3
bins_for_gpio_bits[27]	auto[1]	auto[0]	91531	1			T26	6		T1	1575		T11	3
bins_for_gpio_bits[27]	auto[1]	auto[1]	2660325	1			T25	19934		T26	174		T27	34
bins_for_gpio_bits[28]	auto[0]	auto[0]	3140492	1			T25	18473		T26	37		T27	3
bins_for_gpio_bits[28]	auto[0]	auto[1]	90759	1			T26	4		T1	1521		T11	2
bins_for_gpio_bits[28]	auto[1]	auto[0]	91011	1			T26	4		T1	1528		T11	2
bins_for_gpio_bits[28]	auto[1]	auto[1]	2649046	1			T25	21403		T26	196		T27	35
bins_for_gpio_bits[29]	auto[0]	auto[0]	3135325	1			T25	20745		T26	41		T27	4
bins_for_gpio_bits[29]	auto[0]	auto[1]	91076	1			T26	1		T1	1474		T11	3
bins_for_gpio_bits[29]	auto[1]	auto[0]	91319	1			T26	1		T1	1484		T11	3
bins_for_gpio_bits[29]	auto[1]	auto[1]	2653588	1			T25	19131		T26	198		T27	34
bins_for_gpio_bits[30]	auto[0]	auto[0]	3136379	1			T25	21016		T26	43		T27	6
bins_for_gpio_bits[30]	auto[0]	auto[1]	91140	1			T26	1		T1	1597		T11	1
bins_for_gpio_bits[30]	auto[1]	auto[0]	91406	1			T26	1		T1	1604		T11	1
bins_for_gpio_bits[30]	auto[1]	auto[1]	2652383	1			T25	18860		T26	196		T27	32
bins_for_gpio_bits[31]	auto[0]	auto[0]	3137276	1			T25	20591		T26	43		T27	9
bins_for_gpio_bits[31]	auto[0]	auto[1]	91280	1			T27	1		T28	1		T1	1547
bins_for_gpio_bits[31]	auto[1]	auto[0]	91591	1			T28	1		T1	1554		T11	3
bins_for_gpio_bits[31]	auto[1]	auto[1]	2651161	1			T25	19285		T26	198		T27	28