Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4030732 |
1 |
|
|
T25 |
39876 |
|
T26 |
131 |
|
T27 |
21 |
| auto[1] |
1946404 |
1 |
|
|
T28 |
37 |
|
T1 |
29515 |
|
T13 |
39 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5735391 |
1 |
|
|
T25 |
39876 |
|
T26 |
131 |
|
T27 |
21 |
| auto[1] |
241745 |
1 |
|
|
T28 |
1 |
|
T1 |
2941 |
|
T13 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4031372 |
1 |
|
|
T25 |
39876 |
|
T26 |
131 |
|
T27 |
21 |
| auto[1] |
1945764 |
1 |
|
|
T28 |
23 |
|
T1 |
28620 |
|
T13 |
59 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
853495 |
1 |
|
|
T28 |
3 |
|
T1 |
13359 |
|
T13 |
38 |
| auto[1] |
auto[0] |
auto[1] |
121161 |
1 |
|
|
T1 |
1476 |
|
T13 |
5 |
|
T18 |
89 |
| auto[1] |
auto[1] |
auto[0] |
850524 |
1 |
|
|
T28 |
19 |
|
T1 |
12320 |
|
T13 |
16 |
| auto[1] |
auto[1] |
auto[1] |
120584 |
1 |
|
|
T28 |
1 |
|
T1 |
1465 |
|
T18 |
81 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |