Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4030765 |
1 |
|
|
T25 |
39876 |
|
T26 |
131 |
|
T27 |
21 |
| auto[1] |
1946371 |
1 |
|
|
T28 |
14 |
|
T1 |
30229 |
|
T13 |
26 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5736025 |
1 |
|
|
T25 |
39876 |
|
T26 |
131 |
|
T27 |
21 |
| auto[1] |
241111 |
1 |
|
|
T28 |
1 |
|
T1 |
3140 |
|
T13 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4035361 |
1 |
|
|
T25 |
39876 |
|
T26 |
131 |
|
T27 |
21 |
| auto[1] |
1941775 |
1 |
|
|
T28 |
20 |
|
T1 |
30114 |
|
T13 |
78 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
845117 |
1 |
|
|
T28 |
19 |
|
T1 |
13355 |
|
T13 |
56 |
| auto[1] |
auto[0] |
auto[1] |
119641 |
1 |
|
|
T28 |
1 |
|
T1 |
1577 |
|
T13 |
4 |
| auto[1] |
auto[1] |
auto[0] |
855547 |
1 |
|
|
T1 |
13619 |
|
T13 |
17 |
|
T18 |
378 |
| auto[1] |
auto[1] |
auto[1] |
121470 |
1 |
|
|
T1 |
1563 |
|
T13 |
1 |
|
T18 |
88 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |