Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
852951 |
1 |
|
|
T28 |
7 |
|
T1 |
14085 |
|
T13 |
29 |
| auto[1] |
auto[0] |
auto[1] |
120326 |
1 |
|
|
T28 |
1 |
|
T1 |
1651 |
|
T13 |
2 |
| auto[1] |
auto[1] |
auto[0] |
860851 |
1 |
|
|
T1 |
13354 |
|
T13 |
23 |
|
T18 |
382 |
| auto[1] |
auto[1] |
auto[1] |
122692 |
1 |
|
|
T1 |
1645 |
|
T13 |
2 |
|
T18 |
89 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |