Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4058779 |
1 |
|
|
T25 |
39876 |
|
T26 |
131 |
|
T27 |
21 |
| auto[1] |
1918357 |
1 |
|
|
T28 |
24 |
|
T1 |
30020 |
|
T13 |
86 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5096155 |
1 |
|
|
T25 |
39876 |
|
T26 |
131 |
|
T27 |
21 |
| auto[1] |
880981 |
1 |
|
|
T28 |
8 |
|
T1 |
11160 |
|
T13 |
34 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4060602 |
1 |
|
|
T25 |
39876 |
|
T26 |
131 |
|
T27 |
21 |
| auto[1] |
1916534 |
1 |
|
|
T28 |
26 |
|
T1 |
30796 |
|
T13 |
65 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
529591 |
1 |
|
|
T28 |
15 |
|
T1 |
9817 |
|
T13 |
17 |
| auto[1] |
auto[0] |
auto[1] |
447859 |
1 |
|
|
T28 |
8 |
|
T1 |
5754 |
|
T13 |
21 |
| auto[1] |
auto[1] |
auto[0] |
505962 |
1 |
|
|
T28 |
3 |
|
T1 |
9819 |
|
T13 |
14 |
| auto[1] |
auto[1] |
auto[1] |
433122 |
1 |
|
|
T1 |
5406 |
|
T13 |
13 |
|
T18 |
193 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |