Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4046167 |
1 |
|
|
T25 |
39876 |
|
T26 |
131 |
|
T27 |
21 |
| auto[1] |
1930969 |
1 |
|
|
T28 |
20 |
|
T1 |
29935 |
|
T13 |
78 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5088163 |
1 |
|
|
T25 |
39876 |
|
T26 |
131 |
|
T27 |
21 |
| auto[1] |
888973 |
1 |
|
|
T28 |
7 |
|
T1 |
10812 |
|
T13 |
24 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4043050 |
1 |
|
|
T25 |
39876 |
|
T26 |
131 |
|
T27 |
21 |
| auto[1] |
1934086 |
1 |
|
|
T28 |
18 |
|
T1 |
31055 |
|
T13 |
83 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
521839 |
1 |
|
|
T28 |
6 |
|
T1 |
10205 |
|
T13 |
26 |
| auto[1] |
auto[0] |
auto[1] |
447102 |
1 |
|
|
T28 |
3 |
|
T1 |
5689 |
|
T13 |
9 |
| auto[1] |
auto[1] |
auto[0] |
523274 |
1 |
|
|
T28 |
5 |
|
T1 |
10038 |
|
T13 |
33 |
| auto[1] |
auto[1] |
auto[1] |
441871 |
1 |
|
|
T28 |
4 |
|
T1 |
5123 |
|
T13 |
15 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |