Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4042600 |
1 |
|
|
T25 |
39876 |
|
T26 |
131 |
|
T27 |
21 |
| auto[1] |
1934536 |
1 |
|
|
T28 |
43 |
|
T1 |
30554 |
|
T13 |
40 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5734458 |
1 |
|
|
T25 |
39876 |
|
T26 |
131 |
|
T27 |
21 |
| auto[1] |
242678 |
1 |
|
|
T28 |
1 |
|
T1 |
3334 |
|
T13 |
8 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4029394 |
1 |
|
|
T25 |
39876 |
|
T26 |
131 |
|
T27 |
21 |
| auto[1] |
1947742 |
1 |
|
|
T28 |
35 |
|
T1 |
30462 |
|
T13 |
99 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
856129 |
1 |
|
|
T28 |
11 |
|
T1 |
14413 |
|
T13 |
71 |
| auto[1] |
auto[0] |
auto[1] |
121949 |
1 |
|
|
T1 |
1875 |
|
T13 |
8 |
|
T18 |
95 |
| auto[1] |
auto[1] |
auto[0] |
848935 |
1 |
|
|
T28 |
23 |
|
T1 |
12715 |
|
T13 |
20 |
| auto[1] |
auto[1] |
auto[1] |
120729 |
1 |
|
|
T28 |
1 |
|
T1 |
1459 |
|
T18 |
43 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |