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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 941
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T767 /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.1792486715 Aug 18 05:31:07 PM PDT 24 Aug 18 05:31:07 PM PDT 24 22559802 ps
T768 /workspace/coverage/cover_reg_top/19.gpio_tl_errors.2351060754 Aug 18 05:31:18 PM PDT 24 Aug 18 05:31:20 PM PDT 24 34121232 ps
T94 /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.4072036058 Aug 18 05:31:05 PM PDT 24 Aug 18 05:31:08 PM PDT 24 180445995 ps
T769 /workspace/coverage/cover_reg_top/17.gpio_intr_test.1372097190 Aug 18 05:31:03 PM PDT 24 Aug 18 05:31:04 PM PDT 24 64941149 ps
T770 /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.2211710406 Aug 18 05:31:05 PM PDT 24 Aug 18 05:31:06 PM PDT 24 15466494 ps
T87 /workspace/coverage/cover_reg_top/19.gpio_csr_rw.2687465796 Aug 18 05:31:17 PM PDT 24 Aug 18 05:31:18 PM PDT 24 16849502 ps
T771 /workspace/coverage/cover_reg_top/32.gpio_intr_test.1042759862 Aug 18 05:31:16 PM PDT 24 Aug 18 05:31:17 PM PDT 24 10722316 ps
T88 /workspace/coverage/cover_reg_top/11.gpio_csr_rw.798532311 Aug 18 05:30:59 PM PDT 24 Aug 18 05:31:00 PM PDT 24 36711823 ps
T772 /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.3469989304 Aug 18 05:31:11 PM PDT 24 Aug 18 05:31:11 PM PDT 24 12887269 ps
T773 /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.2703726232 Aug 18 05:31:04 PM PDT 24 Aug 18 05:31:05 PM PDT 24 232689549 ps
T45 /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.1865588241 Aug 18 05:31:05 PM PDT 24 Aug 18 05:31:06 PM PDT 24 348752270 ps
T774 /workspace/coverage/cover_reg_top/8.gpio_intr_test.3075950442 Aug 18 05:31:11 PM PDT 24 Aug 18 05:31:12 PM PDT 24 40838166 ps
T775 /workspace/coverage/cover_reg_top/8.gpio_csr_rw.3475291478 Aug 18 05:31:03 PM PDT 24 Aug 18 05:31:04 PM PDT 24 10674780 ps
T776 /workspace/coverage/cover_reg_top/37.gpio_intr_test.4022507825 Aug 18 05:31:19 PM PDT 24 Aug 18 05:31:20 PM PDT 24 19966531 ps
T777 /workspace/coverage/cover_reg_top/36.gpio_intr_test.3720966408 Aug 18 05:31:15 PM PDT 24 Aug 18 05:31:16 PM PDT 24 54964902 ps
T89 /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.678905309 Aug 18 05:31:01 PM PDT 24 Aug 18 05:31:02 PM PDT 24 64879201 ps
T778 /workspace/coverage/cover_reg_top/6.gpio_intr_test.2757875380 Aug 18 05:31:01 PM PDT 24 Aug 18 05:31:02 PM PDT 24 18526473 ps
T779 /workspace/coverage/cover_reg_top/10.gpio_intr_test.1011298713 Aug 18 05:31:05 PM PDT 24 Aug 18 05:31:06 PM PDT 24 14287786 ps
T780 /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.2639178407 Aug 18 05:31:02 PM PDT 24 Aug 18 05:31:04 PM PDT 24 128127585 ps
T781 /workspace/coverage/cover_reg_top/0.gpio_intr_test.1288156919 Aug 18 05:31:28 PM PDT 24 Aug 18 05:31:28 PM PDT 24 38445237 ps
T782 /workspace/coverage/cover_reg_top/33.gpio_intr_test.1777712031 Aug 18 05:31:16 PM PDT 24 Aug 18 05:31:17 PM PDT 24 51697110 ps
T783 /workspace/coverage/cover_reg_top/12.gpio_intr_test.3871954719 Aug 18 05:31:18 PM PDT 24 Aug 18 05:31:19 PM PDT 24 32930488 ps
T784 /workspace/coverage/cover_reg_top/2.gpio_tl_errors.827396919 Aug 18 05:31:04 PM PDT 24 Aug 18 05:31:06 PM PDT 24 37202730 ps
T785 /workspace/coverage/cover_reg_top/35.gpio_intr_test.3619301744 Aug 18 05:31:10 PM PDT 24 Aug 18 05:31:10 PM PDT 24 22612560 ps
T786 /workspace/coverage/cover_reg_top/14.gpio_intr_test.677025976 Aug 18 05:31:15 PM PDT 24 Aug 18 05:31:16 PM PDT 24 14824967 ps
T46 /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.3483409208 Aug 18 05:31:05 PM PDT 24 Aug 18 05:31:06 PM PDT 24 133818012 ps
T787 /workspace/coverage/cover_reg_top/12.gpio_csr_rw.2937641663 Aug 18 05:31:21 PM PDT 24 Aug 18 05:31:22 PM PDT 24 27387677 ps
T788 /workspace/coverage/cover_reg_top/45.gpio_intr_test.724924781 Aug 18 05:31:33 PM PDT 24 Aug 18 05:31:34 PM PDT 24 17127976 ps
T50 /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.1590776219 Aug 18 05:31:05 PM PDT 24 Aug 18 05:31:06 PM PDT 24 735368127 ps
T789 /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.209065281 Aug 18 05:31:15 PM PDT 24 Aug 18 05:31:16 PM PDT 24 58957962 ps
T790 /workspace/coverage/cover_reg_top/14.gpio_csr_rw.1657674862 Aug 18 05:31:00 PM PDT 24 Aug 18 05:31:00 PM PDT 24 18069275 ps
T49 /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.2974603239 Aug 18 05:31:13 PM PDT 24 Aug 18 05:31:14 PM PDT 24 72228063 ps
T791 /workspace/coverage/cover_reg_top/10.gpio_tl_errors.2444911825 Aug 18 05:31:03 PM PDT 24 Aug 18 05:31:06 PM PDT 24 119485313 ps
T90 /workspace/coverage/cover_reg_top/10.gpio_csr_rw.720306014 Aug 18 05:31:11 PM PDT 24 Aug 18 05:31:11 PM PDT 24 11688146 ps
T792 /workspace/coverage/cover_reg_top/23.gpio_intr_test.1715833340 Aug 18 05:31:25 PM PDT 24 Aug 18 05:31:31 PM PDT 24 15299407 ps
T793 /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.4189570008 Aug 18 05:31:00 PM PDT 24 Aug 18 05:31:00 PM PDT 24 29197403 ps
T794 /workspace/coverage/cover_reg_top/16.gpio_intr_test.3245734137 Aug 18 05:31:21 PM PDT 24 Aug 18 05:31:27 PM PDT 24 12108928 ps
T795 /workspace/coverage/cover_reg_top/7.gpio_tl_errors.1185341383 Aug 18 05:31:12 PM PDT 24 Aug 18 05:31:14 PM PDT 24 133034658 ps
T796 /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.3983203937 Aug 18 05:31:35 PM PDT 24 Aug 18 05:31:36 PM PDT 24 34427627 ps
T797 /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.1917413019 Aug 18 05:31:05 PM PDT 24 Aug 18 05:31:06 PM PDT 24 28106821 ps
T91 /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.1845103272 Aug 18 05:31:10 PM PDT 24 Aug 18 05:31:11 PM PDT 24 19646877 ps
T798 /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.3706481133 Aug 18 05:31:20 PM PDT 24 Aug 18 05:31:21 PM PDT 24 116003410 ps
T92 /workspace/coverage/cover_reg_top/4.gpio_csr_rw.954279098 Aug 18 05:31:03 PM PDT 24 Aug 18 05:31:04 PM PDT 24 41897519 ps
T799 /workspace/coverage/cover_reg_top/20.gpio_intr_test.3030658481 Aug 18 05:31:40 PM PDT 24 Aug 18 05:31:41 PM PDT 24 43551281 ps
T800 /workspace/coverage/cover_reg_top/3.gpio_tl_errors.1691915413 Aug 18 05:31:05 PM PDT 24 Aug 18 05:31:07 PM PDT 24 166729774 ps
T801 /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.3122477228 Aug 18 05:31:03 PM PDT 24 Aug 18 05:31:04 PM PDT 24 96008052 ps
T802 /workspace/coverage/cover_reg_top/5.gpio_intr_test.771148044 Aug 18 05:31:02 PM PDT 24 Aug 18 05:31:03 PM PDT 24 47342715 ps
T803 /workspace/coverage/cover_reg_top/28.gpio_intr_test.1667933184 Aug 18 05:31:16 PM PDT 24 Aug 18 05:31:17 PM PDT 24 37004931 ps
T804 /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.1629011514 Aug 18 05:31:08 PM PDT 24 Aug 18 05:31:09 PM PDT 24 311757681 ps
T805 /workspace/coverage/cover_reg_top/21.gpio_intr_test.268757310 Aug 18 05:31:05 PM PDT 24 Aug 18 05:31:06 PM PDT 24 97510241 ps
T806 /workspace/coverage/cover_reg_top/1.gpio_csr_rw.1744768360 Aug 18 05:31:01 PM PDT 24 Aug 18 05:31:02 PM PDT 24 13528888 ps
T807 /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.933884801 Aug 18 05:31:03 PM PDT 24 Aug 18 05:31:05 PM PDT 24 67565147 ps
T808 /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.1993582032 Aug 18 05:31:14 PM PDT 24 Aug 18 05:31:15 PM PDT 24 100831336 ps
T809 /workspace/coverage/cover_reg_top/9.gpio_intr_test.708006780 Aug 18 05:31:02 PM PDT 24 Aug 18 05:31:02 PM PDT 24 50721790 ps
T810 /workspace/coverage/cover_reg_top/29.gpio_intr_test.1207844845 Aug 18 05:31:24 PM PDT 24 Aug 18 05:31:29 PM PDT 24 19490717 ps
T811 /workspace/coverage/cover_reg_top/8.gpio_tl_errors.1394961303 Aug 18 05:31:04 PM PDT 24 Aug 18 05:31:06 PM PDT 24 149968602 ps
T93 /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.27415404 Aug 18 05:31:17 PM PDT 24 Aug 18 05:31:18 PM PDT 24 37162170 ps
T812 /workspace/coverage/cover_reg_top/17.gpio_tl_errors.67067981 Aug 18 05:31:14 PM PDT 24 Aug 18 05:31:17 PM PDT 24 215846691 ps
T813 /workspace/coverage/cover_reg_top/4.gpio_intr_test.651875420 Aug 18 05:30:58 PM PDT 24 Aug 18 05:30:59 PM PDT 24 27853851 ps
T814 /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.1173411015 Aug 18 05:31:02 PM PDT 24 Aug 18 05:31:03 PM PDT 24 19371709 ps
T815 /workspace/coverage/cover_reg_top/3.gpio_intr_test.3264430846 Aug 18 05:31:00 PM PDT 24 Aug 18 05:31:01 PM PDT 24 13562306 ps
T816 /workspace/coverage/cover_reg_top/41.gpio_intr_test.1751300036 Aug 18 05:31:27 PM PDT 24 Aug 18 05:31:27 PM PDT 24 14797670 ps
T817 /workspace/coverage/cover_reg_top/44.gpio_intr_test.3341034519 Aug 18 05:31:21 PM PDT 24 Aug 18 05:31:26 PM PDT 24 12546011 ps
T818 /workspace/coverage/cover_reg_top/2.gpio_csr_rw.2633433427 Aug 18 05:30:59 PM PDT 24 Aug 18 05:31:00 PM PDT 24 12410128 ps
T819 /workspace/coverage/cover_reg_top/4.gpio_tl_errors.3699175419 Aug 18 05:31:03 PM PDT 24 Aug 18 05:31:06 PM PDT 24 232621374 ps
T820 /workspace/coverage/cover_reg_top/18.gpio_tl_errors.3587173964 Aug 18 05:31:36 PM PDT 24 Aug 18 05:31:39 PM PDT 24 207073883 ps
T821 /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.2455106948 Aug 18 05:31:18 PM PDT 24 Aug 18 05:31:19 PM PDT 24 25479447 ps
T822 /workspace/coverage/cover_reg_top/13.gpio_csr_rw.774326430 Aug 18 05:31:01 PM PDT 24 Aug 18 05:31:02 PM PDT 24 55172536 ps
T823 /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.3772683188 Aug 18 05:30:59 PM PDT 24 Aug 18 05:31:00 PM PDT 24 158560844 ps
T824 /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.767858921 Aug 18 05:31:04 PM PDT 24 Aug 18 05:31:05 PM PDT 24 20205688 ps
T825 /workspace/coverage/cover_reg_top/9.gpio_csr_rw.1244126356 Aug 18 05:31:23 PM PDT 24 Aug 18 05:31:24 PM PDT 24 24609247 ps
T826 /workspace/coverage/cover_reg_top/5.gpio_csr_rw.905043860 Aug 18 05:31:03 PM PDT 24 Aug 18 05:31:03 PM PDT 24 14447625 ps
T97 /workspace/coverage/cover_reg_top/7.gpio_csr_rw.2047857864 Aug 18 05:31:03 PM PDT 24 Aug 18 05:31:04 PM PDT 24 22405723 ps
T827 /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.3201019675 Aug 18 05:31:01 PM PDT 24 Aug 18 05:31:02 PM PDT 24 131872528 ps
T95 /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.3500010761 Aug 18 05:31:01 PM PDT 24 Aug 18 05:31:02 PM PDT 24 53972611 ps
T105 /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.4005523563 Aug 18 05:31:00 PM PDT 24 Aug 18 05:31:01 PM PDT 24 161928302 ps
T828 /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.1146888229 Aug 18 05:31:08 PM PDT 24 Aug 18 05:31:09 PM PDT 24 501454015 ps
T829 /workspace/coverage/cover_reg_top/15.gpio_intr_test.2703775389 Aug 18 05:31:30 PM PDT 24 Aug 18 05:31:30 PM PDT 24 84100242 ps
T96 /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.346028825 Aug 18 05:31:04 PM PDT 24 Aug 18 05:31:05 PM PDT 24 278934244 ps
T830 /workspace/coverage/cover_reg_top/49.gpio_intr_test.2331362658 Aug 18 05:31:23 PM PDT 24 Aug 18 05:31:23 PM PDT 24 41158705 ps
T831 /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.679479520 Aug 18 05:31:04 PM PDT 24 Aug 18 05:31:05 PM PDT 24 22122665 ps
T832 /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.3076210546 Aug 18 05:31:01 PM PDT 24 Aug 18 05:31:03 PM PDT 24 72291403 ps
T833 /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.2466628211 Aug 18 05:31:01 PM PDT 24 Aug 18 05:31:01 PM PDT 24 21474841 ps
T834 /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.4035359760 Aug 18 05:31:06 PM PDT 24 Aug 18 05:31:07 PM PDT 24 49978182 ps
T835 /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.3126710383 Aug 18 05:31:17 PM PDT 24 Aug 18 05:31:19 PM PDT 24 129529359 ps
T836 /workspace/coverage/cover_reg_top/11.gpio_tl_errors.1164603325 Aug 18 05:31:02 PM PDT 24 Aug 18 05:31:04 PM PDT 24 539380269 ps
T837 /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.456336307 Aug 18 05:31:12 PM PDT 24 Aug 18 05:31:12 PM PDT 24 60929662 ps
T838 /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.150027066 Aug 18 05:31:14 PM PDT 24 Aug 18 05:31:15 PM PDT 24 110651091 ps
T839 /workspace/coverage/cover_reg_top/39.gpio_intr_test.1322049115 Aug 18 05:31:11 PM PDT 24 Aug 18 05:31:12 PM PDT 24 51442507 ps
T840 /workspace/coverage/cover_reg_top/0.gpio_csr_rw.942714599 Aug 18 05:31:04 PM PDT 24 Aug 18 05:31:04 PM PDT 24 29137087 ps
T841 /workspace/coverage/cover_reg_top/1.gpio_tl_errors.1436554124 Aug 18 05:31:06 PM PDT 24 Aug 18 05:31:07 PM PDT 24 33796854 ps
T842 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1020246243 Aug 18 05:31:20 PM PDT 24 Aug 18 05:31:21 PM PDT 24 46745167 ps
T843 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1889639605 Aug 18 05:31:24 PM PDT 24 Aug 18 05:31:25 PM PDT 24 183913108 ps
T844 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2191245887 Aug 18 05:31:33 PM PDT 24 Aug 18 05:31:35 PM PDT 24 54480474 ps
T845 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3393670357 Aug 18 05:31:46 PM PDT 24 Aug 18 05:31:47 PM PDT 24 51296116 ps
T846 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3061377478 Aug 18 05:31:40 PM PDT 24 Aug 18 05:31:41 PM PDT 24 82278129 ps
T847 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2863021244 Aug 18 05:31:24 PM PDT 24 Aug 18 05:31:26 PM PDT 24 196568460 ps
T848 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2079605530 Aug 18 05:31:16 PM PDT 24 Aug 18 05:31:17 PM PDT 24 60776593 ps
T849 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.1914054880 Aug 18 05:31:17 PM PDT 24 Aug 18 05:31:19 PM PDT 24 57201583 ps
T850 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.2542231844 Aug 18 05:31:22 PM PDT 24 Aug 18 05:31:23 PM PDT 24 30535605 ps
T851 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.1063027672 Aug 18 05:31:40 PM PDT 24 Aug 18 05:31:41 PM PDT 24 49988155 ps
T852 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.1053533652 Aug 18 05:31:33 PM PDT 24 Aug 18 05:31:34 PM PDT 24 35239238 ps
T853 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1452876324 Aug 18 05:31:41 PM PDT 24 Aug 18 05:31:42 PM PDT 24 88750782 ps
T854 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.570697282 Aug 18 05:31:24 PM PDT 24 Aug 18 05:31:25 PM PDT 24 687368791 ps
T855 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.1083873299 Aug 18 05:31:16 PM PDT 24 Aug 18 05:31:17 PM PDT 24 38206976 ps
T856 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.3472173702 Aug 18 05:31:25 PM PDT 24 Aug 18 05:31:27 PM PDT 24 131112559 ps
T857 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.464402377 Aug 18 05:31:26 PM PDT 24 Aug 18 05:31:28 PM PDT 24 226508527 ps
T858 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.2043432877 Aug 18 05:31:34 PM PDT 24 Aug 18 05:31:35 PM PDT 24 72352815 ps
T859 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.870825723 Aug 18 05:31:41 PM PDT 24 Aug 18 05:31:43 PM PDT 24 315454517 ps
T860 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.990606033 Aug 18 05:31:44 PM PDT 24 Aug 18 05:31:45 PM PDT 24 31489257 ps
T861 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2906377347 Aug 18 05:31:14 PM PDT 24 Aug 18 05:31:15 PM PDT 24 579645924 ps
T862 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.533992475 Aug 18 05:31:29 PM PDT 24 Aug 18 05:31:30 PM PDT 24 221925015 ps
T863 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1064906609 Aug 18 05:31:41 PM PDT 24 Aug 18 05:31:42 PM PDT 24 273978806 ps
T864 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3925725708 Aug 18 05:31:38 PM PDT 24 Aug 18 05:31:40 PM PDT 24 215114025 ps
T865 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.1875269369 Aug 18 05:31:25 PM PDT 24 Aug 18 05:31:26 PM PDT 24 251142550 ps
T866 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4222371705 Aug 18 05:31:21 PM PDT 24 Aug 18 05:31:22 PM PDT 24 263719747 ps
T867 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1814591977 Aug 18 05:31:40 PM PDT 24 Aug 18 05:31:42 PM PDT 24 172186278 ps
T868 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.3272044341 Aug 18 05:31:22 PM PDT 24 Aug 18 05:31:23 PM PDT 24 40339678 ps
T869 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2095409808 Aug 18 05:31:30 PM PDT 24 Aug 18 05:31:31 PM PDT 24 33421374 ps
T870 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1484505926 Aug 18 05:31:21 PM PDT 24 Aug 18 05:31:22 PM PDT 24 73748305 ps
T871 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.3945266871 Aug 18 05:31:43 PM PDT 24 Aug 18 05:31:45 PM PDT 24 73835420 ps
T872 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.104964367 Aug 18 05:31:17 PM PDT 24 Aug 18 05:31:23 PM PDT 24 243858773 ps
T873 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.3638957917 Aug 18 05:31:28 PM PDT 24 Aug 18 05:31:29 PM PDT 24 62478835 ps
T874 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.3850186281 Aug 18 05:31:20 PM PDT 24 Aug 18 05:31:21 PM PDT 24 179985570 ps
T875 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.1643326503 Aug 18 05:31:24 PM PDT 24 Aug 18 05:31:31 PM PDT 24 276094346 ps
T876 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.911398096 Aug 18 05:31:34 PM PDT 24 Aug 18 05:31:35 PM PDT 24 72871928 ps
T877 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2029363675 Aug 18 05:31:27 PM PDT 24 Aug 18 05:31:29 PM PDT 24 85662477 ps
T878 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.23101887 Aug 18 05:31:32 PM PDT 24 Aug 18 05:31:34 PM PDT 24 180149793 ps
T879 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.627377959 Aug 18 05:31:40 PM PDT 24 Aug 18 05:31:41 PM PDT 24 67165304 ps
T880 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.2467451143 Aug 18 05:31:34 PM PDT 24 Aug 18 05:31:35 PM PDT 24 34518146 ps
T881 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.3980998521 Aug 18 05:31:34 PM PDT 24 Aug 18 05:31:36 PM PDT 24 58011438 ps
T882 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2464992611 Aug 18 05:31:20 PM PDT 24 Aug 18 05:31:21 PM PDT 24 45444325 ps
T883 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.1388119202 Aug 18 05:31:20 PM PDT 24 Aug 18 05:31:21 PM PDT 24 298299084 ps
T884 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3420924981 Aug 18 05:31:23 PM PDT 24 Aug 18 05:31:24 PM PDT 24 98700274 ps
T885 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.2116093770 Aug 18 05:31:31 PM PDT 24 Aug 18 05:31:32 PM PDT 24 730890523 ps
T886 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.4257032645 Aug 18 05:31:23 PM PDT 24 Aug 18 05:31:24 PM PDT 24 69306095 ps
T887 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3460685213 Aug 18 05:31:20 PM PDT 24 Aug 18 05:31:20 PM PDT 24 54590191 ps
T888 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.2371354988 Aug 18 05:31:27 PM PDT 24 Aug 18 05:31:29 PM PDT 24 105824475 ps
T889 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.613253036 Aug 18 05:31:28 PM PDT 24 Aug 18 05:31:29 PM PDT 24 91877031 ps
T890 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.3938918211 Aug 18 05:31:22 PM PDT 24 Aug 18 05:31:23 PM PDT 24 272640415 ps
T891 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2405973069 Aug 18 05:31:38 PM PDT 24 Aug 18 05:31:39 PM PDT 24 202526379 ps
T892 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.3400299590 Aug 18 05:31:48 PM PDT 24 Aug 18 05:31:49 PM PDT 24 133644368 ps
T893 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2599508986 Aug 18 05:31:25 PM PDT 24 Aug 18 05:31:27 PM PDT 24 152456028 ps
T894 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.802775750 Aug 18 05:31:19 PM PDT 24 Aug 18 05:31:20 PM PDT 24 39445910 ps
T895 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.2620451945 Aug 18 05:31:19 PM PDT 24 Aug 18 05:31:21 PM PDT 24 98452179 ps
T896 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.3690904529 Aug 18 05:31:46 PM PDT 24 Aug 18 05:31:47 PM PDT 24 184972069 ps
T897 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.881990929 Aug 18 05:31:37 PM PDT 24 Aug 18 05:31:38 PM PDT 24 122405180 ps
T898 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.637005772 Aug 18 05:31:18 PM PDT 24 Aug 18 05:31:19 PM PDT 24 81952399 ps
T899 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.3480801649 Aug 18 05:31:50 PM PDT 24 Aug 18 05:31:52 PM PDT 24 95186561 ps
T900 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.3854803418 Aug 18 05:31:04 PM PDT 24 Aug 18 05:31:05 PM PDT 24 207043206 ps
T901 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1925254776 Aug 18 05:31:24 PM PDT 24 Aug 18 05:31:25 PM PDT 24 42312791 ps
T902 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3557992165 Aug 18 05:31:20 PM PDT 24 Aug 18 05:31:21 PM PDT 24 32319207 ps
T903 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.4249219206 Aug 18 05:31:29 PM PDT 24 Aug 18 05:31:30 PM PDT 24 83299532 ps
T904 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.2215896147 Aug 18 05:31:27 PM PDT 24 Aug 18 05:31:28 PM PDT 24 304744605 ps
T905 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.3836398965 Aug 18 05:31:18 PM PDT 24 Aug 18 05:31:19 PM PDT 24 324718054 ps
T906 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4053311216 Aug 18 05:31:40 PM PDT 24 Aug 18 05:31:41 PM PDT 24 176852833 ps
T907 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.395761731 Aug 18 05:31:29 PM PDT 24 Aug 18 05:31:30 PM PDT 24 490088713 ps
T908 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4209886962 Aug 18 05:31:25 PM PDT 24 Aug 18 05:31:27 PM PDT 24 267984843 ps
T909 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3719686577 Aug 18 05:31:11 PM PDT 24 Aug 18 05:31:12 PM PDT 24 40683042 ps
T910 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.71813809 Aug 18 05:31:25 PM PDT 24 Aug 18 05:31:26 PM PDT 24 73114862 ps
T911 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.3094220552 Aug 18 05:31:24 PM PDT 24 Aug 18 05:31:26 PM PDT 24 794665354 ps
T912 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.2603899494 Aug 18 05:31:39 PM PDT 24 Aug 18 05:31:40 PM PDT 24 54683565 ps
T913 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2973851834 Aug 18 05:31:23 PM PDT 24 Aug 18 05:31:24 PM PDT 24 30815896 ps
T914 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.963518685 Aug 18 05:31:41 PM PDT 24 Aug 18 05:31:42 PM PDT 24 363986231 ps
T915 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1521835958 Aug 18 05:31:50 PM PDT 24 Aug 18 05:31:51 PM PDT 24 89793501 ps
T916 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.2380884901 Aug 18 05:31:23 PM PDT 24 Aug 18 05:31:24 PM PDT 24 114327500 ps
T917 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.3205855816 Aug 18 05:31:17 PM PDT 24 Aug 18 05:31:18 PM PDT 24 162468328 ps
T918 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.3423434498 Aug 18 05:31:26 PM PDT 24 Aug 18 05:31:27 PM PDT 24 55877804 ps
T919 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.2641616505 Aug 18 05:31:54 PM PDT 24 Aug 18 05:31:55 PM PDT 24 106340588 ps
T920 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.678517198 Aug 18 05:31:32 PM PDT 24 Aug 18 05:31:33 PM PDT 24 165213641 ps
T921 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.418574843 Aug 18 05:31:19 PM PDT 24 Aug 18 05:31:21 PM PDT 24 322226906 ps
T922 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.1054797959 Aug 18 05:31:40 PM PDT 24 Aug 18 05:31:41 PM PDT 24 80430791 ps
T923 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.862335561 Aug 18 05:31:41 PM PDT 24 Aug 18 05:31:43 PM PDT 24 131289803 ps
T924 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2919935994 Aug 18 05:31:27 PM PDT 24 Aug 18 05:31:29 PM PDT 24 160230483 ps
T925 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2443590209 Aug 18 05:31:37 PM PDT 24 Aug 18 05:31:38 PM PDT 24 285186707 ps
T926 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4071699040 Aug 18 05:31:45 PM PDT 24 Aug 18 05:31:46 PM PDT 24 83889812 ps
T927 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.1628470548 Aug 18 05:31:34 PM PDT 24 Aug 18 05:31:35 PM PDT 24 66643637 ps
T928 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.718346887 Aug 18 05:31:40 PM PDT 24 Aug 18 05:31:41 PM PDT 24 29663583 ps
T929 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1928365735 Aug 18 05:31:20 PM PDT 24 Aug 18 05:31:22 PM PDT 24 91290257 ps
T930 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.1546636503 Aug 18 05:31:21 PM PDT 24 Aug 18 05:31:22 PM PDT 24 160618663 ps
T931 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3351993878 Aug 18 05:31:40 PM PDT 24 Aug 18 05:31:42 PM PDT 24 68296148 ps
T932 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1135409577 Aug 18 05:31:24 PM PDT 24 Aug 18 05:31:26 PM PDT 24 97291334 ps
T933 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.3476398188 Aug 18 05:31:34 PM PDT 24 Aug 18 05:31:35 PM PDT 24 143114101 ps
T934 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.2462183354 Aug 18 05:31:29 PM PDT 24 Aug 18 05:31:29 PM PDT 24 417118787 ps
T935 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.4177680859 Aug 18 05:31:23 PM PDT 24 Aug 18 05:31:24 PM PDT 24 236494012 ps
T936 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.3410321202 Aug 18 05:31:24 PM PDT 24 Aug 18 05:31:25 PM PDT 24 137233746 ps
T937 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.546688779 Aug 18 05:31:15 PM PDT 24 Aug 18 05:31:17 PM PDT 24 103248857 ps
T938 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.119214961 Aug 18 05:31:29 PM PDT 24 Aug 18 05:31:31 PM PDT 24 1346261879 ps
T939 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3751355597 Aug 18 05:31:19 PM PDT 24 Aug 18 05:31:20 PM PDT 24 354157781 ps
T940 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2948144702 Aug 18 05:31:22 PM PDT 24 Aug 18 05:31:23 PM PDT 24 46595619 ps
T941 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.555412168 Aug 18 05:31:35 PM PDT 24 Aug 18 05:31:37 PM PDT 24 270603640 ps

Test location /workspace/coverage/default/5.gpio_stress_all.3647750105
Short name T1
Test name
Test status
Simulation time 52362862458 ps
CPU time 131.36 seconds
Started Aug 18 05:40:47 PM PDT 24
Finished Aug 18 05:42:58 PM PDT 24
Peak memory 198372 kb
Host smart-1fd8038b-a703-449e-8701-485f74a94592
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647750105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.3647750105
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.2096118773
Short name T106
Test name
Test status
Simulation time 38488013 ps
CPU time 1.6 seconds
Started Aug 18 05:40:52 PM PDT 24
Finished Aug 18 05:40:53 PM PDT 24
Peak memory 198228 kb
Host smart-5f4303a8-c5d6-44ee-a8fc-631e612e1ef4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096118773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.2096118773
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_stress_all_with_rand_reset.3076714591
Short name T30
Test name
Test status
Simulation time 17710321552 ps
CPU time 143.28 seconds
Started Aug 18 05:41:03 PM PDT 24
Finished Aug 18 05:43:31 PM PDT 24
Peak memory 198408 kb
Host smart-0364fd0a-7414-4c25-b703-6f9ae51035cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3076714591 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_stress_all_with_rand_reset.3076714591
Directory /workspace/24.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.3432967414
Short name T25
Test name
Test status
Simulation time 656880093 ps
CPU time 20.08 seconds
Started Aug 18 05:40:55 PM PDT 24
Finished Aug 18 05:41:15 PM PDT 24
Peak memory 198108 kb
Host smart-5f6891d3-f362-4cea-873b-221ff6a2ed22
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432967414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.3432967414
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.1495171757
Short name T42
Test name
Test status
Simulation time 615911419 ps
CPU time 1.48 seconds
Started Aug 18 05:31:02 PM PDT 24
Finished Aug 18 05:31:04 PM PDT 24
Peak memory 198464 kb
Host smart-feccbf87-783f-49a5-baa3-851e87cf5d15
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495171757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.1495171757
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.247602555
Short name T80
Test name
Test status
Simulation time 120637642 ps
CPU time 0.84 seconds
Started Aug 18 05:31:19 PM PDT 24
Finished Aug 18 05:31:20 PM PDT 24
Peak memory 196496 kb
Host smart-f7a76d40-8db7-4118-9a61-707f1ad6bd13
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247602555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
.gpio_csr_aliasing.247602555
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/default/15.gpio_alert_test.481357650
Short name T132
Test name
Test status
Simulation time 26928065 ps
CPU time 0.59 seconds
Started Aug 18 05:40:46 PM PDT 24
Finished Aug 18 05:40:46 PM PDT 24
Peak memory 194036 kb
Host smart-ee48e30f-d7b9-4ed5-87cc-b13e9f214fda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481357650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.481357650
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.764967890
Short name T37
Test name
Test status
Simulation time 110111653 ps
CPU time 0.84 seconds
Started Aug 18 05:40:28 PM PDT 24
Finished Aug 18 05:40:29 PM PDT 24
Peak memory 214872 kb
Host smart-8ccea4f8-dd9a-4660-973c-71f5159babcb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764967890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.764967890
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.678905309
Short name T89
Test name
Test status
Simulation time 64879201 ps
CPU time 0.78 seconds
Started Aug 18 05:31:01 PM PDT 24
Finished Aug 18 05:31:02 PM PDT 24
Peak memory 196176 kb
Host smart-711281f9-92c6-4d7a-9b49-286c2f572496
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678905309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0
.gpio_csr_aliasing.678905309
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.2254729733
Short name T98
Test name
Test status
Simulation time 479545125 ps
CPU time 0.77 seconds
Started Aug 18 05:31:03 PM PDT 24
Finished Aug 18 05:31:04 PM PDT 24
Peak memory 196452 kb
Host smart-8f9abbab-f2a0-4d61-93af-6ed33cf509d4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254729733 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.2254729733
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.2974603239
Short name T49
Test name
Test status
Simulation time 72228063 ps
CPU time 1.15 seconds
Started Aug 18 05:31:13 PM PDT 24
Finished Aug 18 05:31:14 PM PDT 24
Peak memory 198508 kb
Host smart-16b5aba1-ab20-4dad-8da1-240b99c95483
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974603239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.2974603239
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.4005523563
Short name T105
Test name
Test status
Simulation time 161928302 ps
CPU time 0.88 seconds
Started Aug 18 05:31:00 PM PDT 24
Finished Aug 18 05:31:01 PM PDT 24
Peak memory 198292 kb
Host smart-3803c151-7ac0-4f61-85c0-4022a2eb6166
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005523563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.4005523563
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.2639178407
Short name T780
Test name
Test status
Simulation time 128127585 ps
CPU time 1.42 seconds
Started Aug 18 05:31:02 PM PDT 24
Finished Aug 18 05:31:04 PM PDT 24
Peak memory 198420 kb
Host smart-31a51843-6df4-4f72-9638-a3800b751231
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639178407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.2639178407
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.3500010761
Short name T95
Test name
Test status
Simulation time 53972611 ps
CPU time 0.68 seconds
Started Aug 18 05:31:01 PM PDT 24
Finished Aug 18 05:31:02 PM PDT 24
Peak memory 195956 kb
Host smart-dbcdf68e-1555-4391-9706-cce02df60af9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500010761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.3500010761
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.150027066
Short name T838
Test name
Test status
Simulation time 110651091 ps
CPU time 1.45 seconds
Started Aug 18 05:31:14 PM PDT 24
Finished Aug 18 05:31:15 PM PDT 24
Peak memory 198832 kb
Host smart-3f367e9c-f8e4-4c91-b5e4-1f490bba51eb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150027066 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.150027066
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.942714599
Short name T840
Test name
Test status
Simulation time 29137087 ps
CPU time 0.65 seconds
Started Aug 18 05:31:04 PM PDT 24
Finished Aug 18 05:31:04 PM PDT 24
Peak memory 195896 kb
Host smart-7682f8e4-34b2-4271-bccb-025e83650fc1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942714599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_
csr_rw.942714599
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.1288156919
Short name T781
Test name
Test status
Simulation time 38445237 ps
CPU time 0.57 seconds
Started Aug 18 05:31:28 PM PDT 24
Finished Aug 18 05:31:28 PM PDT 24
Peak memory 194204 kb
Host smart-840d3845-9fc8-447b-9f1c-f7f5e4231721
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288156919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.1288156919
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.3772683188
Short name T823
Test name
Test status
Simulation time 158560844 ps
CPU time 0.68 seconds
Started Aug 18 05:30:59 PM PDT 24
Finished Aug 18 05:31:00 PM PDT 24
Peak memory 195124 kb
Host smart-610a1b55-7159-4fe6-becb-454bdef13310
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772683188 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.3772683188
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.3248587716
Short name T763
Test name
Test status
Simulation time 118608400 ps
CPU time 1.15 seconds
Started Aug 18 05:31:01 PM PDT 24
Finished Aug 18 05:31:02 PM PDT 24
Peak memory 198600 kb
Host smart-6b13ef4e-622c-42c0-a105-b5ecdc8d4189
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248587716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.3248587716
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.1865588241
Short name T45
Test name
Test status
Simulation time 348752270 ps
CPU time 1.15 seconds
Started Aug 18 05:31:05 PM PDT 24
Finished Aug 18 05:31:06 PM PDT 24
Peak memory 198476 kb
Host smart-538021a1-58e0-4261-9bc4-cf125a868aea
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865588241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.1865588241
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.4072036058
Short name T94
Test name
Test status
Simulation time 180445995 ps
CPU time 2.41 seconds
Started Aug 18 05:31:05 PM PDT 24
Finished Aug 18 05:31:08 PM PDT 24
Peak memory 197496 kb
Host smart-f154b4fd-3c7a-420f-b13a-942a4886c188
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072036058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.4072036058
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.346028825
Short name T96
Test name
Test status
Simulation time 278934244 ps
CPU time 0.64 seconds
Started Aug 18 05:31:04 PM PDT 24
Finished Aug 18 05:31:05 PM PDT 24
Peak memory 196000 kb
Host smart-f2d3bfd2-04b7-4f7c-a1ed-cede06efa911
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346028825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.346028825
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.3947113208
Short name T757
Test name
Test status
Simulation time 100030575 ps
CPU time 0.76 seconds
Started Aug 18 05:31:15 PM PDT 24
Finished Aug 18 05:31:16 PM PDT 24
Peak memory 198420 kb
Host smart-9e55d256-cd11-49e4-b024-af9d8244f819
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947113208 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.3947113208
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.1744768360
Short name T806
Test name
Test status
Simulation time 13528888 ps
CPU time 0.59 seconds
Started Aug 18 05:31:01 PM PDT 24
Finished Aug 18 05:31:02 PM PDT 24
Peak memory 195060 kb
Host smart-7197d3a3-8c3c-409a-8d14-1d8ea8635831
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744768360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.1744768360
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.2487131390
Short name T729
Test name
Test status
Simulation time 18555959 ps
CPU time 0.62 seconds
Started Aug 18 05:31:00 PM PDT 24
Finished Aug 18 05:31:00 PM PDT 24
Peak memory 194260 kb
Host smart-084bcd4e-d40f-4c1c-af9c-def5f3941ec0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487131390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.2487131390
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.1436554124
Short name T841
Test name
Test status
Simulation time 33796854 ps
CPU time 1.02 seconds
Started Aug 18 05:31:06 PM PDT 24
Finished Aug 18 05:31:07 PM PDT 24
Peak memory 198296 kb
Host smart-abd2e56e-c849-4f78-baeb-e12083711364
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436554124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.1436554124
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.3483409208
Short name T46
Test name
Test status
Simulation time 133818012 ps
CPU time 1.46 seconds
Started Aug 18 05:31:05 PM PDT 24
Finished Aug 18 05:31:06 PM PDT 24
Peak memory 198532 kb
Host smart-e0448bf1-acc2-4f52-99bf-cffd1a9fbc67
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483409208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.3483409208
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.1993582032
Short name T808
Test name
Test status
Simulation time 100831336 ps
CPU time 1.26 seconds
Started Aug 18 05:31:14 PM PDT 24
Finished Aug 18 05:31:15 PM PDT 24
Peak memory 198644 kb
Host smart-67e81f86-51c1-4744-94a8-56f8d7db21d6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993582032 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.1993582032
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.720306014
Short name T90
Test name
Test status
Simulation time 11688146 ps
CPU time 0.62 seconds
Started Aug 18 05:31:11 PM PDT 24
Finished Aug 18 05:31:11 PM PDT 24
Peak memory 195252 kb
Host smart-f98a071c-6f34-443b-ad55-e72ec4c7c12e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720306014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio
_csr_rw.720306014
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.1011298713
Short name T779
Test name
Test status
Simulation time 14287786 ps
CPU time 0.61 seconds
Started Aug 18 05:31:05 PM PDT 24
Finished Aug 18 05:31:06 PM PDT 24
Peak memory 194816 kb
Host smart-6b95ca5d-f2b7-4897-a9cd-d20c5b6794d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011298713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.1011298713
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.2469975231
Short name T82
Test name
Test status
Simulation time 48934596 ps
CPU time 0.75 seconds
Started Aug 18 05:31:04 PM PDT 24
Finished Aug 18 05:31:05 PM PDT 24
Peak memory 197232 kb
Host smart-ee163dba-b5a5-45f9-b514-f75fbfa3f9de
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469975231 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.2469975231
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.2444911825
Short name T791
Test name
Test status
Simulation time 119485313 ps
CPU time 2.41 seconds
Started Aug 18 05:31:03 PM PDT 24
Finished Aug 18 05:31:06 PM PDT 24
Peak memory 198656 kb
Host smart-021580fe-60f6-41a1-9bc9-6568305f7ebe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444911825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.2444911825
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.3595485554
Short name T740
Test name
Test status
Simulation time 17287603 ps
CPU time 0.9 seconds
Started Aug 18 05:31:07 PM PDT 24
Finished Aug 18 05:31:08 PM PDT 24
Peak memory 198360 kb
Host smart-08443455-cbb8-493f-9f96-bb979ba79681
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595485554 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.3595485554
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.798532311
Short name T88
Test name
Test status
Simulation time 36711823 ps
CPU time 0.58 seconds
Started Aug 18 05:30:59 PM PDT 24
Finished Aug 18 05:31:00 PM PDT 24
Peak memory 193692 kb
Host smart-2cdb3d5e-9861-4180-965c-18ba266477fd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798532311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio
_csr_rw.798532311
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.1205537905
Short name T752
Test name
Test status
Simulation time 53196525 ps
CPU time 0.58 seconds
Started Aug 18 05:31:13 PM PDT 24
Finished Aug 18 05:31:14 PM PDT 24
Peak memory 194860 kb
Host smart-c22300d8-93b3-47d1-a08d-ea3c33dc2b01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205537905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.1205537905
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.3821766042
Short name T102
Test name
Test status
Simulation time 21376512 ps
CPU time 0.89 seconds
Started Aug 18 05:31:04 PM PDT 24
Finished Aug 18 05:31:05 PM PDT 24
Peak memory 197868 kb
Host smart-1e68acde-616b-4588-a001-e7fd76d50ffc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821766042 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.3821766042
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.1164603325
Short name T836
Test name
Test status
Simulation time 539380269 ps
CPU time 2.27 seconds
Started Aug 18 05:31:02 PM PDT 24
Finished Aug 18 05:31:04 PM PDT 24
Peak memory 198472 kb
Host smart-dfdee855-5771-4996-b32e-9bcc6341982d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164603325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.1164603325
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.2703726232
Short name T773
Test name
Test status
Simulation time 232689549 ps
CPU time 0.84 seconds
Started Aug 18 05:31:04 PM PDT 24
Finished Aug 18 05:31:05 PM PDT 24
Peak memory 198260 kb
Host smart-781cbf5f-f73a-475a-aa02-a7b9c7314155
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703726232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.2703726232
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.2211710406
Short name T770
Test name
Test status
Simulation time 15466494 ps
CPU time 0.77 seconds
Started Aug 18 05:31:05 PM PDT 24
Finished Aug 18 05:31:06 PM PDT 24
Peak memory 198412 kb
Host smart-e2713fe8-991f-423c-a70e-18cfdc7d00e5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211710406 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.2211710406
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.2937641663
Short name T787
Test name
Test status
Simulation time 27387677 ps
CPU time 0.63 seconds
Started Aug 18 05:31:21 PM PDT 24
Finished Aug 18 05:31:22 PM PDT 24
Peak memory 195500 kb
Host smart-21f57d03-65c8-42d6-b76d-2cda4a435969
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937641663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.2937641663
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.3871954719
Short name T783
Test name
Test status
Simulation time 32930488 ps
CPU time 0.56 seconds
Started Aug 18 05:31:18 PM PDT 24
Finished Aug 18 05:31:19 PM PDT 24
Peak memory 194840 kb
Host smart-ca516647-ae26-4164-8b14-a87c499539ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871954719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.3871954719
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.1792486715
Short name T767
Test name
Test status
Simulation time 22559802 ps
CPU time 0.67 seconds
Started Aug 18 05:31:07 PM PDT 24
Finished Aug 18 05:31:07 PM PDT 24
Peak memory 195072 kb
Host smart-2a6993b9-592e-488d-83da-03b239b66532
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792486715 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.1792486715
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.724530000
Short name T751
Test name
Test status
Simulation time 86395745 ps
CPU time 1.22 seconds
Started Aug 18 05:31:05 PM PDT 24
Finished Aug 18 05:31:06 PM PDT 24
Peak memory 198620 kb
Host smart-11d8bb31-df1d-4368-a995-b9bced506715
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724530000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.724530000
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.3375337361
Short name T742
Test name
Test status
Simulation time 51555333 ps
CPU time 0.87 seconds
Started Aug 18 05:31:26 PM PDT 24
Finished Aug 18 05:31:27 PM PDT 24
Peak memory 197652 kb
Host smart-e60350e4-d24f-442e-9012-6c4f5ef25305
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375337361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.3375337361
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.250743419
Short name T743
Test name
Test status
Simulation time 76816347 ps
CPU time 0.98 seconds
Started Aug 18 05:31:01 PM PDT 24
Finished Aug 18 05:31:02 PM PDT 24
Peak memory 198412 kb
Host smart-c6c89d6c-a65a-4818-884b-8d209b6718cf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250743419 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.250743419
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.774326430
Short name T822
Test name
Test status
Simulation time 55172536 ps
CPU time 0.63 seconds
Started Aug 18 05:31:01 PM PDT 24
Finished Aug 18 05:31:02 PM PDT 24
Peak memory 195328 kb
Host smart-aede768f-7c5b-4de2-967f-d14058245f1a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774326430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio
_csr_rw.774326430
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.1539909667
Short name T725
Test name
Test status
Simulation time 44846447 ps
CPU time 0.61 seconds
Started Aug 18 05:31:01 PM PDT 24
Finished Aug 18 05:31:02 PM PDT 24
Peak memory 194312 kb
Host smart-fd5eea73-322f-4997-a3f7-c10d93b83d5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539909667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.1539909667
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.3030967722
Short name T100
Test name
Test status
Simulation time 16148851 ps
CPU time 0.71 seconds
Started Aug 18 05:31:04 PM PDT 24
Finished Aug 18 05:31:05 PM PDT 24
Peak memory 195228 kb
Host smart-7605adce-70ef-482a-a0f1-e38359ded124
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030967722 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.3030967722
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.77072377
Short name T745
Test name
Test status
Simulation time 257452000 ps
CPU time 1.46 seconds
Started Aug 18 05:31:04 PM PDT 24
Finished Aug 18 05:31:06 PM PDT 24
Peak memory 198516 kb
Host smart-ca5ae35b-c7a6-44c7-a87c-baff2e7be6b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77072377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.77072377
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.933884801
Short name T807
Test name
Test status
Simulation time 67565147 ps
CPU time 1.13 seconds
Started Aug 18 05:31:03 PM PDT 24
Finished Aug 18 05:31:05 PM PDT 24
Peak memory 198536 kb
Host smart-5e8cca63-5f51-4166-bc01-128fbb4c0965
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933884801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 13.gpio_tl_intg_err.933884801
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.456336307
Short name T837
Test name
Test status
Simulation time 60929662 ps
CPU time 0.68 seconds
Started Aug 18 05:31:12 PM PDT 24
Finished Aug 18 05:31:12 PM PDT 24
Peak memory 197524 kb
Host smart-f0a84f50-7251-47b4-b414-6b07faf05df2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456336307 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.456336307
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.1657674862
Short name T790
Test name
Test status
Simulation time 18069275 ps
CPU time 0.58 seconds
Started Aug 18 05:31:00 PM PDT 24
Finished Aug 18 05:31:00 PM PDT 24
Peak memory 193792 kb
Host smart-8992b541-c297-47c3-aa0f-efb9c97809ad
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657674862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.1657674862
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.677025976
Short name T786
Test name
Test status
Simulation time 14824967 ps
CPU time 0.62 seconds
Started Aug 18 05:31:15 PM PDT 24
Finished Aug 18 05:31:16 PM PDT 24
Peak memory 194228 kb
Host smart-c0ff27ae-f1d7-40d3-884e-b068c4d97fc7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677025976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.677025976
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.2970080640
Short name T99
Test name
Test status
Simulation time 24746439 ps
CPU time 0.71 seconds
Started Aug 18 05:31:03 PM PDT 24
Finished Aug 18 05:31:09 PM PDT 24
Peak memory 196136 kb
Host smart-9650bb52-98c4-47a0-b9c1-9779c2790d5d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970080640 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.2970080640
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.3818142948
Short name T732
Test name
Test status
Simulation time 57001230 ps
CPU time 1.62 seconds
Started Aug 18 05:31:22 PM PDT 24
Finished Aug 18 05:31:23 PM PDT 24
Peak memory 198592 kb
Host smart-4bcd3add-d070-45a7-83e0-cb5a181b6bc3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818142948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.3818142948
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.4035359760
Short name T834
Test name
Test status
Simulation time 49978182 ps
CPU time 0.84 seconds
Started Aug 18 05:31:06 PM PDT 24
Finished Aug 18 05:31:07 PM PDT 24
Peak memory 197608 kb
Host smart-d70b6166-4f08-4b84-9e2e-0410455984b9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035359760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.4035359760
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.3706481133
Short name T798
Test name
Test status
Simulation time 116003410 ps
CPU time 0.91 seconds
Started Aug 18 05:31:20 PM PDT 24
Finished Aug 18 05:31:21 PM PDT 24
Peak memory 198112 kb
Host smart-ca63a7a9-f8bc-424f-81a3-c81ec4755c1e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706481133 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.3706481133
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.1967954573
Short name T104
Test name
Test status
Simulation time 13285199 ps
CPU time 0.59 seconds
Started Aug 18 05:31:21 PM PDT 24
Finished Aug 18 05:31:21 PM PDT 24
Peak memory 194736 kb
Host smart-65b344ec-fb9a-40a5-a5b0-49f5cdc23e34
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967954573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.1967954573
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.2703775389
Short name T829
Test name
Test status
Simulation time 84100242 ps
CPU time 0.55 seconds
Started Aug 18 05:31:30 PM PDT 24
Finished Aug 18 05:31:30 PM PDT 24
Peak memory 194212 kb
Host smart-4b0a06f6-326f-404d-9ef5-11c54d024c29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703775389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.2703775389
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.1146888229
Short name T828
Test name
Test status
Simulation time 501454015 ps
CPU time 0.87 seconds
Started Aug 18 05:31:08 PM PDT 24
Finished Aug 18 05:31:09 PM PDT 24
Peak memory 196668 kb
Host smart-d03d8ccf-605c-47e9-a724-99acf160eb2d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146888229 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.1146888229
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.727928588
Short name T730
Test name
Test status
Simulation time 142693297 ps
CPU time 2.93 seconds
Started Aug 18 05:31:34 PM PDT 24
Finished Aug 18 05:31:37 PM PDT 24
Peak memory 198756 kb
Host smart-d39d4e3a-a3fb-48d2-ae1a-fba791d51277
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727928588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.727928588
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.1481094422
Short name T33
Test name
Test status
Simulation time 205610329 ps
CPU time 0.88 seconds
Started Aug 18 05:31:27 PM PDT 24
Finished Aug 18 05:31:28 PM PDT 24
Peak memory 197408 kb
Host smart-eb0d0b97-376b-4222-b9f4-db6cf906a741
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481094422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.1481094422
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.939620424
Short name T721
Test name
Test status
Simulation time 244803113 ps
CPU time 0.99 seconds
Started Aug 18 05:31:20 PM PDT 24
Finished Aug 18 05:31:21 PM PDT 24
Peak memory 198616 kb
Host smart-85e5876d-0d7e-4e37-af4e-42fea9faf0f0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939620424 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.939620424
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.881131274
Short name T741
Test name
Test status
Simulation time 22956585 ps
CPU time 0.59 seconds
Started Aug 18 05:31:36 PM PDT 24
Finished Aug 18 05:31:37 PM PDT 24
Peak memory 195056 kb
Host smart-a6c68c8a-bd50-4608-86ed-0e11409c0299
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881131274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio
_csr_rw.881131274
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.3245734137
Short name T794
Test name
Test status
Simulation time 12108928 ps
CPU time 0.6 seconds
Started Aug 18 05:31:21 PM PDT 24
Finished Aug 18 05:31:27 PM PDT 24
Peak memory 194308 kb
Host smart-5e12c51d-408f-4cc2-8b15-fdafc0ee91b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245734137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.3245734137
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.3983203937
Short name T796
Test name
Test status
Simulation time 34427627 ps
CPU time 0.83 seconds
Started Aug 18 05:31:35 PM PDT 24
Finished Aug 18 05:31:36 PM PDT 24
Peak memory 197208 kb
Host smart-d08b8c9e-b3fb-4c70-80f9-056c4047c70a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983203937 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.3983203937
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.2184068043
Short name T737
Test name
Test status
Simulation time 471445111 ps
CPU time 1.66 seconds
Started Aug 18 05:31:10 PM PDT 24
Finished Aug 18 05:31:12 PM PDT 24
Peak memory 198604 kb
Host smart-ad89d9c0-30fb-4957-9140-99f01f13b74b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184068043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.2184068043
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.2681128596
Short name T32
Test name
Test status
Simulation time 400119651 ps
CPU time 1.35 seconds
Started Aug 18 05:31:05 PM PDT 24
Finished Aug 18 05:31:07 PM PDT 24
Peak memory 198528 kb
Host smart-49f18d3a-d31f-4312-bf0f-6b17252589a3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681128596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.2681128596
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.1043869025
Short name T766
Test name
Test status
Simulation time 229343583 ps
CPU time 1.17 seconds
Started Aug 18 05:31:16 PM PDT 24
Finished Aug 18 05:31:17 PM PDT 24
Peak memory 198408 kb
Host smart-5af511fc-d1cf-48dd-b38f-8e8151e4d064
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043869025 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.1043869025
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.3226021023
Short name T746
Test name
Test status
Simulation time 18570499 ps
CPU time 0.63 seconds
Started Aug 18 05:31:16 PM PDT 24
Finished Aug 18 05:31:17 PM PDT 24
Peak memory 195172 kb
Host smart-20f11cee-0139-4f4e-886c-94fbfe506c59
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226021023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi
o_csr_rw.3226021023
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.1372097190
Short name T769
Test name
Test status
Simulation time 64941149 ps
CPU time 0.62 seconds
Started Aug 18 05:31:03 PM PDT 24
Finished Aug 18 05:31:04 PM PDT 24
Peak memory 194208 kb
Host smart-f2bfd726-62d3-4086-90c5-db7d052176be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372097190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.1372097190
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.2281949895
Short name T77
Test name
Test status
Simulation time 97708495 ps
CPU time 0.85 seconds
Started Aug 18 05:31:14 PM PDT 24
Finished Aug 18 05:31:15 PM PDT 24
Peak memory 196520 kb
Host smart-0ded4543-eb65-4be0-b2e6-0b46bdf851ad
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281949895 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.2281949895
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.67067981
Short name T812
Test name
Test status
Simulation time 215846691 ps
CPU time 2.46 seconds
Started Aug 18 05:31:14 PM PDT 24
Finished Aug 18 05:31:17 PM PDT 24
Peak memory 198568 kb
Host smart-1fcb4de3-5e9d-4a6d-b805-380a2d74121c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67067981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.67067981
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.3126710383
Short name T835
Test name
Test status
Simulation time 129529359 ps
CPU time 1.43 seconds
Started Aug 18 05:31:17 PM PDT 24
Finished Aug 18 05:31:19 PM PDT 24
Peak memory 198448 kb
Host smart-7b4d49e3-b423-41de-a27f-dfa8df6c7cbd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126710383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.3126710383
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.3189059980
Short name T728
Test name
Test status
Simulation time 17162724 ps
CPU time 0.66 seconds
Started Aug 18 05:31:20 PM PDT 24
Finished Aug 18 05:31:21 PM PDT 24
Peak memory 197352 kb
Host smart-83df7e18-7415-4c8d-b972-c68e4f1c418f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189059980 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.3189059980
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.2666796290
Short name T103
Test name
Test status
Simulation time 15094607 ps
CPU time 0.63 seconds
Started Aug 18 05:31:11 PM PDT 24
Finished Aug 18 05:31:12 PM PDT 24
Peak memory 195912 kb
Host smart-c5aa4881-f6ac-489e-a692-c7aa03e7f6a7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666796290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.2666796290
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.409745751
Short name T720
Test name
Test status
Simulation time 50222078 ps
CPU time 0.56 seconds
Started Aug 18 05:31:37 PM PDT 24
Finished Aug 18 05:31:37 PM PDT 24
Peak memory 193996 kb
Host smart-dfdc68df-4e71-47fc-9148-059150ded093
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409745751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.409745751
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.1097208253
Short name T762
Test name
Test status
Simulation time 72112280 ps
CPU time 0.84 seconds
Started Aug 18 05:31:18 PM PDT 24
Finished Aug 18 05:31:19 PM PDT 24
Peak memory 197556 kb
Host smart-303c75a5-0bd4-4455-8847-bf9da1b607d7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097208253 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.1097208253
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.3587173964
Short name T820
Test name
Test status
Simulation time 207073883 ps
CPU time 2.68 seconds
Started Aug 18 05:31:36 PM PDT 24
Finished Aug 18 05:31:39 PM PDT 24
Peak memory 198324 kb
Host smart-b456193e-2976-4e46-86b7-f9a61236588e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587173964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.3587173964
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.767858921
Short name T824
Test name
Test status
Simulation time 20205688 ps
CPU time 0.87 seconds
Started Aug 18 05:31:04 PM PDT 24
Finished Aug 18 05:31:05 PM PDT 24
Peak memory 198384 kb
Host smart-c566623e-5001-4332-a22c-921f60b7c705
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767858921 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.767858921
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.2687465796
Short name T87
Test name
Test status
Simulation time 16849502 ps
CPU time 0.62 seconds
Started Aug 18 05:31:17 PM PDT 24
Finished Aug 18 05:31:18 PM PDT 24
Peak memory 195868 kb
Host smart-bb6cc671-7965-422c-972a-9b9d4205c503
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687465796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.2687465796
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.1715534031
Short name T765
Test name
Test status
Simulation time 23879306 ps
CPU time 0.59 seconds
Started Aug 18 05:31:31 PM PDT 24
Finished Aug 18 05:31:31 PM PDT 24
Peak memory 194036 kb
Host smart-8375df65-36ea-4046-8ae7-08454b5db55b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715534031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.1715534031
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.1009315309
Short name T83
Test name
Test status
Simulation time 120439832 ps
CPU time 0.86 seconds
Started Aug 18 05:31:31 PM PDT 24
Finished Aug 18 05:31:32 PM PDT 24
Peak memory 196364 kb
Host smart-57524a1c-87f0-461d-bad5-70a65f5fcb01
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009315309 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.1009315309
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.2351060754
Short name T768
Test name
Test status
Simulation time 34121232 ps
CPU time 1.78 seconds
Started Aug 18 05:31:18 PM PDT 24
Finished Aug 18 05:31:20 PM PDT 24
Peak memory 198612 kb
Host smart-2f739431-ad0e-4572-aa43-9a26514bc4a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351060754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.2351060754
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.2516158660
Short name T48
Test name
Test status
Simulation time 707054913 ps
CPU time 1.15 seconds
Started Aug 18 05:31:16 PM PDT 24
Finished Aug 18 05:31:17 PM PDT 24
Peak memory 198536 kb
Host smart-bf222483-d72d-47a5-9764-9fa9fffb33bd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516158660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.2516158660
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.1845103272
Short name T91
Test name
Test status
Simulation time 19646877 ps
CPU time 0.68 seconds
Started Aug 18 05:31:10 PM PDT 24
Finished Aug 18 05:31:11 PM PDT 24
Peak memory 195048 kb
Host smart-539acab3-2187-4d65-9714-98302fe1974d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845103272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.1845103272
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.118582058
Short name T86
Test name
Test status
Simulation time 36114562 ps
CPU time 1.41 seconds
Started Aug 18 05:31:01 PM PDT 24
Finished Aug 18 05:31:02 PM PDT 24
Peak memory 197280 kb
Host smart-0347c395-139c-45dd-8081-03523486a3f7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118582058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.118582058
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.1917413019
Short name T797
Test name
Test status
Simulation time 28106821 ps
CPU time 0.69 seconds
Started Aug 18 05:31:05 PM PDT 24
Finished Aug 18 05:31:06 PM PDT 24
Peak memory 195864 kb
Host smart-5b1ea2fd-0bf4-4682-9d64-d5dbdf8bf930
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917413019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.1917413019
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.209065281
Short name T789
Test name
Test status
Simulation time 58957962 ps
CPU time 0.67 seconds
Started Aug 18 05:31:15 PM PDT 24
Finished Aug 18 05:31:16 PM PDT 24
Peak memory 197280 kb
Host smart-8e06609d-e3a7-4655-9eb5-77ea7ed0ba2b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209065281 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.209065281
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.2633433427
Short name T818
Test name
Test status
Simulation time 12410128 ps
CPU time 0.66 seconds
Started Aug 18 05:30:59 PM PDT 24
Finished Aug 18 05:31:00 PM PDT 24
Peak memory 195148 kb
Host smart-4069908f-644d-4a10-931c-9f48ea121314
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633433427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.2633433427
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.4256851541
Short name T723
Test name
Test status
Simulation time 26073431 ps
CPU time 0.66 seconds
Started Aug 18 05:31:04 PM PDT 24
Finished Aug 18 05:31:04 PM PDT 24
Peak memory 194168 kb
Host smart-ca42854b-dc57-4acb-8e43-6e7b6d386f42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256851541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.4256851541
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.4189570008
Short name T793
Test name
Test status
Simulation time 29197403 ps
CPU time 0.64 seconds
Started Aug 18 05:31:00 PM PDT 24
Finished Aug 18 05:31:00 PM PDT 24
Peak memory 194828 kb
Host smart-68234186-eab3-46ec-b818-ad333e952178
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189570008 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.4189570008
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.827396919
Short name T784
Test name
Test status
Simulation time 37202730 ps
CPU time 1.83 seconds
Started Aug 18 05:31:04 PM PDT 24
Finished Aug 18 05:31:06 PM PDT 24
Peak memory 198552 kb
Host smart-6b7ea61b-0479-4ad9-9dc1-d9456236c560
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827396919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.827396919
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.1629011514
Short name T804
Test name
Test status
Simulation time 311757681 ps
CPU time 1.13 seconds
Started Aug 18 05:31:08 PM PDT 24
Finished Aug 18 05:31:09 PM PDT 24
Peak memory 198500 kb
Host smart-f540ca7a-045d-4f65-abdc-64de14cd9ef8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629011514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.1629011514
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.3030658481
Short name T799
Test name
Test status
Simulation time 43551281 ps
CPU time 0.59 seconds
Started Aug 18 05:31:40 PM PDT 24
Finished Aug 18 05:31:41 PM PDT 24
Peak memory 194888 kb
Host smart-750f3294-a3d8-47db-8d3a-429fb2cb36bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030658481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.3030658481
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.268757310
Short name T805
Test name
Test status
Simulation time 97510241 ps
CPU time 0.66 seconds
Started Aug 18 05:31:05 PM PDT 24
Finished Aug 18 05:31:06 PM PDT 24
Peak memory 194164 kb
Host smart-ef302733-1d1b-4727-8987-4e37006914d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268757310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.268757310
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.3348089827
Short name T719
Test name
Test status
Simulation time 18277081 ps
CPU time 0.57 seconds
Started Aug 18 05:31:38 PM PDT 24
Finished Aug 18 05:31:39 PM PDT 24
Peak memory 194208 kb
Host smart-b91bb42c-1128-4d0a-9bd9-bf9262b29c9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348089827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.3348089827
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.1715833340
Short name T792
Test name
Test status
Simulation time 15299407 ps
CPU time 0.6 seconds
Started Aug 18 05:31:25 PM PDT 24
Finished Aug 18 05:31:31 PM PDT 24
Peak memory 194124 kb
Host smart-f8b86c08-695f-4479-a78e-e5665a17aef3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715833340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.1715833340
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.2844575844
Short name T754
Test name
Test status
Simulation time 30460259 ps
CPU time 0.59 seconds
Started Aug 18 05:31:21 PM PDT 24
Finished Aug 18 05:31:22 PM PDT 24
Peak memory 194000 kb
Host smart-49f30086-feac-4b08-a445-89866e1acbd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844575844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.2844575844
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.317824977
Short name T727
Test name
Test status
Simulation time 28548680 ps
CPU time 0.62 seconds
Started Aug 18 05:31:07 PM PDT 24
Finished Aug 18 05:31:08 PM PDT 24
Peak memory 194872 kb
Host smart-6335c69a-9b74-49bf-971c-98551b7828ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317824977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.317824977
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.1989910513
Short name T748
Test name
Test status
Simulation time 46515281 ps
CPU time 0.59 seconds
Started Aug 18 05:31:27 PM PDT 24
Finished Aug 18 05:31:28 PM PDT 24
Peak memory 194196 kb
Host smart-aadb308b-a160-4e10-a657-3fc0fa0f7d56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989910513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.1989910513
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.1031821885
Short name T726
Test name
Test status
Simulation time 13789983 ps
CPU time 0.61 seconds
Started Aug 18 05:31:28 PM PDT 24
Finished Aug 18 05:31:29 PM PDT 24
Peak memory 193944 kb
Host smart-f892ee07-c783-49cc-8aaa-983dbc7168e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031821885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.1031821885
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.1667933184
Short name T803
Test name
Test status
Simulation time 37004931 ps
CPU time 0.65 seconds
Started Aug 18 05:31:16 PM PDT 24
Finished Aug 18 05:31:17 PM PDT 24
Peak memory 194248 kb
Host smart-30873a19-3b65-47e5-b951-7951576b0b70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667933184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.1667933184
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.1207844845
Short name T810
Test name
Test status
Simulation time 19490717 ps
CPU time 0.62 seconds
Started Aug 18 05:31:24 PM PDT 24
Finished Aug 18 05:31:29 PM PDT 24
Peak memory 194312 kb
Host smart-3e49ddf6-5a7c-4cc1-a637-014a4121d92a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207844845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.1207844845
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.27415404
Short name T93
Test name
Test status
Simulation time 37162170 ps
CPU time 0.89 seconds
Started Aug 18 05:31:17 PM PDT 24
Finished Aug 18 05:31:18 PM PDT 24
Peak memory 196480 kb
Host smart-a53a0036-6cb9-4518-8776-8848a9a8f8db
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27415404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
gpio_csr_aliasing.27415404
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.586700829
Short name T81
Test name
Test status
Simulation time 378365124 ps
CPU time 3.28 seconds
Started Aug 18 05:31:01 PM PDT 24
Finished Aug 18 05:31:05 PM PDT 24
Peak memory 197140 kb
Host smart-67bdb3f5-0c1d-4961-aac5-6ea0e78ac876
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586700829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.586700829
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.3250539341
Short name T755
Test name
Test status
Simulation time 39559771 ps
CPU time 0.59 seconds
Started Aug 18 05:31:12 PM PDT 24
Finished Aug 18 05:31:12 PM PDT 24
Peak memory 195056 kb
Host smart-b809790b-f2ba-4ab3-9413-a7c4f2fc4e77
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250539341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.3250539341
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.3457593207
Short name T744
Test name
Test status
Simulation time 29980629 ps
CPU time 0.76 seconds
Started Aug 18 05:30:58 PM PDT 24
Finished Aug 18 05:30:59 PM PDT 24
Peak memory 198416 kb
Host smart-bcaa4151-55ed-4ac6-88d8-7a9c38bb1fd9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457593207 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.3457593207
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.1938491197
Short name T79
Test name
Test status
Simulation time 45911850 ps
CPU time 0.75 seconds
Started Aug 18 05:31:01 PM PDT 24
Finished Aug 18 05:31:01 PM PDT 24
Peak memory 195244 kb
Host smart-f436de20-47b9-41c3-846f-b3c560c823b7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938491197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.1938491197
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.3264430846
Short name T815
Test name
Test status
Simulation time 13562306 ps
CPU time 0.59 seconds
Started Aug 18 05:31:00 PM PDT 24
Finished Aug 18 05:31:01 PM PDT 24
Peak memory 194200 kb
Host smart-95f52a9e-aad6-4d7b-a9b5-f627f0893045
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264430846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.3264430846
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.3254461686
Short name T85
Test name
Test status
Simulation time 106416619 ps
CPU time 0.7 seconds
Started Aug 18 05:31:07 PM PDT 24
Finished Aug 18 05:31:08 PM PDT 24
Peak memory 195308 kb
Host smart-0fe4ec38-2586-4375-9f1e-32799b98fe6a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254461686 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.3254461686
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.1691915413
Short name T800
Test name
Test status
Simulation time 166729774 ps
CPU time 2.51 seconds
Started Aug 18 05:31:05 PM PDT 24
Finished Aug 18 05:31:07 PM PDT 24
Peak memory 198592 kb
Host smart-bc944325-3288-417a-b4e4-4dc35cb14705
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691915413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.1691915413
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.577327356
Short name T47
Test name
Test status
Simulation time 50673369 ps
CPU time 0.86 seconds
Started Aug 18 05:31:17 PM PDT 24
Finished Aug 18 05:31:23 PM PDT 24
Peak memory 197672 kb
Host smart-c83ae7b5-6c57-422f-a6b1-e354c80927f7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577327356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 3.gpio_tl_intg_err.577327356
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.2429219293
Short name T758
Test name
Test status
Simulation time 12795494 ps
CPU time 0.61 seconds
Started Aug 18 05:31:17 PM PDT 24
Finished Aug 18 05:31:18 PM PDT 24
Peak memory 194300 kb
Host smart-9348f725-febe-4b8b-92f7-e4202eb632cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429219293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.2429219293
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.3555213863
Short name T747
Test name
Test status
Simulation time 17184872 ps
CPU time 0.63 seconds
Started Aug 18 05:31:07 PM PDT 24
Finished Aug 18 05:31:08 PM PDT 24
Peak memory 194348 kb
Host smart-c16b0ec2-547c-4ac8-9d42-0eb261acf56a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555213863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.3555213863
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.1042759862
Short name T771
Test name
Test status
Simulation time 10722316 ps
CPU time 0.56 seconds
Started Aug 18 05:31:16 PM PDT 24
Finished Aug 18 05:31:17 PM PDT 24
Peak memory 194844 kb
Host smart-259640e3-b065-4763-81af-cba4d57a96f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042759862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.1042759862
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.1777712031
Short name T782
Test name
Test status
Simulation time 51697110 ps
CPU time 0.6 seconds
Started Aug 18 05:31:16 PM PDT 24
Finished Aug 18 05:31:17 PM PDT 24
Peak memory 194244 kb
Host smart-5c29ce5b-53a8-462f-8eed-1f5f369eec6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777712031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.1777712031
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.1500652234
Short name T764
Test name
Test status
Simulation time 50841061 ps
CPU time 0.58 seconds
Started Aug 18 05:31:27 PM PDT 24
Finished Aug 18 05:31:28 PM PDT 24
Peak memory 194868 kb
Host smart-6a908b13-a140-433b-8e3d-5342c859e821
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500652234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.1500652234
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.3619301744
Short name T785
Test name
Test status
Simulation time 22612560 ps
CPU time 0.61 seconds
Started Aug 18 05:31:10 PM PDT 24
Finished Aug 18 05:31:10 PM PDT 24
Peak memory 194924 kb
Host smart-39d90731-5f12-4b76-b341-dd58632a221f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619301744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.3619301744
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.3720966408
Short name T777
Test name
Test status
Simulation time 54964902 ps
CPU time 0.59 seconds
Started Aug 18 05:31:15 PM PDT 24
Finished Aug 18 05:31:16 PM PDT 24
Peak memory 194304 kb
Host smart-7afa13b5-ff1c-4ad0-ba60-3c3c865b2ebc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720966408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.3720966408
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.4022507825
Short name T776
Test name
Test status
Simulation time 19966531 ps
CPU time 0.6 seconds
Started Aug 18 05:31:19 PM PDT 24
Finished Aug 18 05:31:20 PM PDT 24
Peak memory 194276 kb
Host smart-69feb4d0-e724-42ad-8f24-947bbc8f0203
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022507825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.4022507825
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.3773451065
Short name T733
Test name
Test status
Simulation time 13049227 ps
CPU time 0.59 seconds
Started Aug 18 05:31:11 PM PDT 24
Finished Aug 18 05:31:12 PM PDT 24
Peak memory 194188 kb
Host smart-8c9f3764-c8a6-45eb-a64f-675d9a38874e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773451065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.3773451065
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.1322049115
Short name T839
Test name
Test status
Simulation time 51442507 ps
CPU time 0.62 seconds
Started Aug 18 05:31:11 PM PDT 24
Finished Aug 18 05:31:12 PM PDT 24
Peak memory 194220 kb
Host smart-36c35d39-37e3-43e6-8f3b-7a97f8e712be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322049115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.1322049115
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.353745480
Short name T759
Test name
Test status
Simulation time 47548174 ps
CPU time 0.76 seconds
Started Aug 18 05:31:03 PM PDT 24
Finished Aug 18 05:31:04 PM PDT 24
Peak memory 196132 kb
Host smart-eba2161a-b17b-4745-9c4f-6b40b813d0f7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353745480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4
.gpio_csr_aliasing.353745480
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.889134316
Short name T761
Test name
Test status
Simulation time 755863631 ps
CPU time 2.3 seconds
Started Aug 18 05:31:03 PM PDT 24
Finished Aug 18 05:31:05 PM PDT 24
Peak memory 198424 kb
Host smart-fac4b5b6-b910-46f5-882d-90bf4443731e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889134316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.889134316
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.1578946674
Short name T731
Test name
Test status
Simulation time 28062789 ps
CPU time 0.59 seconds
Started Aug 18 05:31:06 PM PDT 24
Finished Aug 18 05:31:07 PM PDT 24
Peak memory 194788 kb
Host smart-997676b8-050d-43ad-97bd-ecb2925b9f0b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578946674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.1578946674
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.233017511
Short name T736
Test name
Test status
Simulation time 28835679 ps
CPU time 0.76 seconds
Started Aug 18 05:31:12 PM PDT 24
Finished Aug 18 05:31:13 PM PDT 24
Peak memory 198376 kb
Host smart-5e6c83ca-754f-438d-a53f-157eef498fd4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233017511 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.233017511
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.954279098
Short name T92
Test name
Test status
Simulation time 41897519 ps
CPU time 0.63 seconds
Started Aug 18 05:31:03 PM PDT 24
Finished Aug 18 05:31:04 PM PDT 24
Peak memory 195616 kb
Host smart-393f864e-5561-453f-9032-9202be53cf94
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954279098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_
csr_rw.954279098
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.651875420
Short name T813
Test name
Test status
Simulation time 27853851 ps
CPU time 0.56 seconds
Started Aug 18 05:30:58 PM PDT 24
Finished Aug 18 05:30:59 PM PDT 24
Peak memory 194188 kb
Host smart-81c3cf46-ecfb-41a8-9181-e6956016e6f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651875420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.651875420
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.3469989304
Short name T772
Test name
Test status
Simulation time 12887269 ps
CPU time 0.64 seconds
Started Aug 18 05:31:11 PM PDT 24
Finished Aug 18 05:31:11 PM PDT 24
Peak memory 195244 kb
Host smart-4b5d0330-34b1-4dfc-baee-9f6ad4ed0e42
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469989304 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.3469989304
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.3699175419
Short name T819
Test name
Test status
Simulation time 232621374 ps
CPU time 2.87 seconds
Started Aug 18 05:31:03 PM PDT 24
Finished Aug 18 05:31:06 PM PDT 24
Peak memory 198556 kb
Host smart-33daef1c-e89c-4124-a7b9-0175dc0dae31
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699175419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.3699175419
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.2585051101
Short name T43
Test name
Test status
Simulation time 283867716 ps
CPU time 1.15 seconds
Started Aug 18 05:31:04 PM PDT 24
Finished Aug 18 05:31:06 PM PDT 24
Peak memory 198532 kb
Host smart-a8d93e1e-5e14-4bfd-9bfb-91dfc18bbaa6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585051101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.2585051101
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.1036939101
Short name T760
Test name
Test status
Simulation time 34756039 ps
CPU time 0.58 seconds
Started Aug 18 05:31:10 PM PDT 24
Finished Aug 18 05:31:11 PM PDT 24
Peak memory 194840 kb
Host smart-e7b38825-8a68-479b-8480-3c75edecfe02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036939101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.1036939101
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.1751300036
Short name T816
Test name
Test status
Simulation time 14797670 ps
CPU time 0.61 seconds
Started Aug 18 05:31:27 PM PDT 24
Finished Aug 18 05:31:27 PM PDT 24
Peak memory 194292 kb
Host smart-bf6253a7-3c3a-4353-aefa-127f88045dba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751300036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.1751300036
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.1418947389
Short name T738
Test name
Test status
Simulation time 13990624 ps
CPU time 0.59 seconds
Started Aug 18 05:31:27 PM PDT 24
Finished Aug 18 05:31:27 PM PDT 24
Peak memory 194896 kb
Host smart-33c5402b-663d-4efd-a0a0-5f095d26a46c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418947389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.1418947389
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.2487205800
Short name T734
Test name
Test status
Simulation time 14068638 ps
CPU time 0.55 seconds
Started Aug 18 05:31:33 PM PDT 24
Finished Aug 18 05:31:33 PM PDT 24
Peak memory 193932 kb
Host smart-caaef938-9f65-45f5-b554-076c0d8a5267
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487205800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.2487205800
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.3341034519
Short name T817
Test name
Test status
Simulation time 12546011 ps
CPU time 0.57 seconds
Started Aug 18 05:31:21 PM PDT 24
Finished Aug 18 05:31:26 PM PDT 24
Peak memory 194580 kb
Host smart-fa28fd9b-9dec-4681-82de-13f3ae3e1f60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341034519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.3341034519
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.724924781
Short name T788
Test name
Test status
Simulation time 17127976 ps
CPU time 0.55 seconds
Started Aug 18 05:31:33 PM PDT 24
Finished Aug 18 05:31:34 PM PDT 24
Peak memory 194600 kb
Host smart-97596635-d385-45f0-bafb-48726e78b1c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724924781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.724924781
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.225789768
Short name T718
Test name
Test status
Simulation time 16273403 ps
CPU time 0.61 seconds
Started Aug 18 05:31:18 PM PDT 24
Finished Aug 18 05:31:18 PM PDT 24
Peak memory 194216 kb
Host smart-6fef4421-c5aa-46d4-8c8c-9ad695c6b0c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225789768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.225789768
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.367486156
Short name T739
Test name
Test status
Simulation time 14336124 ps
CPU time 0.57 seconds
Started Aug 18 05:31:30 PM PDT 24
Finished Aug 18 05:31:31 PM PDT 24
Peak memory 194824 kb
Host smart-14a8aa1c-f475-441b-9d57-a202e894dca0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367486156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.367486156
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.2226428893
Short name T722
Test name
Test status
Simulation time 11457107 ps
CPU time 0.56 seconds
Started Aug 18 05:31:13 PM PDT 24
Finished Aug 18 05:31:14 PM PDT 24
Peak memory 194216 kb
Host smart-3fa32271-dcd1-47cd-bebd-b6fd7d3eecb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226428893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.2226428893
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.2331362658
Short name T830
Test name
Test status
Simulation time 41158705 ps
CPU time 0.57 seconds
Started Aug 18 05:31:23 PM PDT 24
Finished Aug 18 05:31:23 PM PDT 24
Peak memory 194220 kb
Host smart-a91fdb93-7542-40da-90bb-74491ff5979a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331362658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.2331362658
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.1173411015
Short name T814
Test name
Test status
Simulation time 19371709 ps
CPU time 0.99 seconds
Started Aug 18 05:31:02 PM PDT 24
Finished Aug 18 05:31:03 PM PDT 24
Peak memory 198376 kb
Host smart-1d5502fc-7b71-4ac5-a33b-8bc8035fb9e5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173411015 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.1173411015
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.905043860
Short name T826
Test name
Test status
Simulation time 14447625 ps
CPU time 0.6 seconds
Started Aug 18 05:31:03 PM PDT 24
Finished Aug 18 05:31:03 PM PDT 24
Peak memory 195188 kb
Host smart-9b197230-88cd-4c59-8b83-f801f759e0f8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905043860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_
csr_rw.905043860
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.771148044
Short name T802
Test name
Test status
Simulation time 47342715 ps
CPU time 0.56 seconds
Started Aug 18 05:31:02 PM PDT 24
Finished Aug 18 05:31:03 PM PDT 24
Peak memory 195008 kb
Host smart-b1671516-da7f-4183-bcbc-35f00ece5f26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771148044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.771148044
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.3201019675
Short name T827
Test name
Test status
Simulation time 131872528 ps
CPU time 0.68 seconds
Started Aug 18 05:31:01 PM PDT 24
Finished Aug 18 05:31:02 PM PDT 24
Peak memory 196040 kb
Host smart-a2f4caad-101d-4d5d-9c8a-e11957e5ca76
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201019675 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.3201019675
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.1676066610
Short name T735
Test name
Test status
Simulation time 508866994 ps
CPU time 2.08 seconds
Started Aug 18 05:31:00 PM PDT 24
Finished Aug 18 05:31:03 PM PDT 24
Peak memory 198592 kb
Host smart-1127c117-9736-4ddf-9009-c0eed1e432aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676066610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.1676066610
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.1590776219
Short name T50
Test name
Test status
Simulation time 735368127 ps
CPU time 1.42 seconds
Started Aug 18 05:31:05 PM PDT 24
Finished Aug 18 05:31:06 PM PDT 24
Peak memory 198536 kb
Host smart-9342d300-1506-477a-b2ab-b1b67d1b503a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590776219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.1590776219
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.973311739
Short name T753
Test name
Test status
Simulation time 60291364 ps
CPU time 0.77 seconds
Started Aug 18 05:31:04 PM PDT 24
Finished Aug 18 05:31:05 PM PDT 24
Peak memory 198340 kb
Host smart-77b0edd9-090f-41c6-9d6e-df468c554e0d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973311739 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.973311739
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.35998310
Short name T78
Test name
Test status
Simulation time 14312580 ps
CPU time 0.58 seconds
Started Aug 18 05:31:10 PM PDT 24
Finished Aug 18 05:31:11 PM PDT 24
Peak memory 193776 kb
Host smart-b366eccb-39f1-43a7-83c4-21a582469941
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35998310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SE
Q=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_c
sr_rw.35998310
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.2757875380
Short name T778
Test name
Test status
Simulation time 18526473 ps
CPU time 0.65 seconds
Started Aug 18 05:31:01 PM PDT 24
Finished Aug 18 05:31:02 PM PDT 24
Peak memory 194920 kb
Host smart-468fff6f-7db2-4d14-84ed-c5432d21d2a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757875380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.2757875380
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.3122477228
Short name T801
Test name
Test status
Simulation time 96008052 ps
CPU time 0.74 seconds
Started Aug 18 05:31:03 PM PDT 24
Finished Aug 18 05:31:04 PM PDT 24
Peak memory 196276 kb
Host smart-4ecf9a00-b5c8-4f09-a2f0-6cb95e5b858e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122477228 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.gpio_same_csr_outstanding.3122477228
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.1534152482
Short name T724
Test name
Test status
Simulation time 61240403 ps
CPU time 2.8 seconds
Started Aug 18 05:31:07 PM PDT 24
Finished Aug 18 05:31:09 PM PDT 24
Peak memory 198420 kb
Host smart-b96c613e-de8f-494f-a918-4363258b2ac2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534152482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.1534152482
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.679479520
Short name T831
Test name
Test status
Simulation time 22122665 ps
CPU time 0.73 seconds
Started Aug 18 05:31:04 PM PDT 24
Finished Aug 18 05:31:05 PM PDT 24
Peak memory 198352 kb
Host smart-4e6456e6-47af-4dbc-8749-87355c451ad2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679479520 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.679479520
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.2047857864
Short name T97
Test name
Test status
Simulation time 22405723 ps
CPU time 0.66 seconds
Started Aug 18 05:31:03 PM PDT 24
Finished Aug 18 05:31:04 PM PDT 24
Peak memory 194672 kb
Host smart-4b73ad68-aaa8-4736-b24f-29eee6a63f2d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047857864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.2047857864
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.1531552220
Short name T749
Test name
Test status
Simulation time 16666666 ps
CPU time 0.63 seconds
Started Aug 18 05:31:02 PM PDT 24
Finished Aug 18 05:31:03 PM PDT 24
Peak memory 194232 kb
Host smart-be71b16b-685d-4b61-ad35-c60b97eb7db0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531552220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.1531552220
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.889477952
Short name T84
Test name
Test status
Simulation time 58020779 ps
CPU time 0.77 seconds
Started Aug 18 05:31:05 PM PDT 24
Finished Aug 18 05:31:06 PM PDT 24
Peak memory 196624 kb
Host smart-872791e9-5aca-4b76-936e-61731ac6b0ba
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889477952 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 7.gpio_same_csr_outstanding.889477952
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.1185341383
Short name T795
Test name
Test status
Simulation time 133034658 ps
CPU time 1.89 seconds
Started Aug 18 05:31:12 PM PDT 24
Finished Aug 18 05:31:14 PM PDT 24
Peak memory 198592 kb
Host smart-30d584fd-60fe-41a6-85ac-680e05a77baa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185341383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.1185341383
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.1681458224
Short name T44
Test name
Test status
Simulation time 968713696 ps
CPU time 1.38 seconds
Started Aug 18 05:31:10 PM PDT 24
Finished Aug 18 05:31:12 PM PDT 24
Peak memory 198528 kb
Host smart-7bfda683-2187-4897-81f1-6d1626fd5a54
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681458224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.1681458224
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.2466628211
Short name T833
Test name
Test status
Simulation time 21474841 ps
CPU time 0.7 seconds
Started Aug 18 05:31:01 PM PDT 24
Finished Aug 18 05:31:01 PM PDT 24
Peak memory 198168 kb
Host smart-f600f245-ae68-4e10-814b-2c6b306a7c33
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466628211 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.2466628211
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.3475291478
Short name T775
Test name
Test status
Simulation time 10674780 ps
CPU time 0.56 seconds
Started Aug 18 05:31:03 PM PDT 24
Finished Aug 18 05:31:04 PM PDT 24
Peak memory 194400 kb
Host smart-9ac4ac85-3967-4905-88e7-f3e2b817dee5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475291478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.3475291478
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.3075950442
Short name T774
Test name
Test status
Simulation time 40838166 ps
CPU time 0.57 seconds
Started Aug 18 05:31:11 PM PDT 24
Finished Aug 18 05:31:12 PM PDT 24
Peak memory 194232 kb
Host smart-dc9c04ff-914a-4544-93de-dc4fea16dfef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075950442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.3075950442
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.2455106948
Short name T821
Test name
Test status
Simulation time 25479447 ps
CPU time 0.74 seconds
Started Aug 18 05:31:18 PM PDT 24
Finished Aug 18 05:31:19 PM PDT 24
Peak memory 197032 kb
Host smart-3f0426dd-f79d-4dbf-b0b8-9eff2454c5b6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455106948 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.2455106948
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.1394961303
Short name T811
Test name
Test status
Simulation time 149968602 ps
CPU time 2.01 seconds
Started Aug 18 05:31:04 PM PDT 24
Finished Aug 18 05:31:06 PM PDT 24
Peak memory 198588 kb
Host smart-fade7f96-fb28-41e8-abf7-63d44943bcef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394961303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.1394961303
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.2861168865
Short name T756
Test name
Test status
Simulation time 284403059 ps
CPU time 1.03 seconds
Started Aug 18 05:31:05 PM PDT 24
Finished Aug 18 05:31:06 PM PDT 24
Peak memory 198556 kb
Host smart-e94f2c8c-85fb-4c1c-9c6a-d5ff02e904cf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861168865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.2861168865
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.3076210546
Short name T832
Test name
Test status
Simulation time 72291403 ps
CPU time 1.07 seconds
Started Aug 18 05:31:01 PM PDT 24
Finished Aug 18 05:31:03 PM PDT 24
Peak memory 198416 kb
Host smart-4c7b5b13-bc96-4dc4-b5c9-5b53d6312c48
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076210546 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.3076210546
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.1244126356
Short name T825
Test name
Test status
Simulation time 24609247 ps
CPU time 0.59 seconds
Started Aug 18 05:31:23 PM PDT 24
Finished Aug 18 05:31:24 PM PDT 24
Peak memory 195940 kb
Host smart-87665549-eee6-4c87-b896-d8b7292c1864
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244126356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.1244126356
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.708006780
Short name T809
Test name
Test status
Simulation time 50721790 ps
CPU time 0.63 seconds
Started Aug 18 05:31:02 PM PDT 24
Finished Aug 18 05:31:02 PM PDT 24
Peak memory 194904 kb
Host smart-49ac6a5e-befa-43f0-8aa1-3c8d9840d24b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708006780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.708006780
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.119460946
Short name T101
Test name
Test status
Simulation time 19567868 ps
CPU time 0.79 seconds
Started Aug 18 05:31:05 PM PDT 24
Finished Aug 18 05:31:06 PM PDT 24
Peak memory 197360 kb
Host smart-20cc89ff-12cf-4dfa-9bd9-b28d1ea2eb2e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119460946 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 9.gpio_same_csr_outstanding.119460946
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.547842424
Short name T750
Test name
Test status
Simulation time 168112592 ps
CPU time 2.24 seconds
Started Aug 18 05:31:03 PM PDT 24
Finished Aug 18 05:31:06 PM PDT 24
Peak memory 198568 kb
Host smart-09076c7c-05ae-4a08-b1d8-1ca652da7294
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547842424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.547842424
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.1229271541
Short name T34
Test name
Test status
Simulation time 45331710 ps
CPU time 0.87 seconds
Started Aug 18 05:31:05 PM PDT 24
Finished Aug 18 05:31:06 PM PDT 24
Peak memory 197564 kb
Host smart-1a162f32-f6fe-4dc7-8557-aaf8b26cd1cf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229271541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.1229271541
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.1220160531
Short name T555
Test name
Test status
Simulation time 120739301 ps
CPU time 0.57 seconds
Started Aug 18 05:40:28 PM PDT 24
Finished Aug 18 05:40:31 PM PDT 24
Peak memory 194276 kb
Host smart-6858ae3c-594b-47f3-a9e5-84d57a4caedc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220160531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.1220160531
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.2552382503
Short name T479
Test name
Test status
Simulation time 37073732 ps
CPU time 0.86 seconds
Started Aug 18 05:40:11 PM PDT 24
Finished Aug 18 05:40:12 PM PDT 24
Peak memory 195456 kb
Host smart-3a6d7541-aca7-4702-a9f5-9cb8053d5691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552382503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.2552382503
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.2909091251
Short name T684
Test name
Test status
Simulation time 2320849564 ps
CPU time 18.03 seconds
Started Aug 18 05:40:20 PM PDT 24
Finished Aug 18 05:40:39 PM PDT 24
Peak memory 198232 kb
Host smart-570c69f8-3c8c-4bee-aca1-823ea56e2021
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909091251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.2909091251
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.1913182566
Short name T492
Test name
Test status
Simulation time 155506698 ps
CPU time 0.94 seconds
Started Aug 18 05:40:23 PM PDT 24
Finished Aug 18 05:40:24 PM PDT 24
Peak memory 197924 kb
Host smart-931df711-1349-48be-9202-820303dcace3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913182566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.1913182566
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.3861716046
Short name T400
Test name
Test status
Simulation time 60645791 ps
CPU time 0.71 seconds
Started Aug 18 05:40:26 PM PDT 24
Finished Aug 18 05:40:27 PM PDT 24
Peak memory 194504 kb
Host smart-e5bf78bb-cfce-4839-ac3d-02b565dc7772
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861716046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.3861716046
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.1994180229
Short name T686
Test name
Test status
Simulation time 354706166 ps
CPU time 3.53 seconds
Started Aug 18 05:40:22 PM PDT 24
Finished Aug 18 05:40:26 PM PDT 24
Peak memory 198308 kb
Host smart-c1dccd93-1ddb-475f-88ba-c6f1e8588ef1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994180229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.1994180229
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.1100161211
Short name T309
Test name
Test status
Simulation time 57439470 ps
CPU time 1.63 seconds
Started Aug 18 05:40:29 PM PDT 24
Finished Aug 18 05:40:32 PM PDT 24
Peak memory 195920 kb
Host smart-8526c935-d54c-4be4-aa5a-016e7508ef0e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100161211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
1100161211
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.960761592
Short name T642
Test name
Test status
Simulation time 290333536 ps
CPU time 1.29 seconds
Started Aug 18 05:40:26 PM PDT 24
Finished Aug 18 05:40:27 PM PDT 24
Peak memory 197124 kb
Host smart-191c4f94-0cfb-4b3b-baa3-fbe2c80749df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960761592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.960761592
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.3262249729
Short name T206
Test name
Test status
Simulation time 27005512 ps
CPU time 1.02 seconds
Started Aug 18 05:40:12 PM PDT 24
Finished Aug 18 05:40:13 PM PDT 24
Peak memory 195976 kb
Host smart-31e66735-b3c7-40e7-837b-81543828a712
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262249729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.3262249729
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.2264556647
Short name T487
Test name
Test status
Simulation time 55010821 ps
CPU time 2.23 seconds
Started Aug 18 05:40:26 PM PDT 24
Finished Aug 18 05:40:29 PM PDT 24
Peak memory 198172 kb
Host smart-fa34cb5a-5993-4de3-baf9-5a850cdc3df9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264556647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.2264556647
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_smoke.3570515170
Short name T436
Test name
Test status
Simulation time 43875420 ps
CPU time 1.22 seconds
Started Aug 18 05:40:33 PM PDT 24
Finished Aug 18 05:40:35 PM PDT 24
Peak memory 195700 kb
Host smart-ffb7174b-645b-4000-a42b-18a4bf1afc7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570515170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.3570515170
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.2267494215
Short name T588
Test name
Test status
Simulation time 41215784 ps
CPU time 1.1 seconds
Started Aug 18 05:40:30 PM PDT 24
Finished Aug 18 05:40:31 PM PDT 24
Peak memory 195948 kb
Host smart-83aa8a3a-a57b-4af0-89e4-284eda2265fe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267494215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.2267494215
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.727494850
Short name T410
Test name
Test status
Simulation time 3862970578 ps
CPU time 97.04 seconds
Started Aug 18 05:40:22 PM PDT 24
Finished Aug 18 05:42:00 PM PDT 24
Peak memory 198508 kb
Host smart-08889d64-8daf-4025-8b0d-9d16cac0381b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727494850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gp
io_stress_all.727494850
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_alert_test.3241576614
Short name T559
Test name
Test status
Simulation time 12596699 ps
CPU time 0.58 seconds
Started Aug 18 05:40:24 PM PDT 24
Finished Aug 18 05:40:25 PM PDT 24
Peak memory 193968 kb
Host smart-f3387ba5-93d5-4206-b439-1764b1c240f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241576614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.3241576614
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.833258905
Short name T257
Test name
Test status
Simulation time 49106133 ps
CPU time 0.74 seconds
Started Aug 18 05:40:21 PM PDT 24
Finished Aug 18 05:40:21 PM PDT 24
Peak memory 196060 kb
Host smart-6de57496-ea65-440c-b22e-40389e924c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833258905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.833258905
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.4268847838
Short name T519
Test name
Test status
Simulation time 831194505 ps
CPU time 10.68 seconds
Started Aug 18 05:40:28 PM PDT 24
Finished Aug 18 05:40:39 PM PDT 24
Peak memory 196840 kb
Host smart-ecab2cde-525d-4f20-8e8e-51bf374b580d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268847838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.4268847838
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.2113992566
Short name T717
Test name
Test status
Simulation time 117347003 ps
CPU time 0.93 seconds
Started Aug 18 05:39:58 PM PDT 24
Finished Aug 18 05:39:59 PM PDT 24
Peak memory 197804 kb
Host smart-8ef0ed00-4970-48c8-9014-a3e999202978
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113992566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.2113992566
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.2017331664
Short name T287
Test name
Test status
Simulation time 120152626 ps
CPU time 1.48 seconds
Started Aug 18 05:40:25 PM PDT 24
Finished Aug 18 05:40:27 PM PDT 24
Peak memory 197156 kb
Host smart-b336aa30-bbb5-4e03-803a-51cd3025a266
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017331664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.2017331664
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.1932120469
Short name T165
Test name
Test status
Simulation time 97484646 ps
CPU time 1.02 seconds
Started Aug 18 05:40:48 PM PDT 24
Finished Aug 18 05:40:49 PM PDT 24
Peak memory 197396 kb
Host smart-64609985-89e5-446a-914e-ea57cda43578
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932120469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.1932120469
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.1832557309
Short name T339
Test name
Test status
Simulation time 125538835 ps
CPU time 2.34 seconds
Started Aug 18 05:40:19 PM PDT 24
Finished Aug 18 05:40:22 PM PDT 24
Peak memory 195976 kb
Host smart-79043ae1-c471-4fd8-9422-a30878789013
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832557309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
1832557309
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.1088779389
Short name T118
Test name
Test status
Simulation time 70715820 ps
CPU time 1.25 seconds
Started Aug 18 05:40:29 PM PDT 24
Finished Aug 18 05:40:30 PM PDT 24
Peak memory 197108 kb
Host smart-fd2d6532-e64f-4f83-8f22-4d3bef6db931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088779389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.1088779389
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.4139523679
Short name T398
Test name
Test status
Simulation time 73208570 ps
CPU time 1.27 seconds
Started Aug 18 05:40:28 PM PDT 24
Finished Aug 18 05:40:29 PM PDT 24
Peak memory 198208 kb
Host smart-5042e6a9-1535-4be2-b5ef-6713522c21e8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139523679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.4139523679
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.980422132
Short name T714
Test name
Test status
Simulation time 262335511 ps
CPU time 1.36 seconds
Started Aug 18 05:40:30 PM PDT 24
Finished Aug 18 05:40:31 PM PDT 24
Peak memory 198092 kb
Host smart-103634dc-2bff-4ca3-8f19-16fb3214d007
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980422132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand
om_long_reg_writes_reg_reads.980422132
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.3984736703
Short name T51
Test name
Test status
Simulation time 324155486 ps
CPU time 0.86 seconds
Started Aug 18 05:40:22 PM PDT 24
Finished Aug 18 05:40:23 PM PDT 24
Peak memory 213924 kb
Host smart-4c69f0dc-8c49-4657-bfa8-ff43aad674c7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984736703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.3984736703
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.566697661
Short name T17
Test name
Test status
Simulation time 83663346 ps
CPU time 1.5 seconds
Started Aug 18 05:40:23 PM PDT 24
Finished Aug 18 05:40:25 PM PDT 24
Peak memory 197132 kb
Host smart-e5da265d-638d-4c7d-a06f-c3237175cdfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566697661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.566697661
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.1220240740
Short name T233
Test name
Test status
Simulation time 91434781 ps
CPU time 0.87 seconds
Started Aug 18 05:40:27 PM PDT 24
Finished Aug 18 05:40:28 PM PDT 24
Peak memory 195344 kb
Host smart-8879323d-4caa-4fdd-a0dc-3d180d58c44f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220240740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.1220240740
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.2502290019
Short name T428
Test name
Test status
Simulation time 5619903688 ps
CPU time 59.12 seconds
Started Aug 18 05:40:19 PM PDT 24
Finished Aug 18 05:41:18 PM PDT 24
Peak memory 198232 kb
Host smart-9d5413fd-06dc-422e-bc62-0b5141de4ca5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502290019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g
pio_stress_all.2502290019
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_stress_all_with_rand_reset.4065932457
Short name T62
Test name
Test status
Simulation time 9083322718 ps
CPU time 81.06 seconds
Started Aug 18 05:40:01 PM PDT 24
Finished Aug 18 05:41:22 PM PDT 24
Peak memory 198540 kb
Host smart-c9c31fb1-9914-43fe-9ac2-6a1ebf38cecd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4065932457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_stress_all_with_rand_reset.4065932457
Directory /workspace/1.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.gpio_alert_test.2861089679
Short name T516
Test name
Test status
Simulation time 10451553 ps
CPU time 0.53 seconds
Started Aug 18 05:40:51 PM PDT 24
Finished Aug 18 05:40:51 PM PDT 24
Peak memory 194052 kb
Host smart-743950d4-acee-49fd-998c-cacd837befdf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861089679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.2861089679
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.810897850
Short name T417
Test name
Test status
Simulation time 130050753 ps
CPU time 0.75 seconds
Started Aug 18 05:40:44 PM PDT 24
Finished Aug 18 05:40:45 PM PDT 24
Peak memory 195464 kb
Host smart-443fee6b-afb3-458e-ad0e-2ad8e2605812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810897850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.810897850
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.91362597
Short name T152
Test name
Test status
Simulation time 142801787 ps
CPU time 7.2 seconds
Started Aug 18 05:40:38 PM PDT 24
Finished Aug 18 05:40:46 PM PDT 24
Peak memory 198176 kb
Host smart-30b49149-abc6-473d-a898-7a33cb99f035
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91362597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stress
.91362597
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.803502070
Short name T522
Test name
Test status
Simulation time 65883801 ps
CPU time 0.94 seconds
Started Aug 18 05:40:52 PM PDT 24
Finished Aug 18 05:40:53 PM PDT 24
Peak memory 196496 kb
Host smart-fbba7509-9db1-4f0b-a84b-ecdd9d0e54d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803502070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.803502070
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.3129492114
Short name T133
Test name
Test status
Simulation time 141708279 ps
CPU time 0.85 seconds
Started Aug 18 05:40:57 PM PDT 24
Finished Aug 18 05:40:58 PM PDT 24
Peak memory 196776 kb
Host smart-185af1c4-f75f-4f3b-8f63-ad502945240e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129492114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.3129492114
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.858861749
Short name T318
Test name
Test status
Simulation time 212407008 ps
CPU time 1.75 seconds
Started Aug 18 05:40:41 PM PDT 24
Finished Aug 18 05:40:43 PM PDT 24
Peak memory 198180 kb
Host smart-1fc2e351-d658-4308-8ec9-81bf2eed6064
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858861749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 10.gpio_intr_with_filter_rand_intr_event.858861749
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.2884194800
Short name T283
Test name
Test status
Simulation time 113750268 ps
CPU time 2.28 seconds
Started Aug 18 05:40:36 PM PDT 24
Finished Aug 18 05:40:38 PM PDT 24
Peak memory 196920 kb
Host smart-85640a59-5a78-41bf-a730-729a1c37e846
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884194800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.2884194800
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.2569260468
Short name T456
Test name
Test status
Simulation time 39500796 ps
CPU time 1.24 seconds
Started Aug 18 05:40:35 PM PDT 24
Finished Aug 18 05:40:37 PM PDT 24
Peak memory 196996 kb
Host smart-7e2a6bed-c2b0-48a8-a49a-89708b119ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569260468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.2569260468
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.2288680470
Short name T288
Test name
Test status
Simulation time 21959665 ps
CPU time 0.89 seconds
Started Aug 18 05:40:59 PM PDT 24
Finished Aug 18 05:41:05 PM PDT 24
Peak memory 196852 kb
Host smart-e75578a6-c137-4201-a331-6735989f0a85
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288680470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.2288680470
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.3074995940
Short name T463
Test name
Test status
Simulation time 198768725 ps
CPU time 2.32 seconds
Started Aug 18 05:40:52 PM PDT 24
Finished Aug 18 05:40:55 PM PDT 24
Peak memory 198148 kb
Host smart-75b5a90b-a705-4b81-86c5-3ae650f16d4f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074995940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.3074995940
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.1571766336
Short name T116
Test name
Test status
Simulation time 168970013 ps
CPU time 1.14 seconds
Started Aug 18 05:40:32 PM PDT 24
Finished Aug 18 05:40:33 PM PDT 24
Peak memory 196944 kb
Host smart-003ae84f-557d-4917-82d6-7f3237f79abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571766336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.1571766336
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.895907697
Short name T304
Test name
Test status
Simulation time 82770131 ps
CPU time 0.89 seconds
Started Aug 18 05:40:49 PM PDT 24
Finished Aug 18 05:40:50 PM PDT 24
Peak memory 196124 kb
Host smart-57126691-164b-4869-beaa-6ae0a2deef13
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895907697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.895907697
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.346256146
Short name T613
Test name
Test status
Simulation time 2120187996 ps
CPU time 52.98 seconds
Started Aug 18 05:40:45 PM PDT 24
Finished Aug 18 05:41:38 PM PDT 24
Peak memory 198232 kb
Host smart-779810b9-27e0-44df-92a1-7ec322cd9b8b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346256146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.g
pio_stress_all.346256146
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_alert_test.4111249513
Short name T332
Test name
Test status
Simulation time 55249243 ps
CPU time 0.6 seconds
Started Aug 18 05:40:47 PM PDT 24
Finished Aug 18 05:40:48 PM PDT 24
Peak memory 192852 kb
Host smart-42a2f35f-2f81-4f2e-8774-4750105aa40e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111249513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.4111249513
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.1571674526
Short name T546
Test name
Test status
Simulation time 25598297 ps
CPU time 0.63 seconds
Started Aug 18 05:40:44 PM PDT 24
Finished Aug 18 05:40:45 PM PDT 24
Peak memory 194184 kb
Host smart-795deed9-402f-48b9-8ee6-a7a70e0c5198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571674526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.1571674526
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.488617324
Short name T579
Test name
Test status
Simulation time 514860091 ps
CPU time 16.79 seconds
Started Aug 18 05:40:45 PM PDT 24
Finished Aug 18 05:41:02 PM PDT 24
Peak memory 196908 kb
Host smart-03c526b9-bbcc-4f88-b926-d94c5eb6e769
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488617324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stres
s.488617324
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.372456980
Short name T680
Test name
Test status
Simulation time 761486464 ps
CPU time 0.99 seconds
Started Aug 18 05:41:15 PM PDT 24
Finished Aug 18 05:41:16 PM PDT 24
Peak memory 196632 kb
Host smart-542ef9ac-7753-4825-9262-71127b731db1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372456980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.372456980
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.447961794
Short name T327
Test name
Test status
Simulation time 50911548 ps
CPU time 1.01 seconds
Started Aug 18 05:41:00 PM PDT 24
Finished Aug 18 05:41:01 PM PDT 24
Peak memory 197036 kb
Host smart-fdf68249-4378-4ea3-bd41-f88cf02f0235
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447961794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.447961794
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.1738935556
Short name T594
Test name
Test status
Simulation time 262302984 ps
CPU time 2.6 seconds
Started Aug 18 05:41:09 PM PDT 24
Finished Aug 18 05:41:12 PM PDT 24
Peak memory 198184 kb
Host smart-5dd6aedb-635d-46c2-a430-a7f833a74a1d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738935556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.1738935556
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.2470352014
Short name T461
Test name
Test status
Simulation time 200443362 ps
CPU time 2.97 seconds
Started Aug 18 05:40:48 PM PDT 24
Finished Aug 18 05:40:51 PM PDT 24
Peak memory 197260 kb
Host smart-6f215948-f19f-41d5-868e-6187f87bd609
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470352014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.2470352014
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.2734242676
Short name T697
Test name
Test status
Simulation time 65474947 ps
CPU time 1.21 seconds
Started Aug 18 05:40:47 PM PDT 24
Finished Aug 18 05:40:49 PM PDT 24
Peak memory 195984 kb
Host smart-a4762ee3-201d-49fc-b028-a5e1b3bb1fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734242676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.2734242676
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.426677699
Short name T670
Test name
Test status
Simulation time 68528587 ps
CPU time 1.29 seconds
Started Aug 18 05:40:54 PM PDT 24
Finished Aug 18 05:40:56 PM PDT 24
Peak memory 196620 kb
Host smart-70926a86-600e-4f86-857d-0c39e1e4ae32
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426677699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullup
_pulldown.426677699
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.404940178
Short name T337
Test name
Test status
Simulation time 90879862 ps
CPU time 1.37 seconds
Started Aug 18 05:40:33 PM PDT 24
Finished Aug 18 05:40:35 PM PDT 24
Peak memory 198096 kb
Host smart-0212e68e-1dff-4c63-a9e1-7558dcdf4a94
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404940178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ran
dom_long_reg_writes_reg_reads.404940178
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.706416901
Short name T704
Test name
Test status
Simulation time 352743082 ps
CPU time 1.38 seconds
Started Aug 18 05:40:38 PM PDT 24
Finished Aug 18 05:40:40 PM PDT 24
Peak memory 195648 kb
Host smart-9db9a22e-df01-4851-a46b-e878181d79fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706416901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.706416901
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.1018884831
Short name T635
Test name
Test status
Simulation time 45633621 ps
CPU time 1.04 seconds
Started Aug 18 05:40:44 PM PDT 24
Finished Aug 18 05:40:45 PM PDT 24
Peak memory 195880 kb
Host smart-30f12792-afc5-4bae-bc89-61bd7efb7fa8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018884831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.1018884831
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.1556781774
Short name T362
Test name
Test status
Simulation time 3145186816 ps
CPU time 28.75 seconds
Started Aug 18 05:40:36 PM PDT 24
Finished Aug 18 05:41:05 PM PDT 24
Peak memory 198376 kb
Host smart-6dd7bd2b-990b-4fc4-8027-1cc6d986bf2a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556781774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.1556781774
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_stress_all_with_rand_reset.186478248
Short name T533
Test name
Test status
Simulation time 13146419115 ps
CPU time 110.9 seconds
Started Aug 18 05:40:46 PM PDT 24
Finished Aug 18 05:42:37 PM PDT 24
Peak memory 198532 kb
Host smart-59cf6906-2e14-4189-81c3-02b539fc2721
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=186478248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_stress_all_with_rand_reset.186478248
Directory /workspace/11.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.gpio_alert_test.2496907320
Short name T342
Test name
Test status
Simulation time 11728117 ps
CPU time 0.55 seconds
Started Aug 18 05:40:30 PM PDT 24
Finished Aug 18 05:40:31 PM PDT 24
Peak memory 194256 kb
Host smart-8c20ef89-7955-4f96-bc3d-cb1cedcf21f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496907320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.2496907320
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.2581397149
Short name T647
Test name
Test status
Simulation time 80794369 ps
CPU time 0.71 seconds
Started Aug 18 05:40:48 PM PDT 24
Finished Aug 18 05:40:54 PM PDT 24
Peak memory 195348 kb
Host smart-b22d757f-134e-4fc6-9e03-14863732a2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581397149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.2581397149
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.469843360
Short name T286
Test name
Test status
Simulation time 955407916 ps
CPU time 11.57 seconds
Started Aug 18 05:40:29 PM PDT 24
Finished Aug 18 05:40:41 PM PDT 24
Peak memory 197184 kb
Host smart-428961f0-9e3b-42f9-bac8-4f4ea09e4cf2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469843360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stres
s.469843360
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.2137865129
Short name T455
Test name
Test status
Simulation time 179408597 ps
CPU time 0.86 seconds
Started Aug 18 05:40:53 PM PDT 24
Finished Aug 18 05:40:58 PM PDT 24
Peak memory 196184 kb
Host smart-fd78c902-7771-44b5-9d44-b7e30f3fec57
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137865129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.2137865129
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.869379068
Short name T225
Test name
Test status
Simulation time 112464601 ps
CPU time 0.93 seconds
Started Aug 18 05:40:46 PM PDT 24
Finished Aug 18 05:40:47 PM PDT 24
Peak memory 196232 kb
Host smart-b2da6978-e059-4eee-9543-b71f4c38b78a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869379068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.869379068
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.3439089425
Short name T631
Test name
Test status
Simulation time 634892152 ps
CPU time 3.05 seconds
Started Aug 18 05:40:52 PM PDT 24
Finished Aug 18 05:40:55 PM PDT 24
Peak memory 197948 kb
Host smart-c85ccbeb-7331-4346-840a-9af181e64ae5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439089425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.3439089425
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.1988874144
Short name T390
Test name
Test status
Simulation time 97353943 ps
CPU time 2.91 seconds
Started Aug 18 05:40:45 PM PDT 24
Finished Aug 18 05:40:48 PM PDT 24
Peak memory 198160 kb
Host smart-b7a320b9-d9e4-4291-85d8-917800bc3c34
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988874144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.1988874144
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.4094577919
Short name T557
Test name
Test status
Simulation time 70747226 ps
CPU time 1.21 seconds
Started Aug 18 05:40:44 PM PDT 24
Finished Aug 18 05:40:45 PM PDT 24
Peak memory 197216 kb
Host smart-6db7df30-a000-4e3d-9f0d-36c21ab77a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094577919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.4094577919
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.3473407009
Short name T324
Test name
Test status
Simulation time 71772279 ps
CPU time 0.95 seconds
Started Aug 18 05:40:33 PM PDT 24
Finished Aug 18 05:40:34 PM PDT 24
Peak memory 196136 kb
Host smart-269cd7c7-0c68-44ea-8c7b-94dabaa8a0b3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473407009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.3473407009
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.824231800
Short name T124
Test name
Test status
Simulation time 160066834 ps
CPU time 3.69 seconds
Started Aug 18 05:40:39 PM PDT 24
Finished Aug 18 05:40:42 PM PDT 24
Peak memory 198148 kb
Host smart-f3ebf920-a72b-4bd4-bfc5-1e0c8c00a2e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824231800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ran
dom_long_reg_writes_reg_reads.824231800
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.1748939841
Short name T174
Test name
Test status
Simulation time 178228074 ps
CPU time 1.37 seconds
Started Aug 18 05:40:40 PM PDT 24
Finished Aug 18 05:40:42 PM PDT 24
Peak memory 197064 kb
Host smart-c6b24906-704d-479a-9c42-9b55fa6d212c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748939841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.1748939841
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.3693576064
Short name T508
Test name
Test status
Simulation time 156994258 ps
CPU time 1.14 seconds
Started Aug 18 05:40:46 PM PDT 24
Finished Aug 18 05:40:47 PM PDT 24
Peak memory 196000 kb
Host smart-a904af04-617c-40b8-abe9-ad6ac9b7f203
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693576064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.3693576064
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.737506318
Short name T643
Test name
Test status
Simulation time 19423842049 ps
CPU time 77.54 seconds
Started Aug 18 05:40:47 PM PDT 24
Finished Aug 18 05:42:05 PM PDT 24
Peak memory 191896 kb
Host smart-25462b78-4762-4b7f-9c53-d9d44742604a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737506318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.g
pio_stress_all.737506318
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_alert_test.4128270814
Short name T351
Test name
Test status
Simulation time 10935970 ps
CPU time 0.55 seconds
Started Aug 18 05:40:45 PM PDT 24
Finished Aug 18 05:40:45 PM PDT 24
Peak memory 194064 kb
Host smart-169c5c87-4c81-4e06-a8d0-e76cb4b55279
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128270814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.4128270814
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.3515717634
Short name T138
Test name
Test status
Simulation time 20611706 ps
CPU time 0.69 seconds
Started Aug 18 05:40:48 PM PDT 24
Finished Aug 18 05:40:49 PM PDT 24
Peak memory 195436 kb
Host smart-2b46cf21-ce7b-433e-9104-a71d71c36694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515717634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.3515717634
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.850002475
Short name T489
Test name
Test status
Simulation time 102876718 ps
CPU time 5.47 seconds
Started Aug 18 05:40:43 PM PDT 24
Finished Aug 18 05:40:48 PM PDT 24
Peak memory 197296 kb
Host smart-b85ccf79-ebbb-4f90-bf5c-6909db0cba34
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850002475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stres
s.850002475
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.1597357257
Short name T503
Test name
Test status
Simulation time 75629017 ps
CPU time 0.78 seconds
Started Aug 18 05:40:46 PM PDT 24
Finished Aug 18 05:40:47 PM PDT 24
Peak memory 195452 kb
Host smart-ce44868f-7113-4709-bec5-17e935a2486b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597357257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.1597357257
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.624962692
Short name T689
Test name
Test status
Simulation time 76938315 ps
CPU time 0.86 seconds
Started Aug 18 05:40:51 PM PDT 24
Finished Aug 18 05:40:52 PM PDT 24
Peak memory 195640 kb
Host smart-4362090f-672e-4467-ae78-98cca8e6edbd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624962692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.624962692
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.2371200496
Short name T379
Test name
Test status
Simulation time 82105809 ps
CPU time 1.67 seconds
Started Aug 18 05:40:44 PM PDT 24
Finished Aug 18 05:40:46 PM PDT 24
Peak memory 196712 kb
Host smart-4b0daa70-eb74-4c12-a0eb-d37f7b02c1d2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371200496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.2371200496
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.3396783213
Short name T633
Test name
Test status
Simulation time 50039667 ps
CPU time 1.03 seconds
Started Aug 18 05:40:36 PM PDT 24
Finished Aug 18 05:40:37 PM PDT 24
Peak memory 196476 kb
Host smart-aac88033-8637-4249-a255-78ef05853f5c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396783213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.3396783213
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.984129592
Short name T419
Test name
Test status
Simulation time 191188300 ps
CPU time 1.14 seconds
Started Aug 18 05:40:36 PM PDT 24
Finished Aug 18 05:40:38 PM PDT 24
Peak memory 195968 kb
Host smart-238decca-f8ba-48c9-ad24-9678cfd78cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984129592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.984129592
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.1671183121
Short name T518
Test name
Test status
Simulation time 74575709 ps
CPU time 0.85 seconds
Started Aug 18 05:40:50 PM PDT 24
Finished Aug 18 05:40:51 PM PDT 24
Peak memory 196680 kb
Host smart-10a6fc29-ca82-4ded-bdea-47b3b83474f8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671183121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.1671183121
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.4009679404
Short name T607
Test name
Test status
Simulation time 639614100 ps
CPU time 1.92 seconds
Started Aug 18 05:40:41 PM PDT 24
Finished Aug 18 05:40:43 PM PDT 24
Peak memory 198128 kb
Host smart-87aaec8c-e62f-4910-a1c0-a454def17bd3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009679404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.4009679404
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.2488769272
Short name T491
Test name
Test status
Simulation time 126588891 ps
CPU time 1.35 seconds
Started Aug 18 05:40:36 PM PDT 24
Finished Aug 18 05:40:37 PM PDT 24
Peak memory 197004 kb
Host smart-b5c10cc7-9449-43bd-a5eb-706a1fce4d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488769272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.2488769272
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.484687135
Short name T477
Test name
Test status
Simulation time 73449099 ps
CPU time 1.07 seconds
Started Aug 18 05:40:53 PM PDT 24
Finished Aug 18 05:40:54 PM PDT 24
Peak memory 195812 kb
Host smart-67fd373e-9880-47ff-8ce1-047002ec98c3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484687135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.484687135
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.2377804646
Short name T667
Test name
Test status
Simulation time 18792322291 ps
CPU time 129.82 seconds
Started Aug 18 05:40:44 PM PDT 24
Finished Aug 18 05:42:54 PM PDT 24
Peak memory 198264 kb
Host smart-ea0490ee-065b-4679-9f62-851716f464a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377804646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.2377804646
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_stress_all_with_rand_reset.2059263886
Short name T65
Test name
Test status
Simulation time 4310872281 ps
CPU time 125.4 seconds
Started Aug 18 05:40:51 PM PDT 24
Finished Aug 18 05:43:01 PM PDT 24
Peak memory 198564 kb
Host smart-af5aa0fe-43b7-463e-a3d2-883d55e005c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2059263886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_stress_all_with_rand_reset.2059263886
Directory /workspace/13.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.gpio_alert_test.1952977731
Short name T218
Test name
Test status
Simulation time 12350922 ps
CPU time 0.59 seconds
Started Aug 18 05:40:35 PM PDT 24
Finished Aug 18 05:40:36 PM PDT 24
Peak memory 194988 kb
Host smart-0b3643ad-3195-46d0-b6a0-659e25ee36e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952977731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.1952977731
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.4029142808
Short name T119
Test name
Test status
Simulation time 91290585 ps
CPU time 0.68 seconds
Started Aug 18 05:40:44 PM PDT 24
Finished Aug 18 05:40:44 PM PDT 24
Peak memory 194324 kb
Host smart-fa5d3ca2-5c0b-4c84-89af-0ec616384399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029142808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.4029142808
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.2047207279
Short name T474
Test name
Test status
Simulation time 416830460 ps
CPU time 11.3 seconds
Started Aug 18 05:40:51 PM PDT 24
Finished Aug 18 05:41:03 PM PDT 24
Peak memory 195616 kb
Host smart-6a10e49e-e774-4500-bfbb-8958bd54df61
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047207279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.2047207279
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.3378402554
Short name T510
Test name
Test status
Simulation time 97673977 ps
CPU time 1.04 seconds
Started Aug 18 05:41:12 PM PDT 24
Finished Aug 18 05:41:13 PM PDT 24
Peak memory 198000 kb
Host smart-294cbb36-7197-4f44-9bfc-05d1863f7882
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378402554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.3378402554
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.1425424902
Short name T414
Test name
Test status
Simulation time 38359297 ps
CPU time 1.02 seconds
Started Aug 18 05:40:48 PM PDT 24
Finished Aug 18 05:40:49 PM PDT 24
Peak memory 196712 kb
Host smart-72ce497d-b310-4963-be60-5a39c9223dd9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425424902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.1425424902
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.2319942081
Short name T424
Test name
Test status
Simulation time 42855991 ps
CPU time 1.01 seconds
Started Aug 18 05:40:45 PM PDT 24
Finished Aug 18 05:40:46 PM PDT 24
Peak memory 196180 kb
Host smart-74b4002e-63c5-4421-8064-fd223e5770d1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319942081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.2319942081
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.1102954963
Short name T29
Test name
Test status
Simulation time 56878659 ps
CPU time 1 seconds
Started Aug 18 05:40:48 PM PDT 24
Finished Aug 18 05:40:49 PM PDT 24
Peak memory 195720 kb
Host smart-e4576793-47c6-4652-b2e4-c895fdc8a41f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102954963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.1102954963
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.880529934
Short name T276
Test name
Test status
Simulation time 113404310 ps
CPU time 0.8 seconds
Started Aug 18 05:41:02 PM PDT 24
Finished Aug 18 05:41:08 PM PDT 24
Peak memory 195548 kb
Host smart-3a73ee89-df47-49f7-b9f2-5148cb54868f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880529934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.880529934
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.892893658
Short name T659
Test name
Test status
Simulation time 52682678 ps
CPU time 0.67 seconds
Started Aug 18 05:40:44 PM PDT 24
Finished Aug 18 05:40:45 PM PDT 24
Peak memory 195500 kb
Host smart-3fc0ca03-abae-457d-97f5-6d285090b685
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892893658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullup
_pulldown.892893658
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.2620098192
Short name T374
Test name
Test status
Simulation time 255307929 ps
CPU time 4.14 seconds
Started Aug 18 05:40:47 PM PDT 24
Finished Aug 18 05:40:52 PM PDT 24
Peak memory 198152 kb
Host smart-b31dda4d-fa6b-4a9a-8586-c84857e0de64
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620098192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.2620098192
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.1409088576
Short name T712
Test name
Test status
Simulation time 47562462 ps
CPU time 0.75 seconds
Started Aug 18 05:40:52 PM PDT 24
Finished Aug 18 05:40:53 PM PDT 24
Peak memory 196088 kb
Host smart-a7bf4d86-020a-424b-885a-90e008311710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409088576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.1409088576
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.3251441850
Short name T514
Test name
Test status
Simulation time 56150698 ps
CPU time 0.98 seconds
Started Aug 18 05:40:45 PM PDT 24
Finished Aug 18 05:40:46 PM PDT 24
Peak memory 195700 kb
Host smart-f5dc9d8c-7bd1-4b4e-b12d-c32de9780489
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251441850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.3251441850
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.3158481825
Short name T121
Test name
Test status
Simulation time 3153778529 ps
CPU time 21.5 seconds
Started Aug 18 05:40:43 PM PDT 24
Finished Aug 18 05:41:04 PM PDT 24
Peak memory 198292 kb
Host smart-ca704e5d-ea6a-442f-b77c-8af69e6f97f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158481825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.3158481825
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_stress_all_with_rand_reset.373451301
Short name T63
Test name
Test status
Simulation time 1862840274 ps
CPU time 61.17 seconds
Started Aug 18 05:40:42 PM PDT 24
Finished Aug 18 05:41:43 PM PDT 24
Peak memory 198372 kb
Host smart-8054276f-17f1-4dbd-8ab5-313eaec91387
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=373451301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_stress_all_with_rand_reset.373451301
Directory /workspace/14.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.1804160904
Short name T638
Test name
Test status
Simulation time 27656203 ps
CPU time 0.61 seconds
Started Aug 18 05:40:52 PM PDT 24
Finished Aug 18 05:40:52 PM PDT 24
Peak memory 194700 kb
Host smart-ff617261-8871-4def-8ce6-5fa4c0f881a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804160904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.1804160904
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.3572051460
Short name T582
Test name
Test status
Simulation time 343404753 ps
CPU time 17.71 seconds
Started Aug 18 05:40:44 PM PDT 24
Finished Aug 18 05:41:02 PM PDT 24
Peak memory 195680 kb
Host smart-86baaa12-bebc-4cf7-8901-7fe315fa866d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572051460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.3572051460
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.3453469755
Short name T170
Test name
Test status
Simulation time 63434620 ps
CPU time 0.96 seconds
Started Aug 18 05:40:51 PM PDT 24
Finished Aug 18 05:40:52 PM PDT 24
Peak memory 196856 kb
Host smart-05062d16-5fe6-436f-b65f-c5e17701d10e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453469755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.3453469755
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.1815848379
Short name T241
Test name
Test status
Simulation time 186809077 ps
CPU time 1.27 seconds
Started Aug 18 05:40:47 PM PDT 24
Finished Aug 18 05:40:49 PM PDT 24
Peak memory 197288 kb
Host smart-ffd08ae2-36a9-4c08-ba3b-606febebc9e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815848379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.1815848379
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.1059690918
Short name T256
Test name
Test status
Simulation time 60180085 ps
CPU time 2.29 seconds
Started Aug 18 05:40:52 PM PDT 24
Finished Aug 18 05:40:55 PM PDT 24
Peak memory 198240 kb
Host smart-07b47d88-d57d-447f-9aef-626838c85007
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059690918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.1059690918
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.2639232593
Short name T110
Test name
Test status
Simulation time 65274547 ps
CPU time 1.83 seconds
Started Aug 18 05:40:45 PM PDT 24
Finished Aug 18 05:40:47 PM PDT 24
Peak memory 196888 kb
Host smart-93765553-fb7f-4d16-8157-0f36f3e785f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639232593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.2639232593
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.3127790782
Short name T249
Test name
Test status
Simulation time 107593926 ps
CPU time 1.15 seconds
Started Aug 18 05:40:49 PM PDT 24
Finished Aug 18 05:40:50 PM PDT 24
Peak memory 195968 kb
Host smart-66b41d36-705e-4ed2-9812-8286805d4000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127790782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.3127790782
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.3751437124
Short name T262
Test name
Test status
Simulation time 57843950 ps
CPU time 0.76 seconds
Started Aug 18 05:40:50 PM PDT 24
Finished Aug 18 05:40:51 PM PDT 24
Peak memory 196192 kb
Host smart-83e2bbb4-ac97-4ddc-b715-60353a132a11
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751437124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.3751437124
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.1673957553
Short name T5
Test name
Test status
Simulation time 189646273 ps
CPU time 2 seconds
Started Aug 18 05:40:47 PM PDT 24
Finished Aug 18 05:40:49 PM PDT 24
Peak memory 198180 kb
Host smart-552165a1-9f6f-48d8-8006-7f880603dff2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673957553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.1673957553
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.1515051069
Short name T443
Test name
Test status
Simulation time 44180953 ps
CPU time 0.95 seconds
Started Aug 18 05:40:48 PM PDT 24
Finished Aug 18 05:40:50 PM PDT 24
Peak memory 196488 kb
Host smart-c94461dc-d86f-4af7-9bf1-fba540081022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515051069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.1515051069
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.1859905438
Short name T438
Test name
Test status
Simulation time 37636545 ps
CPU time 1.07 seconds
Started Aug 18 05:40:48 PM PDT 24
Finished Aug 18 05:40:50 PM PDT 24
Peak memory 196704 kb
Host smart-168de7dc-78e1-432f-aedc-92e2ef4457b8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859905438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.1859905438
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.474809478
Short name T210
Test name
Test status
Simulation time 24316139477 ps
CPU time 139.4 seconds
Started Aug 18 05:40:51 PM PDT 24
Finished Aug 18 05:43:10 PM PDT 24
Peak memory 198248 kb
Host smart-3b70878d-ddf7-4b1a-a1b0-4f990121e7d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474809478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.g
pio_stress_all.474809478
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_stress_all_with_rand_reset.2511267717
Short name T587
Test name
Test status
Simulation time 7669526691 ps
CPU time 67.81 seconds
Started Aug 18 05:41:00 PM PDT 24
Finished Aug 18 05:42:07 PM PDT 24
Peak memory 198500 kb
Host smart-f0a68ec5-3dad-4cd4-a205-e32a6e171c38
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2511267717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_stress_all_with_rand_reset.2511267717
Directory /workspace/15.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.gpio_alert_test.2338222735
Short name T391
Test name
Test status
Simulation time 63507688 ps
CPU time 0.57 seconds
Started Aug 18 05:41:01 PM PDT 24
Finished Aug 18 05:41:01 PM PDT 24
Peak memory 194068 kb
Host smart-1acb951f-75dd-4838-9810-00207015a867
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338222735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.2338222735
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.2265572687
Short name T207
Test name
Test status
Simulation time 132756480 ps
CPU time 0.9 seconds
Started Aug 18 05:41:05 PM PDT 24
Finished Aug 18 05:41:06 PM PDT 24
Peak memory 195872 kb
Host smart-f2ad09a4-b456-46d4-924f-54fea7792a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265572687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.2265572687
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.3102049240
Short name T14
Test name
Test status
Simulation time 510297080 ps
CPU time 14.14 seconds
Started Aug 18 05:40:39 PM PDT 24
Finished Aug 18 05:40:53 PM PDT 24
Peak memory 196972 kb
Host smart-1d36a3b6-ee1b-4b41-a2b5-cc0131949f95
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102049240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.3102049240
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.3636245032
Short name T336
Test name
Test status
Simulation time 136961368 ps
CPU time 0.88 seconds
Started Aug 18 05:40:57 PM PDT 24
Finished Aug 18 05:40:59 PM PDT 24
Peak memory 197112 kb
Host smart-738ddde5-ab57-4632-9610-2958f845e6b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636245032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.3636245032
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.1184338579
Short name T211
Test name
Test status
Simulation time 36467287 ps
CPU time 0.77 seconds
Started Aug 18 05:40:59 PM PDT 24
Finished Aug 18 05:41:00 PM PDT 24
Peak memory 195628 kb
Host smart-c95c99ea-bf00-4fb9-be5b-5966f6aab919
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184338579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.1184338579
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.3236562554
Short name T380
Test name
Test status
Simulation time 68774999 ps
CPU time 2.62 seconds
Started Aug 18 05:40:47 PM PDT 24
Finished Aug 18 05:40:50 PM PDT 24
Peak memory 198232 kb
Host smart-877273c0-c929-457c-9c51-060336578fa5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236562554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.3236562554
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.3169425473
Short name T423
Test name
Test status
Simulation time 215985894 ps
CPU time 2.11 seconds
Started Aug 18 05:40:51 PM PDT 24
Finished Aug 18 05:40:53 PM PDT 24
Peak memory 196072 kb
Host smart-48334f02-9685-41fd-9928-d6b0bb70dc56
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169425473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.3169425473
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.3071426266
Short name T600
Test name
Test status
Simulation time 71517740 ps
CPU time 0.72 seconds
Started Aug 18 05:40:46 PM PDT 24
Finished Aug 18 05:40:47 PM PDT 24
Peak memory 195572 kb
Host smart-81f65dc5-c79b-4d98-a7ae-ced27daccc6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071426266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.3071426266
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.2549111350
Short name T652
Test name
Test status
Simulation time 38363123 ps
CPU time 0.82 seconds
Started Aug 18 05:41:10 PM PDT 24
Finished Aug 18 05:41:10 PM PDT 24
Peak memory 196544 kb
Host smart-232fb5ea-d54b-4a12-a184-a79adaa89ecf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549111350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.2549111350
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.1287932183
Short name T314
Test name
Test status
Simulation time 571311385 ps
CPU time 3.13 seconds
Started Aug 18 05:40:50 PM PDT 24
Finished Aug 18 05:40:53 PM PDT 24
Peak memory 198148 kb
Host smart-1499dc70-1add-40a4-aeea-da8df44df1be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287932183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.1287932183
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.4063180641
Short name T219
Test name
Test status
Simulation time 44502988 ps
CPU time 1.24 seconds
Started Aug 18 05:40:43 PM PDT 24
Finished Aug 18 05:40:45 PM PDT 24
Peak memory 196524 kb
Host smart-c3146571-d552-4faa-b252-45d06effb682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063180641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.4063180641
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.3456541753
Short name T603
Test name
Test status
Simulation time 88720013 ps
CPU time 1.2 seconds
Started Aug 18 05:41:01 PM PDT 24
Finished Aug 18 05:41:02 PM PDT 24
Peak memory 196488 kb
Host smart-c4106878-4770-4210-b8c6-ecc72ec3f41b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456541753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.3456541753
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.998859
Short name T61
Test name
Test status
Simulation time 2602663950 ps
CPU time 65.52 seconds
Started Aug 18 05:40:59 PM PDT 24
Finished Aug 18 05:42:05 PM PDT 24
Peak memory 192084 kb
Host smart-00bc2af9-def5-4bef-9bc8-1af43ac7b909
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio
_stress_all.998859
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_stress_all_with_rand_reset.939159521
Short name T4
Test name
Test status
Simulation time 1837515892 ps
CPU time 24.49 seconds
Started Aug 18 05:41:09 PM PDT 24
Finished Aug 18 05:41:34 PM PDT 24
Peak memory 197772 kb
Host smart-989eafe8-f676-4acf-b9ed-fbc3113dd6e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=939159521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_stress_all_with_rand_reset.939159521
Directory /workspace/16.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.gpio_alert_test.1601411080
Short name T41
Test name
Test status
Simulation time 77495268 ps
CPU time 0.55 seconds
Started Aug 18 05:40:54 PM PDT 24
Finished Aug 18 05:40:55 PM PDT 24
Peak memory 194040 kb
Host smart-d55487d3-a427-49fd-8fba-39e9dc56c45d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601411080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.1601411080
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.254407251
Short name T589
Test name
Test status
Simulation time 62713476 ps
CPU time 0.63 seconds
Started Aug 18 05:40:46 PM PDT 24
Finished Aug 18 05:40:46 PM PDT 24
Peak memory 194164 kb
Host smart-1e47b672-1bed-439f-842c-c9e54223666a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254407251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.254407251
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_full_random.4201852904
Short name T646
Test name
Test status
Simulation time 180487864 ps
CPU time 0.74 seconds
Started Aug 18 05:41:04 PM PDT 24
Finished Aug 18 05:41:05 PM PDT 24
Peak memory 196032 kb
Host smart-7d2b35ab-7711-405e-bba3-109523922739
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201852904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.4201852904
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.4254790660
Short name T147
Test name
Test status
Simulation time 146488841 ps
CPU time 1.16 seconds
Started Aug 18 05:40:56 PM PDT 24
Finished Aug 18 05:40:58 PM PDT 24
Peak memory 196244 kb
Host smart-6a905c3d-b457-4954-a7de-7f0a53f98114
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254790660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.4254790660
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.504384641
Short name T397
Test name
Test status
Simulation time 90659465 ps
CPU time 1.49 seconds
Started Aug 18 05:40:56 PM PDT 24
Finished Aug 18 05:40:58 PM PDT 24
Peak memory 196840 kb
Host smart-f0ac167d-6178-4c55-b7e4-9102964004cd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504384641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 17.gpio_intr_with_filter_rand_intr_event.504384641
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.149149610
Short name T175
Test name
Test status
Simulation time 42356591 ps
CPU time 0.92 seconds
Started Aug 18 05:40:57 PM PDT 24
Finished Aug 18 05:40:58 PM PDT 24
Peak memory 195548 kb
Host smart-b23d4edb-6698-4e6a-8b85-373de6614ce1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149149610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger.
149149610
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.3157955804
Short name T355
Test name
Test status
Simulation time 24678159 ps
CPU time 0.86 seconds
Started Aug 18 05:40:55 PM PDT 24
Finished Aug 18 05:40:56 PM PDT 24
Peak memory 196848 kb
Host smart-34a07ce0-2992-4de5-97bc-b8c7872dd75d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157955804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.3157955804
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.44863635
Short name T639
Test name
Test status
Simulation time 18737508 ps
CPU time 0.68 seconds
Started Aug 18 05:40:38 PM PDT 24
Finished Aug 18 05:40:38 PM PDT 24
Peak memory 195432 kb
Host smart-676ffbe4-08c9-49cc-b7da-14ab76a3eed3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44863635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullup_
pulldown.44863635
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.3261904640
Short name T273
Test name
Test status
Simulation time 785183756 ps
CPU time 3.5 seconds
Started Aug 18 05:41:10 PM PDT 24
Finished Aug 18 05:41:14 PM PDT 24
Peak memory 198136 kb
Host smart-4edaaea1-a1bd-42f3-8fe8-eb8dbbe72038
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261904640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.3261904640
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.3135466751
Short name T707
Test name
Test status
Simulation time 96355565 ps
CPU time 0.95 seconds
Started Aug 18 05:40:52 PM PDT 24
Finished Aug 18 05:40:58 PM PDT 24
Peak memory 195932 kb
Host smart-c03ec4d7-7e75-4d7d-b3f9-6d3e1534d11f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135466751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.3135466751
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.788395077
Short name T426
Test name
Test status
Simulation time 427734980 ps
CPU time 1.38 seconds
Started Aug 18 05:41:07 PM PDT 24
Finished Aug 18 05:41:08 PM PDT 24
Peak memory 198152 kb
Host smart-71e7751e-79bf-4f34-8aca-42defd12870e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788395077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.788395077
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.1954868418
Short name T354
Test name
Test status
Simulation time 20328092735 ps
CPU time 123.53 seconds
Started Aug 18 05:41:10 PM PDT 24
Finished Aug 18 05:43:14 PM PDT 24
Peak memory 198348 kb
Host smart-564a60ed-7712-4cd6-ba41-521617e9e92c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954868418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.1954868418
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_alert_test.2302291041
Short name T237
Test name
Test status
Simulation time 53989955 ps
CPU time 0.57 seconds
Started Aug 18 05:40:50 PM PDT 24
Finished Aug 18 05:40:51 PM PDT 24
Peak memory 194756 kb
Host smart-9cdadc34-ff81-4b2f-8b4a-d7ea813ef354
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302291041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.2302291041
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.3056610541
Short name T433
Test name
Test status
Simulation time 674866540 ps
CPU time 1.07 seconds
Started Aug 18 05:41:01 PM PDT 24
Finished Aug 18 05:41:07 PM PDT 24
Peak memory 195700 kb
Host smart-f7ef4c03-5afc-4937-8145-2580c0eb240c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056610541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.3056610541
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.740016169
Short name T524
Test name
Test status
Simulation time 420093200 ps
CPU time 20.52 seconds
Started Aug 18 05:41:11 PM PDT 24
Finished Aug 18 05:41:31 PM PDT 24
Peak memory 197148 kb
Host smart-5184492d-c8b2-4ad2-a40d-17eef85031ce
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740016169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stres
s.740016169
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.2469917030
Short name T528
Test name
Test status
Simulation time 125437738 ps
CPU time 0.85 seconds
Started Aug 18 05:40:59 PM PDT 24
Finished Aug 18 05:41:00 PM PDT 24
Peak memory 196204 kb
Host smart-51db1415-7201-4c26-9bc3-cf0f14cbf37d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469917030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.2469917030
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.4102018492
Short name T674
Test name
Test status
Simulation time 59138645 ps
CPU time 0.95 seconds
Started Aug 18 05:40:53 PM PDT 24
Finished Aug 18 05:40:54 PM PDT 24
Peak memory 196112 kb
Host smart-8ea79450-256e-4dd1-a3f1-1437b65b4ec7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102018492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.4102018492
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.2770295886
Short name T247
Test name
Test status
Simulation time 92211865 ps
CPU time 3.36 seconds
Started Aug 18 05:41:01 PM PDT 24
Finished Aug 18 05:41:05 PM PDT 24
Peak memory 198224 kb
Host smart-442e1e82-3229-45ad-a64e-61dec629775e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770295886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.2770295886
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.3770120195
Short name T507
Test name
Test status
Simulation time 42453823 ps
CPU time 1.37 seconds
Started Aug 18 05:41:00 PM PDT 24
Finished Aug 18 05:41:01 PM PDT 24
Peak memory 196964 kb
Host smart-d4c25616-cff7-4009-82ec-ef204d00ca64
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770120195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.3770120195
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.1754608246
Short name T376
Test name
Test status
Simulation time 94818139 ps
CPU time 1.02 seconds
Started Aug 18 05:40:59 PM PDT 24
Finished Aug 18 05:41:00 PM PDT 24
Peak memory 196780 kb
Host smart-0afe8a9d-efd3-43b4-8c97-e1c6bc5d37f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754608246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.1754608246
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.173186376
Short name T602
Test name
Test status
Simulation time 104309968 ps
CPU time 1.25 seconds
Started Aug 18 05:40:45 PM PDT 24
Finished Aug 18 05:40:47 PM PDT 24
Peak memory 196756 kb
Host smart-d51dd58e-14bc-4087-b80c-9ccec27a76e6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173186376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullup
_pulldown.173186376
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.2123980258
Short name T605
Test name
Test status
Simulation time 292756758 ps
CPU time 3.52 seconds
Started Aug 18 05:40:48 PM PDT 24
Finished Aug 18 05:40:52 PM PDT 24
Peak memory 198124 kb
Host smart-f2fa9f58-1198-4d55-8550-fba2f263764e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123980258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.2123980258
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.1066986016
Short name T202
Test name
Test status
Simulation time 36182915 ps
CPU time 0.99 seconds
Started Aug 18 05:41:02 PM PDT 24
Finished Aug 18 05:41:03 PM PDT 24
Peak memory 195976 kb
Host smart-6f41e33e-8533-496c-9f98-34baf53f061c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066986016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.1066986016
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.2520048895
Short name T498
Test name
Test status
Simulation time 35500647 ps
CPU time 0.86 seconds
Started Aug 18 05:40:50 PM PDT 24
Finished Aug 18 05:40:51 PM PDT 24
Peak memory 196364 kb
Host smart-01418fcd-c695-4549-9662-b69d1022d985
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520048895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.2520048895
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.2666397789
Short name T490
Test name
Test status
Simulation time 22271224594 ps
CPU time 138.03 seconds
Started Aug 18 05:40:52 PM PDT 24
Finished Aug 18 05:43:10 PM PDT 24
Peak memory 198276 kb
Host smart-62328dd8-fb5a-4817-8fa2-f847d094f826
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666397789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.2666397789
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_alert_test.869287506
Short name T554
Test name
Test status
Simulation time 15022933 ps
CPU time 0.57 seconds
Started Aug 18 05:40:49 PM PDT 24
Finished Aug 18 05:40:49 PM PDT 24
Peak memory 194076 kb
Host smart-28f242e0-d5be-46c0-a676-7ed171791788
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869287506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.869287506
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.4160695593
Short name T148
Test name
Test status
Simulation time 306826581 ps
CPU time 0.85 seconds
Started Aug 18 05:40:52 PM PDT 24
Finished Aug 18 05:40:58 PM PDT 24
Peak memory 195784 kb
Host smart-c4db2efa-395b-4d00-a2c1-7635a9ac40dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160695593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.4160695593
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.3164936848
Short name T295
Test name
Test status
Simulation time 897359298 ps
CPU time 10.57 seconds
Started Aug 18 05:41:02 PM PDT 24
Finished Aug 18 05:41:13 PM PDT 24
Peak memory 198100 kb
Host smart-1dcfd801-1116-4b8f-86f3-e8cb4ed9cc57
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164936848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.3164936848
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.2408096491
Short name T622
Test name
Test status
Simulation time 91885350 ps
CPU time 1.03 seconds
Started Aug 18 05:40:59 PM PDT 24
Finished Aug 18 05:41:00 PM PDT 24
Peak memory 196700 kb
Host smart-b514b4d3-d717-499f-9646-34e0f1aaa42a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408096491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.2408096491
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.971846404
Short name T13
Test name
Test status
Simulation time 25756607 ps
CPU time 0.84 seconds
Started Aug 18 05:40:55 PM PDT 24
Finished Aug 18 05:40:56 PM PDT 24
Peak memory 196704 kb
Host smart-5ca2836b-6834-47d5-9d06-4629fef7c4b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971846404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.971846404
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.2576269571
Short name T164
Test name
Test status
Simulation time 80552425 ps
CPU time 1.61 seconds
Started Aug 18 05:41:02 PM PDT 24
Finished Aug 18 05:41:04 PM PDT 24
Peak memory 196980 kb
Host smart-2a3017ef-f2eb-4fea-a15b-39f703245b6f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576269571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.2576269571
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.933797976
Short name T434
Test name
Test status
Simulation time 214302630 ps
CPU time 1.83 seconds
Started Aug 18 05:40:43 PM PDT 24
Finished Aug 18 05:40:45 PM PDT 24
Peak memory 196588 kb
Host smart-b224862b-5dc9-4a1a-b9bc-8f7de268a661
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933797976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger.
933797976
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.1000450244
Short name T520
Test name
Test status
Simulation time 99979129 ps
CPU time 1.04 seconds
Started Aug 18 05:40:47 PM PDT 24
Finished Aug 18 05:40:48 PM PDT 24
Peak memory 196176 kb
Host smart-c98c4d78-74c8-4975-9bb9-9e89d4bf1442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000450244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.1000450244
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.2198392417
Short name T16
Test name
Test status
Simulation time 90977218 ps
CPU time 0.71 seconds
Started Aug 18 05:40:47 PM PDT 24
Finished Aug 18 05:40:48 PM PDT 24
Peak memory 195380 kb
Host smart-f70008a3-8de2-43cc-a071-ce757ab27144
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198392417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.2198392417
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.1987649244
Short name T581
Test name
Test status
Simulation time 256966217 ps
CPU time 1.35 seconds
Started Aug 18 05:40:47 PM PDT 24
Finished Aug 18 05:40:48 PM PDT 24
Peak memory 198080 kb
Host smart-d4487da4-8507-421c-862b-162adccf6e30
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987649244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.1987649244
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.1144341930
Short name T159
Test name
Test status
Simulation time 214978373 ps
CPU time 0.92 seconds
Started Aug 18 05:40:58 PM PDT 24
Finished Aug 18 05:40:59 PM PDT 24
Peak memory 195448 kb
Host smart-c5ca0b93-8835-45be-9256-6a065117ac3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144341930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.1144341930
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.3912634954
Short name T291
Test name
Test status
Simulation time 198689349 ps
CPU time 0.92 seconds
Started Aug 18 05:40:43 PM PDT 24
Finished Aug 18 05:40:45 PM PDT 24
Peak memory 195392 kb
Host smart-a1aeb539-f13e-4ce1-87c6-c4d4dc8ee289
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912634954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.3912634954
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.2986844822
Short name T126
Test name
Test status
Simulation time 4502365053 ps
CPU time 64.47 seconds
Started Aug 18 05:41:27 PM PDT 24
Finished Aug 18 05:42:32 PM PDT 24
Peak memory 198264 kb
Host smart-dc20b76e-ad9c-4404-ac7c-8cde707820dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986844822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.2986844822
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_alert_test.3870314064
Short name T478
Test name
Test status
Simulation time 130956733 ps
CPU time 0.56 seconds
Started Aug 18 05:40:26 PM PDT 24
Finished Aug 18 05:40:27 PM PDT 24
Peak memory 194036 kb
Host smart-c0fbfd17-ff69-45b1-a507-5e68f5dfff1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870314064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.3870314064
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.487818283
Short name T604
Test name
Test status
Simulation time 61032953 ps
CPU time 0.73 seconds
Started Aug 18 05:40:16 PM PDT 24
Finished Aug 18 05:40:17 PM PDT 24
Peak memory 195004 kb
Host smart-a24c9c86-593a-42ee-aabc-bd853d3181f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487818283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.487818283
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.817612871
Short name T649
Test name
Test status
Simulation time 3734201578 ps
CPU time 30.5 seconds
Started Aug 18 05:40:17 PM PDT 24
Finished Aug 18 05:40:47 PM PDT 24
Peak memory 197748 kb
Host smart-13e0068a-e054-4501-a5a7-99a55955c291
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817612871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stress
.817612871
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.1649887676
Short name T28
Test name
Test status
Simulation time 54636343 ps
CPU time 0.85 seconds
Started Aug 18 05:40:14 PM PDT 24
Finished Aug 18 05:40:15 PM PDT 24
Peak memory 196256 kb
Host smart-9ca5996c-948f-4315-93a8-2fb20ae5c2d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649887676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.1649887676
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.4161137957
Short name T74
Test name
Test status
Simulation time 42215329 ps
CPU time 0.87 seconds
Started Aug 18 05:40:32 PM PDT 24
Finished Aug 18 05:40:34 PM PDT 24
Peak memory 196888 kb
Host smart-ec70359a-51f3-421e-aa12-8f6443f54e53
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161137957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.4161137957
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.626419870
Short name T627
Test name
Test status
Simulation time 91979944 ps
CPU time 3.45 seconds
Started Aug 18 05:40:15 PM PDT 24
Finished Aug 18 05:40:19 PM PDT 24
Peak memory 196620 kb
Host smart-b730d83f-2543-4305-be97-020cb3037741
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626419870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.gpio_intr_with_filter_rand_intr_event.626419870
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.482243078
Short name T529
Test name
Test status
Simulation time 45565855 ps
CPU time 1.57 seconds
Started Aug 18 05:40:14 PM PDT 24
Finished Aug 18 05:40:16 PM PDT 24
Peak memory 196256 kb
Host smart-5493b626-e8cd-409f-b967-835d61ba054e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482243078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.482243078
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.3167368905
Short name T352
Test name
Test status
Simulation time 73996274 ps
CPU time 1.01 seconds
Started Aug 18 05:40:24 PM PDT 24
Finished Aug 18 05:40:25 PM PDT 24
Peak memory 195912 kb
Host smart-bb6abea4-3405-434a-b914-98d2790035c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167368905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.3167368905
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.1172554336
Short name T413
Test name
Test status
Simulation time 89327748 ps
CPU time 0.74 seconds
Started Aug 18 05:40:12 PM PDT 24
Finished Aug 18 05:40:12 PM PDT 24
Peak memory 195468 kb
Host smart-421f8263-3ec6-4b9c-b604-d5dc9541830a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172554336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.1172554336
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.3743776714
Short name T338
Test name
Test status
Simulation time 1716502268 ps
CPU time 5.3 seconds
Started Aug 18 05:40:30 PM PDT 24
Finished Aug 18 05:40:36 PM PDT 24
Peak memory 198204 kb
Host smart-4f0f472e-cb4b-4d47-b07c-d74c6c4445f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743776714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.3743776714
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.2421613639
Short name T35
Test name
Test status
Simulation time 256011563 ps
CPU time 0.82 seconds
Started Aug 18 05:40:25 PM PDT 24
Finished Aug 18 05:40:26 PM PDT 24
Peak memory 214856 kb
Host smart-f8ecafe3-a965-43b1-a303-d14832aa0f54
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421613639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.2421613639
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.3635130969
Short name T344
Test name
Test status
Simulation time 74402348 ps
CPU time 1.31 seconds
Started Aug 18 05:40:05 PM PDT 24
Finished Aug 18 05:40:06 PM PDT 24
Peak memory 198152 kb
Host smart-1deab328-685a-4fe4-aaa2-079677931fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635130969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.3635130969
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.1730037846
Short name T238
Test name
Test status
Simulation time 58367505 ps
CPU time 0.94 seconds
Started Aug 18 05:40:21 PM PDT 24
Finished Aug 18 05:40:22 PM PDT 24
Peak memory 195876 kb
Host smart-faaaeb10-1996-4a3d-817b-8c854f0ed273
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730037846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.1730037846
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.379311988
Short name T308
Test name
Test status
Simulation time 16233335633 ps
CPU time 96.75 seconds
Started Aug 18 05:40:12 PM PDT 24
Finished Aug 18 05:41:49 PM PDT 24
Peak memory 198272 kb
Host smart-56f79702-c320-46ba-a4f3-9a698b530f9c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379311988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gp
io_stress_all.379311988
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_alert_test.1994327631
Short name T663
Test name
Test status
Simulation time 24801100 ps
CPU time 0.57 seconds
Started Aug 18 05:40:57 PM PDT 24
Finished Aug 18 05:40:58 PM PDT 24
Peak memory 194600 kb
Host smart-b2a14873-49d6-419a-95f3-06e1b28253ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994327631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.1994327631
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.1757090034
Short name T129
Test name
Test status
Simulation time 28830512 ps
CPU time 0.86 seconds
Started Aug 18 05:41:01 PM PDT 24
Finished Aug 18 05:41:07 PM PDT 24
Peak memory 196264 kb
Host smart-425dcb25-54a5-4f03-80ad-1c86a2247e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757090034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.1757090034
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.1894947296
Short name T181
Test name
Test status
Simulation time 2000296895 ps
CPU time 26.71 seconds
Started Aug 18 05:41:03 PM PDT 24
Finished Aug 18 05:41:30 PM PDT 24
Peak memory 197300 kb
Host smart-98e20638-8529-4a63-9d81-361d99ba9d87
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894947296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.1894947296
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.3311506212
Short name T452
Test name
Test status
Simulation time 60959029 ps
CPU time 0.84 seconds
Started Aug 18 05:40:56 PM PDT 24
Finished Aug 18 05:40:57 PM PDT 24
Peak memory 196956 kb
Host smart-74090fc1-f271-4951-86a2-1d91171bbf82
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311506212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.3311506212
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.1175219936
Short name T544
Test name
Test status
Simulation time 392422201 ps
CPU time 1.18 seconds
Started Aug 18 05:40:47 PM PDT 24
Finished Aug 18 05:40:48 PM PDT 24
Peak memory 197056 kb
Host smart-6e0f2d1c-0d66-4c34-a38b-9a04627c5c35
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175219936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.1175219936
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.744368281
Short name T154
Test name
Test status
Simulation time 42758269 ps
CPU time 1.73 seconds
Started Aug 18 05:41:03 PM PDT 24
Finished Aug 18 05:41:05 PM PDT 24
Peak memory 198228 kb
Host smart-3d02d126-64b2-4e65-a04a-3781e7964d21
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744368281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 20.gpio_intr_with_filter_rand_intr_event.744368281
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.1920160388
Short name T18
Test name
Test status
Simulation time 905857562 ps
CPU time 1.77 seconds
Started Aug 18 05:40:44 PM PDT 24
Finished Aug 18 05:40:46 PM PDT 24
Peak memory 196648 kb
Host smart-5bb0f073-95ec-4e1a-bf44-0a5c3a350cce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920160388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.1920160388
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.400966897
Short name T278
Test name
Test status
Simulation time 1177959851 ps
CPU time 1.17 seconds
Started Aug 18 05:40:54 PM PDT 24
Finished Aug 18 05:40:55 PM PDT 24
Peak memory 196736 kb
Host smart-ff54f028-9127-408b-81dc-b97cbf58c5b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400966897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.400966897
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.2588848415
Short name T172
Test name
Test status
Simulation time 48460973 ps
CPU time 0.7 seconds
Started Aug 18 05:40:45 PM PDT 24
Finished Aug 18 05:40:46 PM PDT 24
Peak memory 196244 kb
Host smart-f9431f0f-0987-4652-9d24-aa40f0852550
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588848415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.2588848415
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.3610359603
Short name T711
Test name
Test status
Simulation time 1870101408 ps
CPU time 6.1 seconds
Started Aug 18 05:40:43 PM PDT 24
Finished Aug 18 05:40:49 PM PDT 24
Peak memory 198156 kb
Host smart-15f30cc8-78ec-46ab-afc2-9e0d2338f1d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610359603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.3610359603
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.3558711482
Short name T267
Test name
Test status
Simulation time 95094677 ps
CPU time 1.4 seconds
Started Aug 18 05:41:03 PM PDT 24
Finished Aug 18 05:41:04 PM PDT 24
Peak memory 195708 kb
Host smart-6455e84a-90bc-43eb-a23d-6724c60c7d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558711482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.3558711482
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.3346419969
Short name T240
Test name
Test status
Simulation time 60738972 ps
CPU time 1.01 seconds
Started Aug 18 05:41:11 PM PDT 24
Finished Aug 18 05:41:12 PM PDT 24
Peak memory 195652 kb
Host smart-70a7dc67-a0e7-4b2c-9cb0-b389520a2a33
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346419969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.3346419969
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.1934592103
Short name T371
Test name
Test status
Simulation time 4593136596 ps
CPU time 100.27 seconds
Started Aug 18 05:41:19 PM PDT 24
Finished Aug 18 05:42:59 PM PDT 24
Peak memory 198356 kb
Host smart-0331a377-e9dc-4ae4-8e1a-8add5803b974
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934592103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.1934592103
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_stress_all_with_rand_reset.2477828226
Short name T523
Test name
Test status
Simulation time 3598875005 ps
CPU time 110.17 seconds
Started Aug 18 05:41:00 PM PDT 24
Finished Aug 18 05:42:51 PM PDT 24
Peak memory 198556 kb
Host smart-442e28da-38e5-4a8f-9731-b797adcc9cd8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2477828226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_stress_all_with_rand_reset.2477828226
Directory /workspace/20.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.gpio_alert_test.494488867
Short name T230
Test name
Test status
Simulation time 17834387 ps
CPU time 0.54 seconds
Started Aug 18 05:40:59 PM PDT 24
Finished Aug 18 05:41:05 PM PDT 24
Peak memory 192812 kb
Host smart-ed01ec9b-9d96-4397-affa-ea4cea793669
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494488867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.494488867
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.616520098
Short name T666
Test name
Test status
Simulation time 292526987 ps
CPU time 0.96 seconds
Started Aug 18 05:40:51 PM PDT 24
Finished Aug 18 05:40:53 PM PDT 24
Peak memory 196080 kb
Host smart-f72d44ae-007e-4459-8dbd-448576e58ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616520098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.616520098
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.2421511989
Short name T190
Test name
Test status
Simulation time 196614614 ps
CPU time 4.96 seconds
Started Aug 18 05:40:59 PM PDT 24
Finished Aug 18 05:41:04 PM PDT 24
Peak memory 197124 kb
Host smart-dd3881c6-2b47-4a11-9243-ab6f99739a87
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421511989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.2421511989
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.997343575
Short name T177
Test name
Test status
Simulation time 65247101 ps
CPU time 0.94 seconds
Started Aug 18 05:41:31 PM PDT 24
Finished Aug 18 05:41:32 PM PDT 24
Peak memory 197820 kb
Host smart-50c6dec0-b159-4153-95d9-5f5bb70869b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997343575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.997343575
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.2476183873
Short name T565
Test name
Test status
Simulation time 285445196 ps
CPU time 1.31 seconds
Started Aug 18 05:41:06 PM PDT 24
Finished Aug 18 05:41:08 PM PDT 24
Peak memory 197364 kb
Host smart-da2f5e01-ae85-406c-a22c-b07159d8ebdb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476183873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.2476183873
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.825636666
Short name T209
Test name
Test status
Simulation time 28210840 ps
CPU time 1.14 seconds
Started Aug 18 05:40:59 PM PDT 24
Finished Aug 18 05:41:00 PM PDT 24
Peak memory 197608 kb
Host smart-814c78f3-f54e-4e00-8903-2c65d55f9947
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825636666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 21.gpio_intr_with_filter_rand_intr_event.825636666
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.1123103841
Short name T358
Test name
Test status
Simulation time 304231277 ps
CPU time 1.85 seconds
Started Aug 18 05:40:58 PM PDT 24
Finished Aug 18 05:41:00 PM PDT 24
Peak memory 197028 kb
Host smart-8ba3f269-cc9a-4686-8a94-beffe81a41f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123103841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.1123103841
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.167375766
Short name T576
Test name
Test status
Simulation time 20039634 ps
CPU time 0.63 seconds
Started Aug 18 05:41:02 PM PDT 24
Finished Aug 18 05:41:03 PM PDT 24
Peak memory 194412 kb
Host smart-7c4e6b05-73f7-466f-a92d-a21c53058a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167375766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.167375766
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.732903868
Short name T234
Test name
Test status
Simulation time 217970708 ps
CPU time 1.23 seconds
Started Aug 18 05:40:50 PM PDT 24
Finished Aug 18 05:40:51 PM PDT 24
Peak memory 196704 kb
Host smart-0b254256-6263-4fcf-8901-3ea49abd0be5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732903868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullup
_pulldown.732903868
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.2018716705
Short name T532
Test name
Test status
Simulation time 3270921151 ps
CPU time 5.58 seconds
Started Aug 18 05:41:12 PM PDT 24
Finished Aug 18 05:41:17 PM PDT 24
Peak memory 198292 kb
Host smart-09d43043-5e62-450f-9e15-70097082165c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018716705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.2018716705
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.982294734
Short name T117
Test name
Test status
Simulation time 163191432 ps
CPU time 1.28 seconds
Started Aug 18 05:41:09 PM PDT 24
Finished Aug 18 05:41:11 PM PDT 24
Peak memory 198164 kb
Host smart-5322e577-1570-4fcb-8ed2-355823c9ca32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982294734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.982294734
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.2205489794
Short name T444
Test name
Test status
Simulation time 87169602 ps
CPU time 1.3 seconds
Started Aug 18 05:40:57 PM PDT 24
Finished Aug 18 05:40:59 PM PDT 24
Peak memory 196952 kb
Host smart-da59ab9a-56fb-48e0-9b80-da41ad0f9c58
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205489794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.2205489794
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.2475393571
Short name T458
Test name
Test status
Simulation time 54073909112 ps
CPU time 138.79 seconds
Started Aug 18 05:41:09 PM PDT 24
Finished Aug 18 05:43:28 PM PDT 24
Peak memory 198372 kb
Host smart-bd62a985-8bba-487a-82fe-1abecd4e1957
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475393571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.2475393571
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_stress_all_with_rand_reset.408751603
Short name T68
Test name
Test status
Simulation time 2453883502 ps
CPU time 8.79 seconds
Started Aug 18 05:40:59 PM PDT 24
Finished Aug 18 05:41:08 PM PDT 24
Peak memory 197340 kb
Host smart-f2c31148-a5da-4c99-b7de-2aa616f9ae43
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=408751603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_stress_all_with_rand_reset.408751603
Directory /workspace/21.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.gpio_alert_test.839783126
Short name T462
Test name
Test status
Simulation time 13887994 ps
CPU time 0.57 seconds
Started Aug 18 05:41:01 PM PDT 24
Finished Aug 18 05:41:02 PM PDT 24
Peak memory 194188 kb
Host smart-27930e86-4809-49d4-9b7e-2ac87aa69e91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839783126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.839783126
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.1556387435
Short name T656
Test name
Test status
Simulation time 32035273 ps
CPU time 0.77 seconds
Started Aug 18 05:40:57 PM PDT 24
Finished Aug 18 05:40:58 PM PDT 24
Peak memory 196172 kb
Host smart-218bfb34-44ac-446b-a4cd-61cfb3188037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556387435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.1556387435
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.3786361862
Short name T403
Test name
Test status
Simulation time 2054033422 ps
CPU time 14.72 seconds
Started Aug 18 05:40:59 PM PDT 24
Finished Aug 18 05:41:13 PM PDT 24
Peak memory 197256 kb
Host smart-6ad571f9-ff11-423f-8415-8c3048d9fcf6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786361862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.3786361862
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.3347876704
Short name T449
Test name
Test status
Simulation time 19715529 ps
CPU time 0.74 seconds
Started Aug 18 05:41:33 PM PDT 24
Finished Aug 18 05:41:34 PM PDT 24
Peak memory 194700 kb
Host smart-f3393009-ea4c-4930-b76a-b7139057851a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347876704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.3347876704
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.1497691239
Short name T76
Test name
Test status
Simulation time 280499914 ps
CPU time 1.08 seconds
Started Aug 18 05:41:01 PM PDT 24
Finished Aug 18 05:41:02 PM PDT 24
Peak memory 196212 kb
Host smart-439f4d7b-72c2-4de8-8c69-c38d919d82c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497691239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.1497691239
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.3962563263
Short name T621
Test name
Test status
Simulation time 49703104 ps
CPU time 1.92 seconds
Started Aug 18 05:41:08 PM PDT 24
Finished Aug 18 05:41:15 PM PDT 24
Peak memory 198276 kb
Host smart-ed4dfc46-1cdf-45b7-b36a-6e7e523bda85
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962563263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.3962563263
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.3804893638
Short name T201
Test name
Test status
Simulation time 432067358 ps
CPU time 2.43 seconds
Started Aug 18 05:41:05 PM PDT 24
Finished Aug 18 05:41:07 PM PDT 24
Peak memory 198252 kb
Host smart-f0da111c-2b8c-4c7d-8c41-3a9b7e309e10
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804893638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.3804893638
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.3380751958
Short name T328
Test name
Test status
Simulation time 115986850 ps
CPU time 0.78 seconds
Started Aug 18 05:41:05 PM PDT 24
Finished Aug 18 05:41:06 PM PDT 24
Peak memory 197304 kb
Host smart-85bf2107-0442-4b94-a7a9-53e1183679e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380751958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.3380751958
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.2061387619
Short name T188
Test name
Test status
Simulation time 411814834 ps
CPU time 1.17 seconds
Started Aug 18 05:41:19 PM PDT 24
Finished Aug 18 05:41:20 PM PDT 24
Peak memory 195992 kb
Host smart-0ab04d82-2e6b-4626-a2f9-89869447bcc9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061387619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.2061387619
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.3601704052
Short name T356
Test name
Test status
Simulation time 120026957 ps
CPU time 2.12 seconds
Started Aug 18 05:40:52 PM PDT 24
Finished Aug 18 05:40:55 PM PDT 24
Peak memory 198136 kb
Host smart-2929b335-1e36-4097-9732-74a9a631d2a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601704052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.3601704052
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.241586526
Short name T366
Test name
Test status
Simulation time 110490692 ps
CPU time 1.1 seconds
Started Aug 18 05:40:53 PM PDT 24
Finished Aug 18 05:40:54 PM PDT 24
Peak memory 196552 kb
Host smart-0dd9833c-77aa-40d0-a6b7-b93ec97cd322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241586526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.241586526
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.442146061
Short name T134
Test name
Test status
Simulation time 160728809 ps
CPU time 1.52 seconds
Started Aug 18 05:41:01 PM PDT 24
Finished Aug 18 05:41:03 PM PDT 24
Peak memory 196904 kb
Host smart-ecce8de9-17da-4ac4-8e42-e635bd1b4fb3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442146061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.442146061
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.1690481170
Short name T250
Test name
Test status
Simulation time 9300543201 ps
CPU time 120.79 seconds
Started Aug 18 05:41:07 PM PDT 24
Finished Aug 18 05:43:08 PM PDT 24
Peak memory 198372 kb
Host smart-a649a7c2-ee17-4677-9a9f-7d7129a8b327
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690481170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.1690481170
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_alert_test.1111802853
Short name T534
Test name
Test status
Simulation time 19097072 ps
CPU time 0.55 seconds
Started Aug 18 05:41:03 PM PDT 24
Finished Aug 18 05:41:04 PM PDT 24
Peak memory 194780 kb
Host smart-69f77068-5dfb-4d9a-b26b-cdf6c0828635
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111802853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.1111802853
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.272641618
Short name T597
Test name
Test status
Simulation time 22502022 ps
CPU time 0.6 seconds
Started Aug 18 05:41:04 PM PDT 24
Finished Aug 18 05:41:05 PM PDT 24
Peak memory 194732 kb
Host smart-bfd6251a-5b33-475d-8c62-cf5c967ed617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272641618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.272641618
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.1090681253
Short name T570
Test name
Test status
Simulation time 2106041660 ps
CPU time 23.23 seconds
Started Aug 18 05:41:00 PM PDT 24
Finished Aug 18 05:41:23 PM PDT 24
Peak memory 197040 kb
Host smart-0c077f13-07ef-4a25-a0b3-c0450538cb33
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090681253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.1090681253
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.2618402900
Short name T673
Test name
Test status
Simulation time 386279562 ps
CPU time 1.03 seconds
Started Aug 18 05:40:58 PM PDT 24
Finished Aug 18 05:40:59 PM PDT 24
Peak memory 196676 kb
Host smart-6dfbfdab-e64a-4e82-ba72-c727ecd38d5f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618402900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.2618402900
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.1472404735
Short name T575
Test name
Test status
Simulation time 308479776 ps
CPU time 1.32 seconds
Started Aug 18 05:40:48 PM PDT 24
Finished Aug 18 05:40:50 PM PDT 24
Peak memory 198232 kb
Host smart-7f35c846-e791-494a-ad5d-c9a82ab28440
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472404735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.1472404735
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.3091269748
Short name T685
Test name
Test status
Simulation time 202585458 ps
CPU time 1.53 seconds
Started Aug 18 05:40:49 PM PDT 24
Finished Aug 18 05:40:51 PM PDT 24
Peak memory 196164 kb
Host smart-7c817615-e4f1-411e-897a-2c326cd8c6ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091269748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.3091269748
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.1764018849
Short name T259
Test name
Test status
Simulation time 642987691 ps
CPU time 1.13 seconds
Started Aug 18 05:41:01 PM PDT 24
Finished Aug 18 05:41:03 PM PDT 24
Peak memory 196720 kb
Host smart-00fd6d03-02a8-49d0-afa7-c34fcb82aff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764018849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.1764018849
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.4078439199
Short name T150
Test name
Test status
Simulation time 51281783 ps
CPU time 1.14 seconds
Started Aug 18 05:40:48 PM PDT 24
Finished Aug 18 05:40:49 PM PDT 24
Peak memory 196772 kb
Host smart-2093568b-d883-479c-a802-78933c49ab56
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078439199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.4078439199
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.2623340509
Short name T38
Test name
Test status
Simulation time 180244334 ps
CPU time 4.18 seconds
Started Aug 18 05:40:59 PM PDT 24
Finished Aug 18 05:41:03 PM PDT 24
Peak memory 198160 kb
Host smart-0212373a-b42d-41f4-a801-6edf3ae46321
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623340509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.2623340509
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.3124241216
Short name T496
Test name
Test status
Simulation time 167822609 ps
CPU time 1.3 seconds
Started Aug 18 05:40:54 PM PDT 24
Finished Aug 18 05:40:56 PM PDT 24
Peak memory 196516 kb
Host smart-5378448f-65c5-4943-a683-f49021aad3ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124241216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.3124241216
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.1385706937
Short name T326
Test name
Test status
Simulation time 32692821 ps
CPU time 0.88 seconds
Started Aug 18 05:41:01 PM PDT 24
Finished Aug 18 05:41:02 PM PDT 24
Peak memory 195612 kb
Host smart-0676f59b-7ff2-4e52-a05b-43cb2d6267db
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385706937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.1385706937
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.2157840813
Short name T208
Test name
Test status
Simulation time 39483355260 ps
CPU time 94.84 seconds
Started Aug 18 05:40:56 PM PDT 24
Finished Aug 18 05:42:31 PM PDT 24
Peak memory 198476 kb
Host smart-e21ef302-8e90-408c-be58-8f179637c9c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157840813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.2157840813
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_alert_test.2844378069
Short name T483
Test name
Test status
Simulation time 24643856 ps
CPU time 0.6 seconds
Started Aug 18 05:40:53 PM PDT 24
Finished Aug 18 05:40:53 PM PDT 24
Peak memory 194700 kb
Host smart-9ce7f335-abac-4304-af8a-f334a935c048
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844378069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.2844378069
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.938711359
Short name T15
Test name
Test status
Simulation time 47357791 ps
CPU time 0.96 seconds
Started Aug 18 05:40:51 PM PDT 24
Finished Aug 18 05:40:52 PM PDT 24
Peak memory 196764 kb
Host smart-323c5ac4-f8a7-45c6-8878-ef5bdee151a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938711359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.938711359
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.4266281445
Short name T556
Test name
Test status
Simulation time 8855392798 ps
CPU time 23.15 seconds
Started Aug 18 05:40:49 PM PDT 24
Finished Aug 18 05:41:12 PM PDT 24
Peak memory 198312 kb
Host smart-dfd0e31a-dcc8-4b2d-93a4-21565944655e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266281445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.4266281445
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.2491719238
Short name T542
Test name
Test status
Simulation time 286481462 ps
CPU time 0.91 seconds
Started Aug 18 05:40:53 PM PDT 24
Finished Aug 18 05:40:54 PM PDT 24
Peak memory 196592 kb
Host smart-5da199e7-fc34-4979-b93f-d035a8bb3a45
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491719238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.2491719238
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.3465041799
Short name T343
Test name
Test status
Simulation time 506829314 ps
CPU time 1.22 seconds
Started Aug 18 05:41:20 PM PDT 24
Finished Aug 18 05:41:21 PM PDT 24
Peak memory 196312 kb
Host smart-ca7137ae-1c48-451c-b001-0537079d0918
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465041799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.3465041799
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.3194903114
Short name T217
Test name
Test status
Simulation time 26084247 ps
CPU time 1.13 seconds
Started Aug 18 05:40:49 PM PDT 24
Finished Aug 18 05:40:51 PM PDT 24
Peak memory 197624 kb
Host smart-12d8afdf-6c46-4125-9e89-2c5a368effc8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194903114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.3194903114
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.1306380535
Short name T421
Test name
Test status
Simulation time 156076922 ps
CPU time 1.67 seconds
Started Aug 18 05:41:11 PM PDT 24
Finished Aug 18 05:41:17 PM PDT 24
Peak memory 196328 kb
Host smart-576f0abd-bef2-4f80-a198-b6a576a508e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306380535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.1306380535
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.3910772505
Short name T258
Test name
Test status
Simulation time 22306682 ps
CPU time 0.66 seconds
Started Aug 18 05:41:09 PM PDT 24
Finished Aug 18 05:41:15 PM PDT 24
Peak memory 194444 kb
Host smart-6bf3c1d2-49ab-4463-9ecd-64109d5ee8e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910772505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.3910772505
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.3196320011
Short name T501
Test name
Test status
Simulation time 18270594 ps
CPU time 0.73 seconds
Started Aug 18 05:40:54 PM PDT 24
Finished Aug 18 05:40:55 PM PDT 24
Peak memory 195556 kb
Host smart-f974f6c0-eba7-4d7d-81e8-e2f846263d0d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196320011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullu
p_pulldown.3196320011
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.2174326783
Short name T9
Test name
Test status
Simulation time 450347087 ps
CPU time 4.96 seconds
Started Aug 18 05:41:04 PM PDT 24
Finished Aug 18 05:41:09 PM PDT 24
Peak memory 198204 kb
Host smart-be3a5cf3-564a-4ef5-8883-467ddcf5ebff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174326783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.2174326783
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.490185021
Short name T70
Test name
Test status
Simulation time 181308477 ps
CPU time 1.28 seconds
Started Aug 18 05:40:46 PM PDT 24
Finished Aug 18 05:40:48 PM PDT 24
Peak memory 195676 kb
Host smart-42907178-3cef-4f5b-802e-afd1ee43b36d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490185021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.490185021
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.3873137243
Short name T335
Test name
Test status
Simulation time 159659660 ps
CPU time 0.86 seconds
Started Aug 18 05:40:57 PM PDT 24
Finished Aug 18 05:40:58 PM PDT 24
Peak memory 196548 kb
Host smart-346a5598-207a-4d73-834e-b8afd780f6ef
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873137243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.3873137243
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.4224312001
Short name T388
Test name
Test status
Simulation time 19984807359 ps
CPU time 82.38 seconds
Started Aug 18 05:40:56 PM PDT 24
Finished Aug 18 05:42:18 PM PDT 24
Peak memory 198364 kb
Host smart-c4b1891a-6c80-4e22-81dc-15310d1db512
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224312001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.4224312001
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_alert_test.2505757678
Short name T166
Test name
Test status
Simulation time 13570599 ps
CPU time 0.57 seconds
Started Aug 18 05:41:30 PM PDT 24
Finished Aug 18 05:41:30 PM PDT 24
Peak memory 192800 kb
Host smart-95372d32-9b5f-4918-b90e-52ef4080faaa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505757678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.2505757678
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.1754728769
Short name T265
Test name
Test status
Simulation time 116787714 ps
CPU time 0.79 seconds
Started Aug 18 05:41:11 PM PDT 24
Finished Aug 18 05:41:11 PM PDT 24
Peak memory 195516 kb
Host smart-d047600b-0491-4061-90de-6c9f52cad473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754728769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.1754728769
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.8043381
Short name T695
Test name
Test status
Simulation time 158253512 ps
CPU time 8.03 seconds
Started Aug 18 05:40:57 PM PDT 24
Finished Aug 18 05:41:06 PM PDT 24
Peak memory 198148 kb
Host smart-afca4ae7-c7ab-4529-9253-68e102079cf6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8043381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_s
tress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stress.8043381
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.2971283097
Short name T20
Test name
Test status
Simulation time 99473864 ps
CPU time 0.8 seconds
Started Aug 18 05:41:00 PM PDT 24
Finished Aug 18 05:41:00 PM PDT 24
Peak memory 196012 kb
Host smart-b54579cc-db58-480c-adce-2be7996e8b48
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971283097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.2971283097
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.234364985
Short name T140
Test name
Test status
Simulation time 286112695 ps
CPU time 1.05 seconds
Started Aug 18 05:41:06 PM PDT 24
Finished Aug 18 05:41:07 PM PDT 24
Peak memory 195936 kb
Host smart-fd3b8eda-3789-4d7c-8f66-d4e996c2fa7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234364985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.234364985
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.3901226096
Short name T107
Test name
Test status
Simulation time 184732849 ps
CPU time 3.57 seconds
Started Aug 18 05:41:01 PM PDT 24
Finished Aug 18 05:41:04 PM PDT 24
Peak memory 198220 kb
Host smart-fe626f7a-b83b-439d-a081-81f4dc8e23ee
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901226096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.3901226096
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.3923636178
Short name T221
Test name
Test status
Simulation time 48599751 ps
CPU time 1.48 seconds
Started Aug 18 05:41:04 PM PDT 24
Finished Aug 18 05:41:05 PM PDT 24
Peak memory 196644 kb
Host smart-10306967-0567-4cb7-a2b9-0a0c82d0bf48
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923636178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.3923636178
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.3903901997
Short name T526
Test name
Test status
Simulation time 70602591 ps
CPU time 0.91 seconds
Started Aug 18 05:40:57 PM PDT 24
Finished Aug 18 05:40:58 PM PDT 24
Peak memory 196116 kb
Host smart-f2adbf8e-9186-48b6-887a-2cc8689072fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903901997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.3903901997
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.1606674179
Short name T127
Test name
Test status
Simulation time 62097913 ps
CPU time 1.28 seconds
Started Aug 18 05:41:06 PM PDT 24
Finished Aug 18 05:41:07 PM PDT 24
Peak memory 198220 kb
Host smart-249d122e-d0be-400b-8504-2600af2a2990
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606674179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.1606674179
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.1505314837
Short name T21
Test name
Test status
Simulation time 310339099 ps
CPU time 3.69 seconds
Started Aug 18 05:41:39 PM PDT 24
Finished Aug 18 05:41:43 PM PDT 24
Peak memory 198128 kb
Host smart-46559434-ea1c-4078-9abd-85fcf3fd643a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505314837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.1505314837
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.2437105934
Short name T473
Test name
Test status
Simulation time 35281455 ps
CPU time 1.06 seconds
Started Aug 18 05:40:58 PM PDT 24
Finished Aug 18 05:40:59 PM PDT 24
Peak memory 196684 kb
Host smart-0830ed45-7317-406c-8055-cf2defa519d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437105934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.2437105934
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.3379127484
Short name T192
Test name
Test status
Simulation time 40353625 ps
CPU time 1.08 seconds
Started Aug 18 05:41:11 PM PDT 24
Finished Aug 18 05:41:12 PM PDT 24
Peak memory 195996 kb
Host smart-a3c1450a-3ec2-418b-b1c4-fe409f481f8a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379127484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.3379127484
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.4002103747
Short name T363
Test name
Test status
Simulation time 17820982934 ps
CPU time 184.91 seconds
Started Aug 18 05:41:06 PM PDT 24
Finished Aug 18 05:44:11 PM PDT 24
Peak memory 198348 kb
Host smart-2ad88c30-fe7d-4872-b1a5-6fcc2ff84328
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002103747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.4002103747
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_alert_test.4147893611
Short name T215
Test name
Test status
Simulation time 25458667 ps
CPU time 0.6 seconds
Started Aug 18 05:41:23 PM PDT 24
Finished Aug 18 05:41:24 PM PDT 24
Peak memory 194224 kb
Host smart-faadf8f8-c54f-45e3-a23a-d026e84c1a49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147893611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.4147893611
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.903740958
Short name T384
Test name
Test status
Simulation time 37325265 ps
CPU time 0.73 seconds
Started Aug 18 05:41:12 PM PDT 24
Finished Aug 18 05:41:13 PM PDT 24
Peak memory 196016 kb
Host smart-28a7d79d-39a5-446d-bbe0-2810e828e749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903740958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.903740958
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.390181442
Short name T280
Test name
Test status
Simulation time 614309420 ps
CPU time 18.89 seconds
Started Aug 18 05:40:53 PM PDT 24
Finished Aug 18 05:41:12 PM PDT 24
Peak memory 198156 kb
Host smart-c2c7b334-7605-4d50-baef-6983775c470b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390181442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stres
s.390181442
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.3405808910
Short name T416
Test name
Test status
Simulation time 239003855 ps
CPU time 0.68 seconds
Started Aug 18 05:41:37 PM PDT 24
Finished Aug 18 05:41:38 PM PDT 24
Peak memory 194756 kb
Host smart-2ca7abc2-8a55-4453-b46b-8aee69a98908
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405808910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.3405808910
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.4095122634
Short name T260
Test name
Test status
Simulation time 52664959 ps
CPU time 0.82 seconds
Started Aug 18 05:41:23 PM PDT 24
Finished Aug 18 05:41:23 PM PDT 24
Peak memory 195640 kb
Host smart-8d2ea1cc-0cf8-477d-811a-6a4abcd2dd88
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095122634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.4095122634
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.247226557
Short name T131
Test name
Test status
Simulation time 33309589 ps
CPU time 0.9 seconds
Started Aug 18 05:41:05 PM PDT 24
Finished Aug 18 05:41:06 PM PDT 24
Peak memory 196760 kb
Host smart-fbd185b4-caf0-4c96-b9a7-cf8ca25f4c44
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247226557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 26.gpio_intr_with_filter_rand_intr_event.247226557
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.2209533060
Short name T437
Test name
Test status
Simulation time 107083381 ps
CPU time 3.07 seconds
Started Aug 18 05:40:58 PM PDT 24
Finished Aug 18 05:41:01 PM PDT 24
Peak memory 197256 kb
Host smart-5b50ce54-9177-447f-b4c0-47027de2134a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209533060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.2209533060
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.2226246157
Short name T236
Test name
Test status
Simulation time 51620853 ps
CPU time 1.1 seconds
Started Aug 18 05:41:19 PM PDT 24
Finished Aug 18 05:41:25 PM PDT 24
Peak memory 196064 kb
Host smart-c3f44ce9-8634-47ce-8515-33552c4e5c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226246157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.2226246157
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.224488477
Short name T320
Test name
Test status
Simulation time 22036778 ps
CPU time 0.85 seconds
Started Aug 18 05:40:49 PM PDT 24
Finished Aug 18 05:40:50 PM PDT 24
Peak memory 196736 kb
Host smart-e7aee5f3-74ab-4548-8a92-ac03658da5be
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224488477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullup
_pulldown.224488477
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.1706705589
Short name T540
Test name
Test status
Simulation time 217177257 ps
CPU time 2.76 seconds
Started Aug 18 05:41:14 PM PDT 24
Finished Aug 18 05:41:17 PM PDT 24
Peak memory 197212 kb
Host smart-88a31bd9-1c55-43ba-aff6-c1a46479cae4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706705589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.1706705589
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.4117102399
Short name T682
Test name
Test status
Simulation time 73032824 ps
CPU time 1.24 seconds
Started Aug 18 05:41:29 PM PDT 24
Finished Aug 18 05:41:30 PM PDT 24
Peak memory 196520 kb
Host smart-ee6057b7-5661-4080-8980-a6ce2a1b6773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117102399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.4117102399
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.2701380656
Short name T346
Test name
Test status
Simulation time 49580179 ps
CPU time 0.93 seconds
Started Aug 18 05:41:08 PM PDT 24
Finished Aug 18 05:41:09 PM PDT 24
Peak memory 196484 kb
Host smart-1b208762-ae5c-48eb-8040-cd30e91df861
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701380656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.2701380656
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.4176450472
Short name T655
Test name
Test status
Simulation time 10851977147 ps
CPU time 34.27 seconds
Started Aug 18 05:41:08 PM PDT 24
Finished Aug 18 05:41:42 PM PDT 24
Peak memory 198376 kb
Host smart-50f75caf-c50d-47a8-b593-d5879a25537c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176450472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.4176450472
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_stress_all_with_rand_reset.241485130
Short name T460
Test name
Test status
Simulation time 6757859848 ps
CPU time 220.14 seconds
Started Aug 18 05:41:32 PM PDT 24
Finished Aug 18 05:45:12 PM PDT 24
Peak memory 198508 kb
Host smart-73767cf2-ec0d-4bf0-8fc0-4a5e4acbd2c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=241485130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_stress_all_with_rand_reset.241485130
Directory /workspace/26.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.gpio_alert_test.873444782
Short name T466
Test name
Test status
Simulation time 13296126 ps
CPU time 0.54 seconds
Started Aug 18 05:40:58 PM PDT 24
Finished Aug 18 05:40:58 PM PDT 24
Peak memory 193984 kb
Host smart-ba078942-2589-4c00-892a-f3658f13adf0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873444782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.873444782
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.1368844801
Short name T357
Test name
Test status
Simulation time 18672379 ps
CPU time 0.66 seconds
Started Aug 18 05:41:53 PM PDT 24
Finished Aug 18 05:41:54 PM PDT 24
Peak memory 194968 kb
Host smart-79f4f7a7-3480-4680-9090-37845c6e0b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368844801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.1368844801
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.169880625
Short name T322
Test name
Test status
Simulation time 555059012 ps
CPU time 14.13 seconds
Started Aug 18 05:40:53 PM PDT 24
Finished Aug 18 05:41:07 PM PDT 24
Peak memory 197000 kb
Host smart-5bc47720-337a-4253-a03d-78d8f819b863
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169880625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stres
s.169880625
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.848949049
Short name T142
Test name
Test status
Simulation time 105737842 ps
CPU time 0.65 seconds
Started Aug 18 05:41:13 PM PDT 24
Finished Aug 18 05:41:14 PM PDT 24
Peak memory 194628 kb
Host smart-e5a2ddca-20b3-4022-a417-dbef5778809b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848949049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.848949049
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.2898612570
Short name T231
Test name
Test status
Simulation time 54747303 ps
CPU time 1.39 seconds
Started Aug 18 05:41:02 PM PDT 24
Finished Aug 18 05:41:04 PM PDT 24
Peak memory 198196 kb
Host smart-d7953b33-136d-459a-b877-d8882e6ed709
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898612570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.2898612570
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.802897409
Short name T194
Test name
Test status
Simulation time 58911547 ps
CPU time 2.33 seconds
Started Aug 18 05:41:22 PM PDT 24
Finished Aug 18 05:41:25 PM PDT 24
Peak memory 198208 kb
Host smart-d8fc635f-aca4-4d34-95bf-05186f3aaab3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802897409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 27.gpio_intr_with_filter_rand_intr_event.802897409
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.2460653540
Short name T662
Test name
Test status
Simulation time 1647262843 ps
CPU time 3.4 seconds
Started Aug 18 05:41:22 PM PDT 24
Finished Aug 18 05:41:26 PM PDT 24
Peak memory 197308 kb
Host smart-2a2d47c6-fa5d-4257-a487-04a452edd8ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460653540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.2460653540
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.2669802398
Short name T213
Test name
Test status
Simulation time 26805221 ps
CPU time 0.92 seconds
Started Aug 18 05:40:50 PM PDT 24
Finished Aug 18 05:40:51 PM PDT 24
Peak memory 196012 kb
Host smart-181c841a-57dd-4b99-971a-928eb64fe6cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669802398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.2669802398
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.2255069958
Short name T623
Test name
Test status
Simulation time 74017866 ps
CPU time 0.74 seconds
Started Aug 18 05:40:51 PM PDT 24
Finished Aug 18 05:40:52 PM PDT 24
Peak memory 194288 kb
Host smart-ce910922-9899-4f29-99b6-dbd28c46f6fa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255069958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.2255069958
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.3159443081
Short name T567
Test name
Test status
Simulation time 183712453 ps
CPU time 2.34 seconds
Started Aug 18 05:40:57 PM PDT 24
Finished Aug 18 05:40:59 PM PDT 24
Peak memory 198144 kb
Host smart-d1c641d3-b37a-44f1-811f-fd422cc4e839
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159443081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.3159443081
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.2879607259
Short name T404
Test name
Test status
Simulation time 61153383 ps
CPU time 1.22 seconds
Started Aug 18 05:41:01 PM PDT 24
Finished Aug 18 05:41:02 PM PDT 24
Peak memory 196452 kb
Host smart-85b09bff-d125-4f5a-851d-a839fc47122b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879607259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.2879607259
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.1391345542
Short name T313
Test name
Test status
Simulation time 26188262 ps
CPU time 0.84 seconds
Started Aug 18 05:41:05 PM PDT 24
Finished Aug 18 05:41:06 PM PDT 24
Peak memory 197184 kb
Host smart-2d337532-137c-47a6-a345-453eb32dae10
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391345542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.1391345542
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.3494325514
Short name T114
Test name
Test status
Simulation time 5896380554 ps
CPU time 72.7 seconds
Started Aug 18 05:41:02 PM PDT 24
Finished Aug 18 05:42:14 PM PDT 24
Peak memory 198384 kb
Host smart-5dda0f10-1795-440a-bb2c-84f3067a7a63
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494325514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.3494325514
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_alert_test.2747340726
Short name T271
Test name
Test status
Simulation time 25386077 ps
CPU time 0.59 seconds
Started Aug 18 05:41:13 PM PDT 24
Finished Aug 18 05:41:13 PM PDT 24
Peak memory 194956 kb
Host smart-5aea5367-4022-48a2-85ba-b448947ed1d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747340726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.2747340726
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.826350963
Short name T687
Test name
Test status
Simulation time 58093661 ps
CPU time 0.61 seconds
Started Aug 18 05:41:04 PM PDT 24
Finished Aug 18 05:41:05 PM PDT 24
Peak memory 194132 kb
Host smart-6e31b239-0e8c-494c-a310-355cf7f43f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826350963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.826350963
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.2419134862
Short name T521
Test name
Test status
Simulation time 736433545 ps
CPU time 19.96 seconds
Started Aug 18 05:40:58 PM PDT 24
Finished Aug 18 05:41:18 PM PDT 24
Peak memory 197236 kb
Host smart-817331b3-191f-43dd-89d1-d65db130401a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419134862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.2419134862
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.3007080880
Short name T372
Test name
Test status
Simulation time 39212150 ps
CPU time 0.77 seconds
Started Aug 18 05:41:08 PM PDT 24
Finished Aug 18 05:41:09 PM PDT 24
Peak memory 195988 kb
Host smart-febabad5-1e9b-49a5-a9b3-2e6d7e6bd512
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007080880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.3007080880
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.3895801778
Short name T227
Test name
Test status
Simulation time 311076850 ps
CPU time 1.23 seconds
Started Aug 18 05:41:21 PM PDT 24
Finished Aug 18 05:41:22 PM PDT 24
Peak memory 196744 kb
Host smart-21060e3d-a0d2-4f30-a3ab-e5fc23238bfd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895801778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.3895801778
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.3747808481
Short name T657
Test name
Test status
Simulation time 131088244 ps
CPU time 2.54 seconds
Started Aug 18 05:41:05 PM PDT 24
Finished Aug 18 05:41:08 PM PDT 24
Peak memory 198224 kb
Host smart-124ff64c-71b1-421e-8db3-3efff24e350c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747808481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.3747808481
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.4052741751
Short name T505
Test name
Test status
Simulation time 204425667 ps
CPU time 2.78 seconds
Started Aug 18 05:41:05 PM PDT 24
Finished Aug 18 05:41:08 PM PDT 24
Peak memory 195932 kb
Host smart-0fc94ad9-69c4-440c-80d3-585bac34b838
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052741751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.4052741751
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.3773094936
Short name T583
Test name
Test status
Simulation time 59254567 ps
CPU time 1.04 seconds
Started Aug 18 05:41:05 PM PDT 24
Finished Aug 18 05:41:06 PM PDT 24
Peak memory 196240 kb
Host smart-6bf5aff2-a426-428a-a546-92bb1525345c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773094936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.3773094936
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.2184144258
Short name T632
Test name
Test status
Simulation time 100481025 ps
CPU time 0.98 seconds
Started Aug 18 05:41:20 PM PDT 24
Finished Aug 18 05:41:21 PM PDT 24
Peak memory 195976 kb
Host smart-e529cc2c-fe15-4523-b752-65a92cc28092
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184144258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.2184144258
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.2679250441
Short name T612
Test name
Test status
Simulation time 947574224 ps
CPU time 4.1 seconds
Started Aug 18 05:40:58 PM PDT 24
Finished Aug 18 05:41:02 PM PDT 24
Peak memory 198128 kb
Host smart-cb67924c-d5ff-4925-b147-1d0dce5cba31
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679250441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.2679250441
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.2441957062
Short name T476
Test name
Test status
Simulation time 181338916 ps
CPU time 0.95 seconds
Started Aug 18 05:41:39 PM PDT 24
Finished Aug 18 05:41:40 PM PDT 24
Peak memory 196480 kb
Host smart-6b5362fa-0cfc-4f65-a067-d936f90a85e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441957062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.2441957062
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.2804323155
Short name T156
Test name
Test status
Simulation time 126132649 ps
CPU time 0.87 seconds
Started Aug 18 05:41:05 PM PDT 24
Finished Aug 18 05:41:06 PM PDT 24
Peak memory 195380 kb
Host smart-9fdf61fb-1bbb-4144-afe3-d43523ced5d2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804323155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.2804323155
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.914112520
Short name T457
Test name
Test status
Simulation time 12594527460 ps
CPU time 125.71 seconds
Started Aug 18 05:40:51 PM PDT 24
Finished Aug 18 05:42:57 PM PDT 24
Peak memory 198364 kb
Host smart-5117d846-03a8-43f2-b306-c052f07cc091
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914112520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.g
pio_stress_all.914112520
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_alert_test.1117552839
Short name T415
Test name
Test status
Simulation time 46072937 ps
CPU time 0.55 seconds
Started Aug 18 05:40:52 PM PDT 24
Finished Aug 18 05:40:53 PM PDT 24
Peak memory 194024 kb
Host smart-0feb672c-5885-4232-9991-c4a3ad6229ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117552839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.1117552839
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.2775286441
Short name T383
Test name
Test status
Simulation time 82730852 ps
CPU time 0.9 seconds
Started Aug 18 05:41:20 PM PDT 24
Finished Aug 18 05:41:21 PM PDT 24
Peak memory 196032 kb
Host smart-6ad71847-f0e1-4831-b11e-5e4ecdf21bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775286441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.2775286441
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.4039844183
Short name T193
Test name
Test status
Simulation time 515354878 ps
CPU time 7.58 seconds
Started Aug 18 05:41:54 PM PDT 24
Finished Aug 18 05:42:02 PM PDT 24
Peak memory 198188 kb
Host smart-1521d2d5-1e97-4dfb-a9ad-e79dbc15580b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039844183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.4039844183
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.4141863714
Short name T144
Test name
Test status
Simulation time 20544484 ps
CPU time 0.66 seconds
Started Aug 18 05:41:11 PM PDT 24
Finished Aug 18 05:41:12 PM PDT 24
Peak memory 194728 kb
Host smart-87fa4f22-8537-4647-a54a-3b4cd7df97d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141863714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.4141863714
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.2416005017
Short name T486
Test name
Test status
Simulation time 230594352 ps
CPU time 1.05 seconds
Started Aug 18 05:40:59 PM PDT 24
Finished Aug 18 05:41:01 PM PDT 24
Peak memory 196204 kb
Host smart-e21e1e92-0c9e-47b8-a814-ba7ab4adf005
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416005017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.2416005017
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.1522710523
Short name T563
Test name
Test status
Simulation time 94165749 ps
CPU time 1.12 seconds
Started Aug 18 05:41:24 PM PDT 24
Finished Aug 18 05:41:25 PM PDT 24
Peak memory 197952 kb
Host smart-497799fd-65be-45ad-9b1a-f246daf4be6f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522710523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.1522710523
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.2402382439
Short name T422
Test name
Test status
Simulation time 43292059 ps
CPU time 1.36 seconds
Started Aug 18 05:41:06 PM PDT 24
Finished Aug 18 05:41:08 PM PDT 24
Peak memory 196836 kb
Host smart-cb6596f6-3d65-4e9a-9263-81a8f2298ace
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402382439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.2402382439
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.2995757324
Short name T494
Test name
Test status
Simulation time 69342804 ps
CPU time 0.72 seconds
Started Aug 18 05:41:28 PM PDT 24
Finished Aug 18 05:41:28 PM PDT 24
Peak memory 195428 kb
Host smart-f08620ca-7177-48ec-8b3b-ffac18a87f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995757324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.2995757324
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.3250453061
Short name T573
Test name
Test status
Simulation time 186519608 ps
CPU time 1.12 seconds
Started Aug 18 05:40:54 PM PDT 24
Finished Aug 18 05:40:55 PM PDT 24
Peak memory 197184 kb
Host smart-575083f7-8f7b-4710-84d6-d722e080d793
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250453061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.3250453061
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.315423262
Short name T701
Test name
Test status
Simulation time 1557211057 ps
CPU time 5.7 seconds
Started Aug 18 05:41:25 PM PDT 24
Finished Aug 18 05:41:31 PM PDT 24
Peak memory 198116 kb
Host smart-10c9f1d5-3fa4-43e3-80e5-3862281b76b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315423262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ran
dom_long_reg_writes_reg_reads.315423262
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.603057574
Short name T420
Test name
Test status
Simulation time 253222926 ps
CPU time 1 seconds
Started Aug 18 05:41:05 PM PDT 24
Finished Aug 18 05:41:06 PM PDT 24
Peak memory 195732 kb
Host smart-35c6b99f-4dc0-4dbc-9abf-dbae2087f1bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603057574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.603057574
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.3409611523
Short name T393
Test name
Test status
Simulation time 58214923 ps
CPU time 1.08 seconds
Started Aug 18 05:40:52 PM PDT 24
Finished Aug 18 05:40:53 PM PDT 24
Peak memory 195704 kb
Host smart-0128e074-9ddd-46e4-86ad-f44d5ae2d9a3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409611523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.3409611523
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.4207438995
Short name T683
Test name
Test status
Simulation time 7285189719 ps
CPU time 184.9 seconds
Started Aug 18 05:41:21 PM PDT 24
Finished Aug 18 05:44:31 PM PDT 24
Peak memory 198348 kb
Host smart-f565cda9-dcac-4d66-be4c-bb6e8dabb83d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207438995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.4207438995
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_stress_all_with_rand_reset.635108011
Short name T31
Test name
Test status
Simulation time 2785635612 ps
CPU time 87.6 seconds
Started Aug 18 05:41:13 PM PDT 24
Finished Aug 18 05:42:41 PM PDT 24
Peak memory 198544 kb
Host smart-0377ed2e-fdf7-4d58-ba95-052c99566225
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=635108011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_stress_all_with_rand_reset.635108011
Directory /workspace/29.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.gpio_alert_test.741740947
Short name T550
Test name
Test status
Simulation time 20421994 ps
CPU time 0.57 seconds
Started Aug 18 05:40:30 PM PDT 24
Finished Aug 18 05:40:30 PM PDT 24
Peak memory 194020 kb
Host smart-40ac6bc5-039f-40e2-b350-1631d2dc3821
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741740947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.741740947
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.3802174854
Short name T112
Test name
Test status
Simulation time 20934789 ps
CPU time 0.7 seconds
Started Aug 18 05:40:31 PM PDT 24
Finished Aug 18 05:40:32 PM PDT 24
Peak memory 195388 kb
Host smart-1b196fc3-4cd2-4e31-9c49-44e6b9de2004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802174854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.3802174854
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.1900386272
Short name T149
Test name
Test status
Simulation time 701729968 ps
CPU time 19.95 seconds
Started Aug 18 05:40:27 PM PDT 24
Finished Aug 18 05:40:53 PM PDT 24
Peak memory 198160 kb
Host smart-48682167-ee7f-400e-83cc-2df220f4886e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900386272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.1900386272
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.3222007998
Short name T593
Test name
Test status
Simulation time 34746015 ps
CPU time 0.74 seconds
Started Aug 18 05:40:40 PM PDT 24
Finished Aug 18 05:40:40 PM PDT 24
Peak memory 194864 kb
Host smart-1793b26c-9e54-4b58-bd22-c3c69ea8cb6d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222007998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.3222007998
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.2298426549
Short name T185
Test name
Test status
Simulation time 30330940 ps
CPU time 0.89 seconds
Started Aug 18 05:40:11 PM PDT 24
Finished Aug 18 05:40:13 PM PDT 24
Peak memory 196784 kb
Host smart-1020ce2b-45b7-4fa8-b93a-55210fbc5e9b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298426549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.2298426549
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.388449187
Short name T12
Test name
Test status
Simulation time 88161223 ps
CPU time 3.63 seconds
Started Aug 18 05:40:34 PM PDT 24
Finished Aug 18 05:40:38 PM PDT 24
Peak memory 196460 kb
Host smart-59384976-9561-476b-a680-92ef09ed07c6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388449187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.gpio_intr_with_filter_rand_intr_event.388449187
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.2203312286
Short name T412
Test name
Test status
Simulation time 123278392 ps
CPU time 1.85 seconds
Started Aug 18 05:40:20 PM PDT 24
Finished Aug 18 05:40:22 PM PDT 24
Peak memory 196864 kb
Host smart-87cccb5d-1dec-4d80-b448-ac1e65b0b68d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203312286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
2203312286
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.550679226
Short name T672
Test name
Test status
Simulation time 242182701 ps
CPU time 1.18 seconds
Started Aug 18 05:40:15 PM PDT 24
Finished Aug 18 05:40:17 PM PDT 24
Peak memory 195964 kb
Host smart-247b27af-992a-463b-b032-a548e8e100ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550679226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.550679226
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.3958492291
Short name T333
Test name
Test status
Simulation time 41447990 ps
CPU time 0.87 seconds
Started Aug 18 05:40:15 PM PDT 24
Finished Aug 18 05:40:16 PM PDT 24
Peak memory 196240 kb
Host smart-12fefe5c-bd8b-4e91-b2cd-05ea1d28d7b1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958492291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.3958492291
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.2078233100
Short name T696
Test name
Test status
Simulation time 426066285 ps
CPU time 5.33 seconds
Started Aug 18 05:40:27 PM PDT 24
Finished Aug 18 05:40:32 PM PDT 24
Peak memory 198116 kb
Host smart-90926114-cf14-4a7a-a52f-6840f4429b1b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078233100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.2078233100
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.3709364216
Short name T52
Test name
Test status
Simulation time 577538713 ps
CPU time 0.88 seconds
Started Aug 18 05:40:32 PM PDT 24
Finished Aug 18 05:40:34 PM PDT 24
Peak memory 214052 kb
Host smart-ec12548c-7c6b-4f0f-966e-a5565de40a4f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709364216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.3709364216
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.3114714590
Short name T305
Test name
Test status
Simulation time 99076913 ps
CPU time 0.9 seconds
Started Aug 18 05:40:28 PM PDT 24
Finished Aug 18 05:40:29 PM PDT 24
Peak memory 195612 kb
Host smart-dfae0861-0082-46d1-8906-c9122df755d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114714590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.3114714590
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.2706600042
Short name T176
Test name
Test status
Simulation time 32622058 ps
CPU time 0.91 seconds
Started Aug 18 05:40:21 PM PDT 24
Finished Aug 18 05:40:22 PM PDT 24
Peak memory 196304 kb
Host smart-64618fe5-a543-439f-b37f-8279d03a6277
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706600042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.2706600042
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.3665667864
Short name T713
Test name
Test status
Simulation time 7523855697 ps
CPU time 103.35 seconds
Started Aug 18 05:40:27 PM PDT 24
Finished Aug 18 05:42:11 PM PDT 24
Peak memory 198352 kb
Host smart-3828353b-e893-4579-8eeb-e6b9fefa9073
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665667864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.3665667864
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_stress_all_with_rand_reset.950354498
Short name T64
Test name
Test status
Simulation time 21123475326 ps
CPU time 168.14 seconds
Started Aug 18 05:40:51 PM PDT 24
Finished Aug 18 05:43:39 PM PDT 24
Peak memory 198556 kb
Host smart-8eff7b04-5137-4154-8a62-7d5b04749032
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=950354498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_stress_all_with_rand_reset.950354498
Directory /workspace/3.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.gpio_alert_test.4062403582
Short name T387
Test name
Test status
Simulation time 21013689 ps
CPU time 0.53 seconds
Started Aug 18 05:41:36 PM PDT 24
Finished Aug 18 05:41:37 PM PDT 24
Peak memory 193940 kb
Host smart-5fb6a8b3-4326-47c5-aad6-e3db5d77ef0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062403582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.4062403582
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.1554889797
Short name T199
Test name
Test status
Simulation time 101771782 ps
CPU time 0.83 seconds
Started Aug 18 05:41:32 PM PDT 24
Finished Aug 18 05:41:33 PM PDT 24
Peak memory 197156 kb
Host smart-c533c735-9e88-42f2-a824-e0e76ebfb44b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554889797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.1554889797
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.1552992452
Short name T665
Test name
Test status
Simulation time 438898403 ps
CPU time 3.58 seconds
Started Aug 18 05:41:16 PM PDT 24
Finished Aug 18 05:41:24 PM PDT 24
Peak memory 196108 kb
Host smart-b139c730-c068-4dd4-8c58-ff35e7acb9c7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552992452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.1552992452
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.3084256912
Short name T493
Test name
Test status
Simulation time 150920458 ps
CPU time 0.74 seconds
Started Aug 18 05:41:04 PM PDT 24
Finished Aug 18 05:41:05 PM PDT 24
Peak memory 195584 kb
Host smart-8cfc12e9-1112-41e1-ad77-f3bb4f57c804
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084256912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.3084256912
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.1318663097
Short name T330
Test name
Test status
Simulation time 160939324 ps
CPU time 0.82 seconds
Started Aug 18 05:40:54 PM PDT 24
Finished Aug 18 05:40:55 PM PDT 24
Peak memory 195664 kb
Host smart-332ff924-1d09-4630-a9f2-ca020ce33d49
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318663097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.1318663097
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.411811914
Short name T619
Test name
Test status
Simulation time 140885611 ps
CPU time 1.53 seconds
Started Aug 18 05:41:10 PM PDT 24
Finished Aug 18 05:41:11 PM PDT 24
Peak memory 198064 kb
Host smart-034a8668-f4f1-4fa3-8c0d-91b049b17c8a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411811914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 30.gpio_intr_with_filter_rand_intr_event.411811914
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.615159244
Short name T450
Test name
Test status
Simulation time 726430394 ps
CPU time 2.51 seconds
Started Aug 18 05:41:19 PM PDT 24
Finished Aug 18 05:41:22 PM PDT 24
Peak memory 197340 kb
Host smart-059bc411-e974-438e-b580-215372c74aa6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615159244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger.
615159244
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.3514890513
Short name T292
Test name
Test status
Simulation time 77791641 ps
CPU time 1.2 seconds
Started Aug 18 05:41:33 PM PDT 24
Finished Aug 18 05:41:34 PM PDT 24
Peak memory 197272 kb
Host smart-d23bc61e-cc05-4db4-81ec-c54caf8aa3a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514890513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.3514890513
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.2212405283
Short name T253
Test name
Test status
Simulation time 34192567 ps
CPU time 1.23 seconds
Started Aug 18 05:41:22 PM PDT 24
Finished Aug 18 05:41:23 PM PDT 24
Peak memory 197184 kb
Host smart-4c55fdcf-a46e-455f-8c34-50db4e2a7211
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212405283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.2212405283
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.4107445976
Short name T661
Test name
Test status
Simulation time 86806869 ps
CPU time 3.99 seconds
Started Aug 18 05:41:11 PM PDT 24
Finished Aug 18 05:41:15 PM PDT 24
Peak memory 198128 kb
Host smart-eb522111-79dc-423a-8d25-7e3f9735d498
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107445976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.4107445976
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.3294251543
Short name T254
Test name
Test status
Simulation time 83877921 ps
CPU time 0.92 seconds
Started Aug 18 05:41:07 PM PDT 24
Finished Aug 18 05:41:08 PM PDT 24
Peak memory 196392 kb
Host smart-29099b65-c267-4ac0-b64d-cdbbdfec740c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294251543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.3294251543
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.2395343317
Short name T699
Test name
Test status
Simulation time 183235858 ps
CPU time 1.21 seconds
Started Aug 18 05:40:58 PM PDT 24
Finished Aug 18 05:40:59 PM PDT 24
Peak memory 196600 kb
Host smart-6e73a15d-a2b7-4d3a-8b4a-c5eaa71d9470
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395343317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.2395343317
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.3273333737
Short name T640
Test name
Test status
Simulation time 31845084283 ps
CPU time 76.01 seconds
Started Aug 18 05:41:16 PM PDT 24
Finished Aug 18 05:42:32 PM PDT 24
Peak memory 198324 kb
Host smart-102792fd-68a7-45ed-87ef-4f14d7472c40
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273333737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.3273333737
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_alert_test.1957388075
Short name T248
Test name
Test status
Simulation time 146222985 ps
CPU time 0.58 seconds
Started Aug 18 05:41:39 PM PDT 24
Finished Aug 18 05:41:39 PM PDT 24
Peak memory 195036 kb
Host smart-12206b29-6c67-4ed6-ac91-69a84da66303
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957388075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.1957388075
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.4210151426
Short name T396
Test name
Test status
Simulation time 99053619 ps
CPU time 0.86 seconds
Started Aug 18 05:41:39 PM PDT 24
Finished Aug 18 05:41:40 PM PDT 24
Peak memory 195864 kb
Host smart-b76fdd2c-da78-4965-a55c-89e4caa6cc78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210151426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.4210151426
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.282148336
Short name T368
Test name
Test status
Simulation time 9830369097 ps
CPU time 25.34 seconds
Started Aug 18 05:41:20 PM PDT 24
Finished Aug 18 05:41:45 PM PDT 24
Peak memory 197136 kb
Host smart-33fdbdf3-c5f1-4b20-b63f-8aef43063b85
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282148336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stres
s.282148336
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.1016413635
Short name T511
Test name
Test status
Simulation time 279097734 ps
CPU time 1 seconds
Started Aug 18 05:41:20 PM PDT 24
Finished Aug 18 05:41:21 PM PDT 24
Peak memory 196852 kb
Host smart-8a3b3e62-e3b8-4c50-8622-eff7f3cad253
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016413635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.1016413635
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.2923333775
Short name T72
Test name
Test status
Simulation time 257682903 ps
CPU time 1.22 seconds
Started Aug 18 05:41:31 PM PDT 24
Finished Aug 18 05:41:33 PM PDT 24
Peak memory 196956 kb
Host smart-8e0c8529-cd9d-43c9-8ab0-779a47419f57
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923333775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.2923333775
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.3822380968
Short name T571
Test name
Test status
Simulation time 84366071 ps
CPU time 3.22 seconds
Started Aug 18 05:41:04 PM PDT 24
Finished Aug 18 05:41:07 PM PDT 24
Peak memory 198184 kb
Host smart-a7b7bfdd-7f50-4dcd-8fa8-c28a7ab8dd80
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822380968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.3822380968
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.751254165
Short name T547
Test name
Test status
Simulation time 85629436 ps
CPU time 2.37 seconds
Started Aug 18 05:41:20 PM PDT 24
Finished Aug 18 05:41:23 PM PDT 24
Peak memory 197380 kb
Host smart-b30346cf-cd00-4b67-8ebd-8c56925a4bca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751254165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger.
751254165
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.1368769814
Short name T200
Test name
Test status
Simulation time 150633218 ps
CPU time 1.08 seconds
Started Aug 18 05:41:17 PM PDT 24
Finished Aug 18 05:41:18 PM PDT 24
Peak memory 196636 kb
Host smart-0de0de72-b4c2-45a4-a98f-026c691e78fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368769814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.1368769814
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.1317093518
Short name T577
Test name
Test status
Simulation time 555884942 ps
CPU time 1.2 seconds
Started Aug 18 05:41:28 PM PDT 24
Finished Aug 18 05:41:29 PM PDT 24
Peak memory 196012 kb
Host smart-4750bb2d-84cd-495b-82f1-96031b975397
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317093518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.1317093518
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.676674896
Short name T606
Test name
Test status
Simulation time 96758175 ps
CPU time 1.41 seconds
Started Aug 18 05:41:38 PM PDT 24
Finished Aug 18 05:41:40 PM PDT 24
Peak memory 198192 kb
Host smart-7da7872f-93c8-4846-96ef-e40c9763249d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676674896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ran
dom_long_reg_writes_reg_reads.676674896
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.3719543327
Short name T19
Test name
Test status
Simulation time 137032556 ps
CPU time 0.79 seconds
Started Aug 18 05:41:24 PM PDT 24
Finished Aug 18 05:41:25 PM PDT 24
Peak memory 196140 kb
Host smart-14e0bf32-ae37-4370-ae0c-92b83986a678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719543327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.3719543327
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.2295129056
Short name T123
Test name
Test status
Simulation time 30716203 ps
CPU time 0.89 seconds
Started Aug 18 05:41:36 PM PDT 24
Finished Aug 18 05:41:37 PM PDT 24
Peak memory 196324 kb
Host smart-22226d02-a81a-4078-a316-35afd598110b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295129056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.2295129056
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.3037641879
Short name T580
Test name
Test status
Simulation time 11525790897 ps
CPU time 164.7 seconds
Started Aug 18 05:41:24 PM PDT 24
Finished Aug 18 05:44:08 PM PDT 24
Peak memory 198320 kb
Host smart-63e466b5-6a43-49e2-9b0d-57c878eb5bdb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037641879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.3037641879
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_alert_test.148183106
Short name T471
Test name
Test status
Simulation time 11738537 ps
CPU time 0.55 seconds
Started Aug 18 05:41:15 PM PDT 24
Finished Aug 18 05:41:16 PM PDT 24
Peak memory 194060 kb
Host smart-dc0eb430-9b68-47bb-aad7-cc811f2a8d53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148183106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.148183106
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.113540098
Short name T445
Test name
Test status
Simulation time 86482458 ps
CPU time 0.71 seconds
Started Aug 18 05:41:17 PM PDT 24
Finished Aug 18 05:41:18 PM PDT 24
Peak memory 194256 kb
Host smart-c73ba788-cba8-4772-abad-36d4708c616b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113540098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.113540098
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.3501981789
Short name T693
Test name
Test status
Simulation time 454026681 ps
CPU time 23.9 seconds
Started Aug 18 05:41:03 PM PDT 24
Finished Aug 18 05:41:27 PM PDT 24
Peak memory 198152 kb
Host smart-af540530-cafa-45f4-ad2e-370a0d17e10b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501981789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.3501981789
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.3469071884
Short name T538
Test name
Test status
Simulation time 50921813 ps
CPU time 0.8 seconds
Started Aug 18 05:41:28 PM PDT 24
Finished Aug 18 05:41:29 PM PDT 24
Peak memory 196120 kb
Host smart-fb405a10-ae9a-49a9-ac9d-3c2250cb1e8b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469071884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.3469071884
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.1210189278
Short name T499
Test name
Test status
Simulation time 28403061 ps
CPU time 0.92 seconds
Started Aug 18 05:41:28 PM PDT 24
Finished Aug 18 05:41:29 PM PDT 24
Peak memory 197624 kb
Host smart-89cd404f-0931-43d7-b86f-6f7bb792fcc0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210189278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.1210189278
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.1092914955
Short name T293
Test name
Test status
Simulation time 486317863 ps
CPU time 1.22 seconds
Started Aug 18 05:41:38 PM PDT 24
Finished Aug 18 05:41:43 PM PDT 24
Peak memory 197888 kb
Host smart-442f26f3-8643-4b11-b21b-64bd0db0c727
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092914955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.1092914955
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.149851743
Short name T705
Test name
Test status
Simulation time 42749747 ps
CPU time 1.04 seconds
Started Aug 18 05:41:01 PM PDT 24
Finished Aug 18 05:41:02 PM PDT 24
Peak memory 195504 kb
Host smart-0fb44deb-0233-4c8f-991c-a7a86cef2fd0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149851743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger.
149851743
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.4078365467
Short name T568
Test name
Test status
Simulation time 40630529 ps
CPU time 0.69 seconds
Started Aug 18 05:41:22 PM PDT 24
Finished Aug 18 05:41:23 PM PDT 24
Peak memory 196108 kb
Host smart-97734613-a8a7-4519-b26d-b1528df985de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078365467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.4078365467
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.460755968
Short name T517
Test name
Test status
Simulation time 119499002 ps
CPU time 0.86 seconds
Started Aug 18 05:41:30 PM PDT 24
Finished Aug 18 05:41:31 PM PDT 24
Peak memory 196740 kb
Host smart-e42f2d78-9521-4f6d-bd7f-8d302acdaab8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460755968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullup
_pulldown.460755968
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.1840729349
Short name T298
Test name
Test status
Simulation time 35167655 ps
CPU time 1.62 seconds
Started Aug 18 05:41:02 PM PDT 24
Finished Aug 18 05:41:04 PM PDT 24
Peak memory 198152 kb
Host smart-dce5fec4-6fa4-4786-a073-99f87811f6d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840729349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.1840729349
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.1626076861
Short name T439
Test name
Test status
Simulation time 245334858 ps
CPU time 1.07 seconds
Started Aug 18 05:41:01 PM PDT 24
Finished Aug 18 05:41:03 PM PDT 24
Peak memory 195680 kb
Host smart-185f7327-2444-41ab-8235-c5c484890c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626076861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.1626076861
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.2123494082
Short name T628
Test name
Test status
Simulation time 211952168 ps
CPU time 1.12 seconds
Started Aug 18 05:41:18 PM PDT 24
Finished Aug 18 05:41:20 PM PDT 24
Peak memory 195844 kb
Host smart-f1d16a55-f801-4c4b-9bdf-3e18ab9dcf5c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123494082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.2123494082
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.1164597129
Short name T382
Test name
Test status
Simulation time 10220689324 ps
CPU time 140.89 seconds
Started Aug 18 05:41:02 PM PDT 24
Finished Aug 18 05:43:23 PM PDT 24
Peak memory 198280 kb
Host smart-e1cf9a38-dbc3-4a7f-a836-3ec731ec5075
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164597129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.1164597129
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_stress_all_with_rand_reset.4000100673
Short name T608
Test name
Test status
Simulation time 6257043695 ps
CPU time 99.34 seconds
Started Aug 18 05:41:34 PM PDT 24
Finished Aug 18 05:43:13 PM PDT 24
Peak memory 198524 kb
Host smart-5dacb155-9415-41d7-9caa-a91209b5b74b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4000100673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_stress_all_with_rand_reset.4000100673
Directory /workspace/32.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.gpio_alert_test.2398100518
Short name T299
Test name
Test status
Simulation time 14662787 ps
CPU time 0.6 seconds
Started Aug 18 05:41:43 PM PDT 24
Finished Aug 18 05:41:43 PM PDT 24
Peak memory 194948 kb
Host smart-d9974e98-0f4a-45d1-8a06-f8685db2a1de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398100518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.2398100518
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.2902938521
Short name T306
Test name
Test status
Simulation time 46643324 ps
CPU time 0.64 seconds
Started Aug 18 05:41:28 PM PDT 24
Finished Aug 18 05:41:28 PM PDT 24
Peak memory 194220 kb
Host smart-04953f9f-9a18-488d-82f6-30782ddbc020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902938521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.2902938521
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.2703809427
Short name T353
Test name
Test status
Simulation time 116063732 ps
CPU time 5.89 seconds
Started Aug 18 05:41:04 PM PDT 24
Finished Aug 18 05:41:10 PM PDT 24
Peak memory 196904 kb
Host smart-7b0ddc3e-648c-4119-aa78-39ec1732514f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703809427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.2703809427
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.2320510862
Short name T56
Test name
Test status
Simulation time 95310084 ps
CPU time 0.84 seconds
Started Aug 18 05:41:15 PM PDT 24
Finished Aug 18 05:41:16 PM PDT 24
Peak memory 196116 kb
Host smart-b8bd1d5c-6b0a-4cd2-96d8-2393f36787d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320510862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.2320510862
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.3151966638
Short name T564
Test name
Test status
Simulation time 54098523 ps
CPU time 1.36 seconds
Started Aug 18 05:41:05 PM PDT 24
Finished Aug 18 05:41:11 PM PDT 24
Peak memory 197140 kb
Host smart-eee0d3f8-2509-4f8b-8368-d5b09bd8493d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151966638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.3151966638
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.2126392126
Short name T574
Test name
Test status
Simulation time 34456403 ps
CPU time 1.4 seconds
Started Aug 18 05:41:05 PM PDT 24
Finished Aug 18 05:41:06 PM PDT 24
Peak memory 196812 kb
Host smart-ecb71df7-f786-41bb-80b4-c85cf239d02d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126392126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.2126392126
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.2685156806
Short name T359
Test name
Test status
Simulation time 92099334 ps
CPU time 1.93 seconds
Started Aug 18 05:41:05 PM PDT 24
Finished Aug 18 05:41:07 PM PDT 24
Peak memory 196196 kb
Host smart-820e1cdc-68d8-4578-a94d-59207435a2ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685156806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.2685156806
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.62521770
Short name T700
Test name
Test status
Simulation time 37248595 ps
CPU time 1.23 seconds
Started Aug 18 05:41:24 PM PDT 24
Finished Aug 18 05:41:25 PM PDT 24
Peak memory 196076 kb
Host smart-73cc078d-bb37-4db2-9d0a-c9a482fc7b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62521770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.62521770
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.36398976
Short name T350
Test name
Test status
Simulation time 651466847 ps
CPU time 1.34 seconds
Started Aug 18 05:41:17 PM PDT 24
Finished Aug 18 05:41:18 PM PDT 24
Peak memory 197136 kb
Host smart-cda7304f-5782-421c-b43f-d1e47b1aa6a7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36398976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullup_
pulldown.36398976
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.2549456729
Short name T6
Test name
Test status
Simulation time 532563243 ps
CPU time 3.85 seconds
Started Aug 18 05:41:39 PM PDT 24
Finished Aug 18 05:41:42 PM PDT 24
Peak memory 198108 kb
Host smart-e3ec1b71-889a-43a2-91a7-a8e22c77b3c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549456729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.2549456729
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.1131344784
Short name T120
Test name
Test status
Simulation time 305517413 ps
CPU time 1.38 seconds
Started Aug 18 05:41:15 PM PDT 24
Finished Aug 18 05:41:17 PM PDT 24
Peak memory 196832 kb
Host smart-248c334a-d80f-40ac-aee1-88c8440c57bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131344784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.1131344784
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.2699623538
Short name T676
Test name
Test status
Simulation time 46074151 ps
CPU time 1.28 seconds
Started Aug 18 05:41:24 PM PDT 24
Finished Aug 18 05:41:30 PM PDT 24
Peak memory 198160 kb
Host smart-f5d99e2d-9f42-4084-a56b-71699c87f369
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699623538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.2699623538
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.4019908129
Short name T690
Test name
Test status
Simulation time 12586012643 ps
CPU time 27.43 seconds
Started Aug 18 05:41:21 PM PDT 24
Finished Aug 18 05:41:49 PM PDT 24
Peak memory 198292 kb
Host smart-f86f35ca-75b4-4e72-8acc-4f9b08333ccd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019908129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.4019908129
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_stress_all_with_rand_reset.1194025063
Short name T641
Test name
Test status
Simulation time 1008682794 ps
CPU time 14.35 seconds
Started Aug 18 05:41:30 PM PDT 24
Finished Aug 18 05:41:45 PM PDT 24
Peak memory 198436 kb
Host smart-e9e61acb-3f93-45e1-95b6-ec657c62d14b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1194025063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_stress_all_with_rand_reset.1194025063
Directory /workspace/33.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.gpio_alert_test.130721332
Short name T128
Test name
Test status
Simulation time 42361580 ps
CPU time 0.58 seconds
Started Aug 18 05:41:22 PM PDT 24
Finished Aug 18 05:41:23 PM PDT 24
Peak memory 194036 kb
Host smart-08ac57cf-934f-41b0-8017-b0e6c6eb8bb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130721332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.130721332
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.117130321
Short name T405
Test name
Test status
Simulation time 170267670 ps
CPU time 0.64 seconds
Started Aug 18 05:41:25 PM PDT 24
Finished Aug 18 05:41:26 PM PDT 24
Peak memory 194236 kb
Host smart-ecca01a4-7d23-43da-af7d-15082979537b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117130321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.117130321
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.1952774792
Short name T710
Test name
Test status
Simulation time 385320183 ps
CPU time 10.17 seconds
Started Aug 18 05:41:23 PM PDT 24
Finished Aug 18 05:41:38 PM PDT 24
Peak memory 197056 kb
Host smart-86d5ec11-1d97-466c-b5bd-d3c54e5df8aa
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952774792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.1952774792
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.13245735
Short name T289
Test name
Test status
Simulation time 116530994 ps
CPU time 0.7 seconds
Started Aug 18 05:41:07 PM PDT 24
Finished Aug 18 05:41:08 PM PDT 24
Peak memory 194792 kb
Host smart-2e7dfc55-3add-4b5d-a206-0de6a309db27
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13245735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.13245735
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.2999392961
Short name T706
Test name
Test status
Simulation time 64050550 ps
CPU time 1.12 seconds
Started Aug 18 05:41:22 PM PDT 24
Finished Aug 18 05:41:24 PM PDT 24
Peak memory 196108 kb
Host smart-022f1218-e177-404c-9ff4-b6fa748a1f8e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999392961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.2999392961
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.3089084803
Short name T186
Test name
Test status
Simulation time 46518291 ps
CPU time 1.82 seconds
Started Aug 18 05:41:28 PM PDT 24
Finished Aug 18 05:41:30 PM PDT 24
Peak memory 198180 kb
Host smart-1d179af3-dc0c-471a-860b-b73c60a4354d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089084803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.3089084803
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.3112849934
Short name T334
Test name
Test status
Simulation time 66307067 ps
CPU time 1.38 seconds
Started Aug 18 05:41:28 PM PDT 24
Finished Aug 18 05:41:29 PM PDT 24
Peak memory 196168 kb
Host smart-49fcb8d2-8b70-4547-8c42-3f81b1fdbdaf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112849934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.3112849934
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.2652155684
Short name T158
Test name
Test status
Simulation time 196819244 ps
CPU time 1.13 seconds
Started Aug 18 05:41:28 PM PDT 24
Finished Aug 18 05:41:29 PM PDT 24
Peak memory 195964 kb
Host smart-ae47168d-fff7-4b59-9a94-0822bce3d863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652155684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.2652155684
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.3917066949
Short name T427
Test name
Test status
Simulation time 83129379 ps
CPU time 0.7 seconds
Started Aug 18 05:41:14 PM PDT 24
Finished Aug 18 05:41:15 PM PDT 24
Peak memory 196220 kb
Host smart-ee828f29-0df7-47c2-be93-8a5fb039e7a5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917066949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.3917066949
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.2408009877
Short name T590
Test name
Test status
Simulation time 172889903 ps
CPU time 1.87 seconds
Started Aug 18 05:41:32 PM PDT 24
Finished Aug 18 05:41:34 PM PDT 24
Peak memory 198164 kb
Host smart-8eb89dfb-76ec-428a-82cd-4d0f7ffe482b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408009877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.2408009877
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.3746558866
Short name T139
Test name
Test status
Simulation time 436012480 ps
CPU time 1.37 seconds
Started Aug 18 05:41:06 PM PDT 24
Finished Aug 18 05:41:07 PM PDT 24
Peak memory 196924 kb
Host smart-3bde15cd-b27e-4194-b73c-6039335197bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746558866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.3746558866
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.4060935970
Short name T601
Test name
Test status
Simulation time 543337671 ps
CPU time 1.36 seconds
Started Aug 18 05:41:31 PM PDT 24
Finished Aug 18 05:41:33 PM PDT 24
Peak memory 196932 kb
Host smart-21b6aa88-9afe-4ff7-8c10-029924f243da
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060935970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.4060935970
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.3404349069
Short name T136
Test name
Test status
Simulation time 8270031624 ps
CPU time 105.34 seconds
Started Aug 18 05:41:12 PM PDT 24
Finished Aug 18 05:42:57 PM PDT 24
Peak memory 198364 kb
Host smart-9d8fd6d7-5279-486e-9517-8c93f5f19196
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404349069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.3404349069
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_alert_test.2665448692
Short name T264
Test name
Test status
Simulation time 46358310 ps
CPU time 0.57 seconds
Started Aug 18 05:41:33 PM PDT 24
Finished Aug 18 05:41:33 PM PDT 24
Peak memory 194752 kb
Host smart-8732152f-8592-4592-b2c4-a597eb7904aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665448692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.2665448692
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.3803145365
Short name T454
Test name
Test status
Simulation time 69296544 ps
CPU time 0.8 seconds
Started Aug 18 05:41:29 PM PDT 24
Finished Aug 18 05:41:30 PM PDT 24
Peak memory 195636 kb
Host smart-54cd4248-15bc-4cbc-b1fb-8c446e426f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803145365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.3803145365
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.835136167
Short name T484
Test name
Test status
Simulation time 3121913147 ps
CPU time 27.23 seconds
Started Aug 18 05:41:03 PM PDT 24
Finished Aug 18 05:41:31 PM PDT 24
Peak memory 197236 kb
Host smart-c6634896-9ec9-49c1-9faa-c6c8aaaa68e2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835136167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stres
s.835136167
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.3824363990
Short name T3
Test name
Test status
Simulation time 153099052 ps
CPU time 0.73 seconds
Started Aug 18 05:41:04 PM PDT 24
Finished Aug 18 05:41:05 PM PDT 24
Peak memory 194944 kb
Host smart-3db65f42-93e7-4435-9e74-726d5524d22a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824363990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.3824363990
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.1147734415
Short name T465
Test name
Test status
Simulation time 93523223 ps
CPU time 1 seconds
Started Aug 18 05:41:24 PM PDT 24
Finished Aug 18 05:41:25 PM PDT 24
Peak memory 196720 kb
Host smart-80abd0f3-f671-4469-954e-27440126a499
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147734415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.1147734415
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.705525595
Short name T275
Test name
Test status
Simulation time 41377186 ps
CPU time 1.48 seconds
Started Aug 18 05:41:33 PM PDT 24
Finished Aug 18 05:41:35 PM PDT 24
Peak memory 196368 kb
Host smart-d58ab006-67b3-408a-a89c-a79cb9287383
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705525595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 35.gpio_intr_with_filter_rand_intr_event.705525595
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.774060962
Short name T625
Test name
Test status
Simulation time 28278228 ps
CPU time 0.92 seconds
Started Aug 18 05:41:36 PM PDT 24
Finished Aug 18 05:41:37 PM PDT 24
Peak memory 195540 kb
Host smart-2977aa39-4dc8-4705-b19d-17c46a7a95f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774060962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger.
774060962
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.1465272481
Short name T323
Test name
Test status
Simulation time 160425176 ps
CPU time 1.31 seconds
Started Aug 18 05:41:20 PM PDT 24
Finished Aug 18 05:41:21 PM PDT 24
Peak memory 195904 kb
Host smart-38dc4baa-f55a-4511-bea4-4d117f6b4b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465272481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.1465272481
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.3263000190
Short name T650
Test name
Test status
Simulation time 117802020 ps
CPU time 1.18 seconds
Started Aug 18 05:41:06 PM PDT 24
Finished Aug 18 05:41:07 PM PDT 24
Peak memory 197116 kb
Host smart-3bfe7dbf-06b4-4060-9f9a-8cdd2f31dbb7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263000190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.3263000190
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.4281435129
Short name T545
Test name
Test status
Simulation time 1473261391 ps
CPU time 3.96 seconds
Started Aug 18 05:41:42 PM PDT 24
Finished Aug 18 05:41:46 PM PDT 24
Peak memory 198084 kb
Host smart-4230695b-552c-413e-ba79-89c4ef5bb25d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281435129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.4281435129
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.1275019793
Short name T282
Test name
Test status
Simulation time 103519475 ps
CPU time 1.1 seconds
Started Aug 18 05:41:05 PM PDT 24
Finished Aug 18 05:41:06 PM PDT 24
Peak memory 196672 kb
Host smart-441b5c3a-1a19-492e-aea0-77480c8157bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275019793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.1275019793
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.1990577877
Short name T500
Test name
Test status
Simulation time 94894713 ps
CPU time 1.36 seconds
Started Aug 18 05:41:40 PM PDT 24
Finished Aug 18 05:41:41 PM PDT 24
Peak memory 195692 kb
Host smart-edf3145a-1d1e-4ce9-ac8e-b28bc17b5438
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990577877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.1990577877
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.3085125153
Short name T408
Test name
Test status
Simulation time 13680520820 ps
CPU time 40.5 seconds
Started Aug 18 05:41:19 PM PDT 24
Finished Aug 18 05:42:00 PM PDT 24
Peak memory 198324 kb
Host smart-b27f3e7f-0e10-4d1b-b16a-0275202e25e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085125153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.3085125153
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_alert_test.127855639
Short name T40
Test name
Test status
Simulation time 44751320 ps
CPU time 0.57 seconds
Started Aug 18 05:41:08 PM PDT 24
Finished Aug 18 05:41:09 PM PDT 24
Peak memory 194064 kb
Host smart-5ca60d9b-7c33-4ac9-87c6-6bf970f24066
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127855639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.127855639
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.4226220518
Short name T244
Test name
Test status
Simulation time 117771709 ps
CPU time 0.71 seconds
Started Aug 18 05:41:32 PM PDT 24
Finished Aug 18 05:41:33 PM PDT 24
Peak memory 196156 kb
Host smart-c19515dd-aa6b-4c71-b570-a17e34851133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226220518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.4226220518
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.4188212131
Short name T566
Test name
Test status
Simulation time 345712350 ps
CPU time 11.67 seconds
Started Aug 18 05:41:30 PM PDT 24
Finished Aug 18 05:41:42 PM PDT 24
Peak memory 198172 kb
Host smart-99900c45-2149-423c-8a10-d0b63c06b3fd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188212131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.4188212131
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.2453695379
Short name T509
Test name
Test status
Simulation time 151328531 ps
CPU time 0.98 seconds
Started Aug 18 05:41:30 PM PDT 24
Finished Aug 18 05:41:32 PM PDT 24
Peak memory 196524 kb
Host smart-fe435b48-8106-486d-86ba-64ff7c2b425d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453695379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.2453695379
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.896023056
Short name T243
Test name
Test status
Simulation time 45121864 ps
CPU time 0.84 seconds
Started Aug 18 05:41:26 PM PDT 24
Finished Aug 18 05:41:27 PM PDT 24
Peak memory 196872 kb
Host smart-8f833efb-6935-4e14-83f6-6b867a9b4b13
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896023056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.896023056
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.4210077293
Short name T660
Test name
Test status
Simulation time 64726678 ps
CPU time 2.44 seconds
Started Aug 18 05:41:24 PM PDT 24
Finished Aug 18 05:41:32 PM PDT 24
Peak memory 198240 kb
Host smart-9d47bc64-cfec-4599-8c7a-571682888d7c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210077293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.4210077293
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.3356764736
Short name T431
Test name
Test status
Simulation time 510705130 ps
CPU time 1.54 seconds
Started Aug 18 05:41:06 PM PDT 24
Finished Aug 18 05:41:08 PM PDT 24
Peak memory 196804 kb
Host smart-c52d265d-6e96-4392-82c4-fa70c0718331
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356764736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.3356764736
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.2126773120
Short name T378
Test name
Test status
Simulation time 58681605 ps
CPU time 1.3 seconds
Started Aug 18 05:41:29 PM PDT 24
Finished Aug 18 05:41:30 PM PDT 24
Peak memory 196052 kb
Host smart-50dac023-0d3a-4020-9725-bdd05b1f5dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126773120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.2126773120
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.2180992628
Short name T485
Test name
Test status
Simulation time 219941812 ps
CPU time 1.29 seconds
Started Aug 18 05:41:18 PM PDT 24
Finished Aug 18 05:41:24 PM PDT 24
Peak memory 197084 kb
Host smart-d76e4f12-311e-41df-9692-8d0d9cf144e3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180992628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.2180992628
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.3704729509
Short name T432
Test name
Test status
Simulation time 198518688 ps
CPU time 2.55 seconds
Started Aug 18 05:41:14 PM PDT 24
Finished Aug 18 05:41:16 PM PDT 24
Peak memory 198180 kb
Host smart-d895b7c1-a277-470e-bd26-08d273be9c5c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704729509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.3704729509
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.190700395
Short name T59
Test name
Test status
Simulation time 283720986 ps
CPU time 1.34 seconds
Started Aug 18 05:41:16 PM PDT 24
Finished Aug 18 05:41:17 PM PDT 24
Peak memory 198008 kb
Host smart-f6929f52-fc09-4c16-bbfa-d95c4f568f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190700395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.190700395
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.1639735076
Short name T381
Test name
Test status
Simulation time 28337457 ps
CPU time 0.87 seconds
Started Aug 18 05:41:25 PM PDT 24
Finished Aug 18 05:41:26 PM PDT 24
Peak memory 196548 kb
Host smart-9ea51c45-ea04-4a12-8ef3-d8cb33fb7289
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639735076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.1639735076
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.528338488
Short name T311
Test name
Test status
Simulation time 4436562130 ps
CPU time 98.54 seconds
Started Aug 18 05:41:37 PM PDT 24
Finished Aug 18 05:43:21 PM PDT 24
Peak memory 198352 kb
Host smart-1ef8d60f-94b4-4f09-bf75-859b02deba7e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528338488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.g
pio_stress_all.528338488
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_stress_all_with_rand_reset.839055742
Short name T67
Test name
Test status
Simulation time 25674757742 ps
CPU time 202.53 seconds
Started Aug 18 05:41:29 PM PDT 24
Finished Aug 18 05:44:52 PM PDT 24
Peak memory 198544 kb
Host smart-a8a3e5e3-56ac-4455-8f62-9cf3265aeb5c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=839055742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_stress_all_with_rand_reset.839055742
Directory /workspace/36.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.gpio_alert_test.3755156619
Short name T303
Test name
Test status
Simulation time 23888258 ps
CPU time 0.57 seconds
Started Aug 18 05:41:41 PM PDT 24
Finished Aug 18 05:41:42 PM PDT 24
Peak memory 194048 kb
Host smart-b87134db-92cd-44db-a28f-ac4a04cf311e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755156619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.3755156619
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.2041492158
Short name T694
Test name
Test status
Simulation time 56541079 ps
CPU time 0.74 seconds
Started Aug 18 05:41:18 PM PDT 24
Finished Aug 18 05:41:18 PM PDT 24
Peak memory 195480 kb
Host smart-e2a7d5e3-fafb-41d8-980d-a3ab9e9a074d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041492158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.2041492158
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.3568829238
Short name T317
Test name
Test status
Simulation time 408883149 ps
CPU time 20.65 seconds
Started Aug 18 05:41:45 PM PDT 24
Finished Aug 18 05:42:06 PM PDT 24
Peak memory 195664 kb
Host smart-1390bf29-a7f4-46d2-a69f-87e9dedb392c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568829238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stre
ss.3568829238
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.610168653
Short name T22
Test name
Test status
Simulation time 193472244 ps
CPU time 0.81 seconds
Started Aug 18 05:41:28 PM PDT 24
Finished Aug 18 05:41:29 PM PDT 24
Peak memory 195968 kb
Host smart-fa042e11-2c7c-483d-a1e6-c58d4328b29b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610168653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.610168653
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.901313929
Short name T592
Test name
Test status
Simulation time 40750169 ps
CPU time 1.06 seconds
Started Aug 18 05:41:34 PM PDT 24
Finished Aug 18 05:41:35 PM PDT 24
Peak memory 196008 kb
Host smart-a4f7fc5d-8627-4a96-9d6d-82f31d39534e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901313929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.901313929
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.234797222
Short name T464
Test name
Test status
Simulation time 26156687 ps
CPU time 1.06 seconds
Started Aug 18 05:41:40 PM PDT 24
Finished Aug 18 05:41:41 PM PDT 24
Peak memory 196468 kb
Host smart-d35daac1-9cde-4984-88ba-7047c64bcf73
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234797222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 37.gpio_intr_with_filter_rand_intr_event.234797222
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.86320593
Short name T145
Test name
Test status
Simulation time 171284872 ps
CPU time 3.26 seconds
Started Aug 18 05:41:40 PM PDT 24
Finished Aug 18 05:41:44 PM PDT 24
Peak memory 198200 kb
Host smart-a6e872f6-8f89-4cdd-bd2a-520b17888493
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86320593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger.86320593
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.3343151706
Short name T678
Test name
Test status
Simulation time 74860068 ps
CPU time 0.94 seconds
Started Aug 18 05:41:23 PM PDT 24
Finished Aug 18 05:41:24 PM PDT 24
Peak memory 195976 kb
Host smart-15de35f0-6b3c-4c1a-893a-168e6ba36433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343151706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.3343151706
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.2349404683
Short name T669
Test name
Test status
Simulation time 73498139 ps
CPU time 0.85 seconds
Started Aug 18 05:41:08 PM PDT 24
Finished Aug 18 05:41:14 PM PDT 24
Peak memory 196032 kb
Host smart-9d4cf4db-e5b8-4c95-8715-556a6e4a9d65
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349404683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.2349404683
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.1675288558
Short name T232
Test name
Test status
Simulation time 128403814 ps
CPU time 5.31 seconds
Started Aug 18 05:41:29 PM PDT 24
Finished Aug 18 05:41:34 PM PDT 24
Peak memory 197428 kb
Host smart-e3dea452-aaa8-42b9-92e0-5166b870356a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675288558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.1675288558
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.3570883356
Short name T54
Test name
Test status
Simulation time 275176689 ps
CPU time 1.18 seconds
Started Aug 18 05:41:36 PM PDT 24
Finished Aug 18 05:41:38 PM PDT 24
Peak memory 195900 kb
Host smart-c39e0958-8c93-4b83-a0fe-dccd32564924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570883356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.3570883356
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.3443884254
Short name T392
Test name
Test status
Simulation time 48603913 ps
CPU time 1.09 seconds
Started Aug 18 05:41:32 PM PDT 24
Finished Aug 18 05:41:34 PM PDT 24
Peak memory 195868 kb
Host smart-830113bb-c30d-46c0-b63d-d5ad395bb4fd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443884254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.3443884254
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.2707987600
Short name T7
Test name
Test status
Simulation time 19835319213 ps
CPU time 58.79 seconds
Started Aug 18 05:41:21 PM PDT 24
Finished Aug 18 05:42:19 PM PDT 24
Peak memory 198296 kb
Host smart-ddf75443-1f63-4fe3-9478-fb8906f98915
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707987600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.2707987600
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_alert_test.2293937230
Short name T122
Test name
Test status
Simulation time 19606272 ps
CPU time 0.57 seconds
Started Aug 18 05:41:33 PM PDT 24
Finished Aug 18 05:41:34 PM PDT 24
Peak memory 194760 kb
Host smart-3d9aac09-e896-4fa9-bf21-ba751cec86e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293937230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.2293937230
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.98598636
Short name T513
Test name
Test status
Simulation time 47910524 ps
CPU time 0.78 seconds
Started Aug 18 05:41:34 PM PDT 24
Finished Aug 18 05:41:35 PM PDT 24
Peak memory 196092 kb
Host smart-c1ab84bd-12e6-44c7-990b-8350298c4a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98598636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.98598636
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.2495579023
Short name T584
Test name
Test status
Simulation time 260673271 ps
CPU time 10.02 seconds
Started Aug 18 05:41:29 PM PDT 24
Finished Aug 18 05:41:39 PM PDT 24
Peak memory 198112 kb
Host smart-00f58ccd-513d-4950-824a-050b056379e3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495579023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.2495579023
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.3300878900
Short name T75
Test name
Test status
Simulation time 126624923 ps
CPU time 0.93 seconds
Started Aug 18 05:41:26 PM PDT 24
Finished Aug 18 05:41:27 PM PDT 24
Peak memory 197320 kb
Host smart-9c52af0e-526c-49a3-82fc-c9b98759c5e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300878900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.3300878900
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.986830295
Short name T578
Test name
Test status
Simulation time 212289096 ps
CPU time 0.96 seconds
Started Aug 18 05:41:37 PM PDT 24
Finished Aug 18 05:41:48 PM PDT 24
Peak memory 195976 kb
Host smart-fad7e338-d233-47d7-b0ae-920cc80f0156
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986830295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.986830295
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.2541716493
Short name T161
Test name
Test status
Simulation time 36047253 ps
CPU time 1.33 seconds
Started Aug 18 05:41:26 PM PDT 24
Finished Aug 18 05:41:28 PM PDT 24
Peak memory 198228 kb
Host smart-3b77314c-6f32-4104-8aa3-2ab0ebe10fa5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541716493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.2541716493
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.1373410401
Short name T60
Test name
Test status
Simulation time 60096491 ps
CPU time 0.94 seconds
Started Aug 18 05:41:39 PM PDT 24
Finished Aug 18 05:41:43 PM PDT 24
Peak memory 195740 kb
Host smart-4823eb11-e5e6-4faf-9bee-caa74dbb8380
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373410401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.1373410401
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.3675127159
Short name T183
Test name
Test status
Simulation time 73595332 ps
CPU time 0.82 seconds
Started Aug 18 05:41:12 PM PDT 24
Finished Aug 18 05:41:13 PM PDT 24
Peak memory 196712 kb
Host smart-163604b9-161a-4a78-a7cc-1bc6c7c8417c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675127159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.3675127159
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.2997990812
Short name T151
Test name
Test status
Simulation time 21507252 ps
CPU time 0.81 seconds
Started Aug 18 05:41:41 PM PDT 24
Finished Aug 18 05:41:42 PM PDT 24
Peak memory 197416 kb
Host smart-ec1575d9-81c5-48b9-894c-3e460a3e30d7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997990812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.2997990812
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.2589521789
Short name T558
Test name
Test status
Simulation time 409543121 ps
CPU time 4.42 seconds
Started Aug 18 05:41:31 PM PDT 24
Finished Aug 18 05:41:36 PM PDT 24
Peak memory 198156 kb
Host smart-3e03d012-dafd-4848-ad04-6cce57dcd40f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589521789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.2589521789
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.73056751
Short name T527
Test name
Test status
Simulation time 259232744 ps
CPU time 1.26 seconds
Started Aug 18 05:41:26 PM PDT 24
Finished Aug 18 05:41:28 PM PDT 24
Peak memory 197000 kb
Host smart-4122a7be-f7b3-4639-8cb2-bc3d2afd32dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73056751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.73056751
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.1854164885
Short name T178
Test name
Test status
Simulation time 318606687 ps
CPU time 1.5 seconds
Started Aug 18 05:41:28 PM PDT 24
Finished Aug 18 05:41:30 PM PDT 24
Peak memory 198140 kb
Host smart-9819ec9c-877c-42ae-970f-8c09e7b7bbc9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854164885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.1854164885
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.1637122659
Short name T300
Test name
Test status
Simulation time 2581952132 ps
CPU time 38.89 seconds
Started Aug 18 05:41:38 PM PDT 24
Finished Aug 18 05:42:21 PM PDT 24
Peak memory 198240 kb
Host smart-05d23dae-2256-4da5-b75d-1a10cf04b0ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637122659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.1637122659
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_stress_all_with_rand_reset.3928567121
Short name T369
Test name
Test status
Simulation time 119409042899 ps
CPU time 274 seconds
Started Aug 18 05:41:20 PM PDT 24
Finished Aug 18 05:45:54 PM PDT 24
Peak memory 198472 kb
Host smart-087ba656-1704-4d6b-a691-96ed50e49d59
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3928567121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_stress_all_with_rand_reset.3928567121
Directory /workspace/38.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.gpio_alert_test.1940569276
Short name T294
Test name
Test status
Simulation time 40926547 ps
CPU time 0.57 seconds
Started Aug 18 05:41:22 PM PDT 24
Finished Aug 18 05:41:23 PM PDT 24
Peak memory 193304 kb
Host smart-8f790a4a-baf5-4a66-b083-3da93038a0ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940569276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.1940569276
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.940793488
Short name T360
Test name
Test status
Simulation time 20853816 ps
CPU time 0.68 seconds
Started Aug 18 05:41:28 PM PDT 24
Finished Aug 18 05:41:29 PM PDT 24
Peak memory 194264 kb
Host smart-8482ad7d-c9ea-4ea9-a837-917745156a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940793488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.940793488
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.2395302444
Short name T637
Test name
Test status
Simulation time 981891438 ps
CPU time 8.19 seconds
Started Aug 18 05:41:22 PM PDT 24
Finished Aug 18 05:41:31 PM PDT 24
Peak memory 197144 kb
Host smart-8d34b3e8-28a4-4c82-99d6-a8b8c3649dd6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395302444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.2395302444
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.3936524776
Short name T242
Test name
Test status
Simulation time 469418555 ps
CPU time 0.89 seconds
Started Aug 18 05:41:27 PM PDT 24
Finished Aug 18 05:41:28 PM PDT 24
Peak memory 197288 kb
Host smart-37025c5c-39d7-4dab-bf7f-373cbaebd5bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936524776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.3936524776
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.2180613208
Short name T316
Test name
Test status
Simulation time 40319839 ps
CPU time 0.79 seconds
Started Aug 18 05:41:34 PM PDT 24
Finished Aug 18 05:41:35 PM PDT 24
Peak memory 194740 kb
Host smart-1eabf68c-4d9b-4cbe-9065-d28a9a163dd0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180613208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.2180613208
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.840849820
Short name T198
Test name
Test status
Simulation time 48920218 ps
CPU time 1.87 seconds
Started Aug 18 05:41:24 PM PDT 24
Finished Aug 18 05:41:26 PM PDT 24
Peak memory 198160 kb
Host smart-2fd8e0ac-3061-44ae-ad31-9aae98b9a0c0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840849820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 39.gpio_intr_with_filter_rand_intr_event.840849820
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.214909178
Short name T312
Test name
Test status
Simulation time 182756983 ps
CPU time 2.26 seconds
Started Aug 18 05:41:27 PM PDT 24
Finished Aug 18 05:41:30 PM PDT 24
Peak memory 197244 kb
Host smart-9b9fcffe-8d90-41a2-94c3-fb873ea40a79
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214909178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger.
214909178
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.2659798297
Short name T634
Test name
Test status
Simulation time 135899546 ps
CPU time 0.99 seconds
Started Aug 18 05:41:10 PM PDT 24
Finished Aug 18 05:41:11 PM PDT 24
Peak memory 195932 kb
Host smart-6bfd004d-75d5-4325-8dae-8a1554ae2d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659798297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.2659798297
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.3908982790
Short name T407
Test name
Test status
Simulation time 40398110 ps
CPU time 0.86 seconds
Started Aug 18 05:41:30 PM PDT 24
Finished Aug 18 05:41:31 PM PDT 24
Peak memory 195820 kb
Host smart-799bbcf7-575e-43c6-82bb-1deddf5f2d0e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908982790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.3908982790
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.658182053
Short name T58
Test name
Test status
Simulation time 1232254932 ps
CPU time 5.04 seconds
Started Aug 18 05:41:33 PM PDT 24
Finished Aug 18 05:41:38 PM PDT 24
Peak memory 198124 kb
Host smart-78e8a0f9-5709-4dc7-b0d7-8d8c505cd310
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658182053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ran
dom_long_reg_writes_reg_reads.658182053
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.2390947654
Short name T470
Test name
Test status
Simulation time 70376786 ps
CPU time 1.24 seconds
Started Aug 18 05:41:31 PM PDT 24
Finished Aug 18 05:41:33 PM PDT 24
Peak memory 196040 kb
Host smart-595069c8-bd2e-44b7-bb76-28f899e8151c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390947654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.2390947654
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.293421075
Short name T617
Test name
Test status
Simulation time 148299562 ps
CPU time 0.87 seconds
Started Aug 18 05:41:33 PM PDT 24
Finished Aug 18 05:41:34 PM PDT 24
Peak memory 196632 kb
Host smart-cdfce65b-11a0-469b-8c84-a6b0769db1d8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293421075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.293421075
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.3515059379
Short name T469
Test name
Test status
Simulation time 14326932949 ps
CPU time 102.04 seconds
Started Aug 18 05:41:26 PM PDT 24
Finished Aug 18 05:43:08 PM PDT 24
Peak memory 198380 kb
Host smart-6deb8804-7796-41be-80c6-eb615cebf52d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515059379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.3515059379
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_alert_test.2359935808
Short name T226
Test name
Test status
Simulation time 14625784 ps
CPU time 0.57 seconds
Started Aug 18 05:40:21 PM PDT 24
Finished Aug 18 05:40:21 PM PDT 24
Peak memory 194052 kb
Host smart-5db6c58d-0a67-40cd-a48f-152122238622
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359935808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.2359935808
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.758449008
Short name T389
Test name
Test status
Simulation time 14196110 ps
CPU time 0.64 seconds
Started Aug 18 05:40:31 PM PDT 24
Finished Aug 18 05:40:32 PM PDT 24
Peak memory 194028 kb
Host smart-eceffcf3-428e-4c48-8981-46fe72f51b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758449008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.758449008
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.3976690477
Short name T269
Test name
Test status
Simulation time 659648327 ps
CPU time 20.16 seconds
Started Aug 18 05:40:39 PM PDT 24
Finished Aug 18 05:41:00 PM PDT 24
Peak memory 198200 kb
Host smart-f3ab3192-3a37-4b97-8ee6-36c30969b25f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976690477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.3976690477
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.247550769
Short name T224
Test name
Test status
Simulation time 35219206 ps
CPU time 0.64 seconds
Started Aug 18 05:40:40 PM PDT 24
Finished Aug 18 05:40:41 PM PDT 24
Peak memory 194584 kb
Host smart-3f8579f5-52be-4781-bbea-b40222dddaca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247550769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.247550769
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.1438889823
Short name T506
Test name
Test status
Simulation time 261549772 ps
CPU time 1.45 seconds
Started Aug 18 05:40:33 PM PDT 24
Finished Aug 18 05:40:34 PM PDT 24
Peak memory 196624 kb
Host smart-b9359a68-af5e-41f4-bc7f-3b5eddcce9f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438889823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.1438889823
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.4113544207
Short name T205
Test name
Test status
Simulation time 109656827 ps
CPU time 1.49 seconds
Started Aug 18 05:40:25 PM PDT 24
Finished Aug 18 05:40:27 PM PDT 24
Peak memory 198216 kb
Host smart-08b09065-4ff1-4cb2-a6fd-e984830d582a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113544207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.4113544207
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.370507870
Short name T375
Test name
Test status
Simulation time 246046385 ps
CPU time 3.4 seconds
Started Aug 18 05:40:15 PM PDT 24
Finished Aug 18 05:40:19 PM PDT 24
Peak memory 196820 kb
Host smart-e5626eca-a90c-417b-b09a-8054f89e9e9e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370507870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.370507870
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.631135471
Short name T531
Test name
Test status
Simulation time 110346327 ps
CPU time 1.13 seconds
Started Aug 18 05:40:28 PM PDT 24
Finished Aug 18 05:40:29 PM PDT 24
Peak memory 196720 kb
Host smart-df25fdd1-7403-4c5c-a87f-73d0c8226c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631135471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.631135471
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.3418825793
Short name T160
Test name
Test status
Simulation time 99257373 ps
CPU time 0.79 seconds
Started Aug 18 05:40:15 PM PDT 24
Finished Aug 18 05:40:15 PM PDT 24
Peak memory 195992 kb
Host smart-78719b21-d977-4da0-99dc-7e3b4f68a373
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418825793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.3418825793
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.158840193
Short name T716
Test name
Test status
Simulation time 837266663 ps
CPU time 3.75 seconds
Started Aug 18 05:40:31 PM PDT 24
Finished Aug 18 05:40:36 PM PDT 24
Peak memory 198156 kb
Host smart-2612b0b1-0e79-45ee-b8db-eceb03b1aa1d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158840193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand
om_long_reg_writes_reg_reads.158840193
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.124296787
Short name T36
Test name
Test status
Simulation time 65959936 ps
CPU time 0.86 seconds
Started Aug 18 05:40:32 PM PDT 24
Finished Aug 18 05:40:33 PM PDT 24
Peak memory 214104 kb
Host smart-07414222-8db3-4f74-9b3d-11a2caae5115
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124296787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.124296787
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.1100202963
Short name T223
Test name
Test status
Simulation time 31395929 ps
CPU time 0.76 seconds
Started Aug 18 05:40:48 PM PDT 24
Finished Aug 18 05:40:58 PM PDT 24
Peak memory 195340 kb
Host smart-d345282a-ade5-4c3c-8944-a52a88d0fc8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100202963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.1100202963
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.3661089739
Short name T125
Test name
Test status
Simulation time 59190939 ps
CPU time 0.83 seconds
Started Aug 18 05:40:19 PM PDT 24
Finished Aug 18 05:40:20 PM PDT 24
Peak memory 195388 kb
Host smart-50a10e46-e2b9-473b-aa1a-7e4d556585fd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661089739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.3661089739
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.3283448718
Short name T539
Test name
Test status
Simulation time 1565698011 ps
CPU time 36.82 seconds
Started Aug 18 05:40:13 PM PDT 24
Finished Aug 18 05:40:50 PM PDT 24
Peak memory 198208 kb
Host smart-48f5fa5a-a8d5-424f-8581-38dc48bcb2a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283448718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.3283448718
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_alert_test.3057412818
Short name T535
Test name
Test status
Simulation time 40346920 ps
CPU time 0.56 seconds
Started Aug 18 05:41:23 PM PDT 24
Finished Aug 18 05:41:24 PM PDT 24
Peak memory 194048 kb
Host smart-5855bc39-ab24-45be-afe5-e1c4b2399ed7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057412818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.3057412818
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.44790388
Short name T480
Test name
Test status
Simulation time 92076626 ps
CPU time 0.79 seconds
Started Aug 18 05:41:15 PM PDT 24
Finished Aug 18 05:41:16 PM PDT 24
Peak memory 195680 kb
Host smart-2505f01c-bb49-4f16-94c2-384d839bf683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44790388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.44790388
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.3329642215
Short name T272
Test name
Test status
Simulation time 1602539471 ps
CPU time 17.76 seconds
Started Aug 18 05:41:33 PM PDT 24
Finished Aug 18 05:41:51 PM PDT 24
Peak memory 196972 kb
Host smart-1741aad1-a66f-4629-b592-a7ca2b991e14
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329642215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.3329642215
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.4010840359
Short name T467
Test name
Test status
Simulation time 67729973 ps
CPU time 0.71 seconds
Started Aug 18 05:41:27 PM PDT 24
Finished Aug 18 05:41:28 PM PDT 24
Peak memory 194000 kb
Host smart-728367b8-74f3-4570-8590-2d959f5edd96
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010840359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.4010840359
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.1122028986
Short name T472
Test name
Test status
Simulation time 63049999 ps
CPU time 1.3 seconds
Started Aug 18 05:41:32 PM PDT 24
Finished Aug 18 05:41:33 PM PDT 24
Peak memory 198184 kb
Host smart-3822d0ba-b151-4b74-b796-073a1329de95
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122028986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.1122028986
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.932025778
Short name T163
Test name
Test status
Simulation time 67171782 ps
CPU time 1.87 seconds
Started Aug 18 05:41:31 PM PDT 24
Finished Aug 18 05:41:33 PM PDT 24
Peak memory 196448 kb
Host smart-7fbeef0c-ec16-4ec7-ac2c-51527711d4a1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932025778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 40.gpio_intr_with_filter_rand_intr_event.932025778
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.4061075004
Short name T459
Test name
Test status
Simulation time 502000639 ps
CPU time 2.35 seconds
Started Aug 18 05:41:41 PM PDT 24
Finished Aug 18 05:41:44 PM PDT 24
Peak memory 195956 kb
Host smart-a689a75e-0e3a-4f10-b980-4d96573a49ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061075004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.4061075004
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.3629204920
Short name T675
Test name
Test status
Simulation time 92895235 ps
CPU time 1.04 seconds
Started Aug 18 05:41:30 PM PDT 24
Finished Aug 18 05:41:31 PM PDT 24
Peak memory 196656 kb
Host smart-600dd1e3-681c-40eb-8821-62ffca9ec855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629204920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.3629204920
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.3255727721
Short name T453
Test name
Test status
Simulation time 109531424 ps
CPU time 0.96 seconds
Started Aug 18 05:41:31 PM PDT 24
Finished Aug 18 05:41:32 PM PDT 24
Peak memory 196736 kb
Host smart-276ccdaf-64b4-46b1-9ef1-49068f303965
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255727721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.3255727721
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.3073524333
Short name T171
Test name
Test status
Simulation time 253536029 ps
CPU time 2.1 seconds
Started Aug 18 05:41:23 PM PDT 24
Finished Aug 18 05:41:25 PM PDT 24
Peak memory 198176 kb
Host smart-e13a67e6-ed15-46b5-aa82-cbd42c68cec9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073524333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.3073524333
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.2179518389
Short name T702
Test name
Test status
Simulation time 68411485 ps
CPU time 1.15 seconds
Started Aug 18 05:41:22 PM PDT 24
Finished Aug 18 05:41:24 PM PDT 24
Peak memory 195996 kb
Host smart-213dbfb3-e814-4668-8598-c786f89460b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179518389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.2179518389
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.3738551403
Short name T658
Test name
Test status
Simulation time 79511673 ps
CPU time 0.76 seconds
Started Aug 18 05:41:34 PM PDT 24
Finished Aug 18 05:41:35 PM PDT 24
Peak memory 195300 kb
Host smart-dd0c4abd-f662-47c1-ab9a-e5559ca0074c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738551403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.3738551403
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.2690442614
Short name T630
Test name
Test status
Simulation time 15355615637 ps
CPU time 160.1 seconds
Started Aug 18 05:41:27 PM PDT 24
Finished Aug 18 05:44:07 PM PDT 24
Peak memory 198320 kb
Host smart-646134bf-8424-4a58-bada-67e626f08e4f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690442614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.2690442614
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_stress_all_with_rand_reset.1402923047
Short name T536
Test name
Test status
Simulation time 5417881275 ps
CPU time 175.91 seconds
Started Aug 18 05:41:32 PM PDT 24
Finished Aug 18 05:44:28 PM PDT 24
Peak memory 198544 kb
Host smart-a7d344e6-9e99-4418-b849-63bb94e942db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1402923047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_stress_all_with_rand_reset.1402923047
Directory /workspace/40.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.gpio_alert_test.1023361077
Short name T315
Test name
Test status
Simulation time 46923268 ps
CPU time 0.56 seconds
Started Aug 18 05:41:26 PM PDT 24
Finished Aug 18 05:41:27 PM PDT 24
Peak memory 194764 kb
Host smart-82e7567e-fd95-4c07-8daa-0c33ae847c9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023361077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.1023361077
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.2578651923
Short name T130
Test name
Test status
Simulation time 28625160 ps
CPU time 0.88 seconds
Started Aug 18 05:41:27 PM PDT 24
Finished Aug 18 05:41:28 PM PDT 24
Peak memory 197140 kb
Host smart-97b07658-401c-4e98-8dab-52f8139b287e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578651923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.2578651923
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.3800227078
Short name T310
Test name
Test status
Simulation time 370979829 ps
CPU time 17.99 seconds
Started Aug 18 05:41:40 PM PDT 24
Finished Aug 18 05:41:58 PM PDT 24
Peak memory 195696 kb
Host smart-f6831ee2-7d8f-4b76-8236-decdeb4c81fb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800227078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.3800227078
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.183813682
Short name T245
Test name
Test status
Simulation time 57723730 ps
CPU time 0.85 seconds
Started Aug 18 05:41:51 PM PDT 24
Finished Aug 18 05:41:53 PM PDT 24
Peak memory 197100 kb
Host smart-eae75451-89be-493e-bfc3-a8a2d4ba463a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183813682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.183813682
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.654220492
Short name T648
Test name
Test status
Simulation time 308186559 ps
CPU time 1.27 seconds
Started Aug 18 05:41:32 PM PDT 24
Finished Aug 18 05:41:34 PM PDT 24
Peak memory 197320 kb
Host smart-c883db64-5023-4547-b515-e65e43f4f3f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654220492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.654220492
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.527942120
Short name T616
Test name
Test status
Simulation time 90436963 ps
CPU time 3.32 seconds
Started Aug 18 05:41:38 PM PDT 24
Finished Aug 18 05:41:41 PM PDT 24
Peak memory 198168 kb
Host smart-f241bbf0-58ad-493c-bcc5-b9abeaa6c70a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527942120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 41.gpio_intr_with_filter_rand_intr_event.527942120
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.1653376534
Short name T212
Test name
Test status
Simulation time 109904531 ps
CPU time 2.45 seconds
Started Aug 18 05:41:31 PM PDT 24
Finished Aug 18 05:41:34 PM PDT 24
Peak memory 197180 kb
Host smart-d2ab7b37-9bf2-43e1-9062-1adafba40802
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653376534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.1653376534
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.1202494523
Short name T281
Test name
Test status
Simulation time 38019467 ps
CPU time 0.81 seconds
Started Aug 18 05:41:43 PM PDT 24
Finished Aug 18 05:41:44 PM PDT 24
Peak memory 196760 kb
Host smart-02707ec9-83ca-4f5f-a84b-400bfde1b9fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202494523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.1202494523
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.3843422918
Short name T402
Test name
Test status
Simulation time 122354393 ps
CPU time 1.24 seconds
Started Aug 18 05:41:30 PM PDT 24
Finished Aug 18 05:41:31 PM PDT 24
Peak memory 197172 kb
Host smart-7379f00e-b88e-4e70-a59f-b8b94c50bc00
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843422918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.3843422918
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.2089561580
Short name T429
Test name
Test status
Simulation time 359140480 ps
CPU time 2.53 seconds
Started Aug 18 05:41:31 PM PDT 24
Finished Aug 18 05:41:34 PM PDT 24
Peak memory 198132 kb
Host smart-87f0b48e-ac43-4c25-9fb4-d558642652e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089561580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.2089561580
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.2765020552
Short name T653
Test name
Test status
Simulation time 575324744 ps
CPU time 1.34 seconds
Started Aug 18 05:41:29 PM PDT 24
Finished Aug 18 05:41:31 PM PDT 24
Peak memory 196884 kb
Host smart-5e500123-edce-45ae-b372-428118978dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765020552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.2765020552
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.802388560
Short name T157
Test name
Test status
Simulation time 145580126 ps
CPU time 1.21 seconds
Started Aug 18 05:41:37 PM PDT 24
Finished Aug 18 05:41:38 PM PDT 24
Peak memory 198168 kb
Host smart-68a6d8f4-6358-4128-acce-701ce19580f8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802388560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.802388560
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.2272361814
Short name T386
Test name
Test status
Simulation time 63930262672 ps
CPU time 76.84 seconds
Started Aug 18 05:41:44 PM PDT 24
Finished Aug 18 05:43:01 PM PDT 24
Peak memory 198372 kb
Host smart-d2dc36d8-2788-47e6-81de-8484de8e05de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272361814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.2272361814
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_alert_test.2669562796
Short name T347
Test name
Test status
Simulation time 35061790 ps
CPU time 0.56 seconds
Started Aug 18 05:41:44 PM PDT 24
Finished Aug 18 05:41:45 PM PDT 24
Peak memory 194756 kb
Host smart-073e3566-a8cf-4c55-b4ab-62aab9a143ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669562796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.2669562796
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.1922629931
Short name T27
Test name
Test status
Simulation time 48456476 ps
CPU time 0.6 seconds
Started Aug 18 05:41:36 PM PDT 24
Finished Aug 18 05:41:37 PM PDT 24
Peak memory 194888 kb
Host smart-15afe948-677d-4014-877d-e4f18539feb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922629931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.1922629931
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.545699583
Short name T204
Test name
Test status
Simulation time 600254333 ps
CPU time 18.98 seconds
Started Aug 18 05:41:22 PM PDT 24
Finished Aug 18 05:41:42 PM PDT 24
Peak memory 198136 kb
Host smart-b4f9aa2f-f054-4fe7-8f3c-f5364a29bf87
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545699583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stres
s.545699583
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.1780094801
Short name T430
Test name
Test status
Simulation time 47068646 ps
CPU time 0.77 seconds
Started Aug 18 05:41:39 PM PDT 24
Finished Aug 18 05:41:40 PM PDT 24
Peak memory 196664 kb
Host smart-c431a656-77f2-4f89-9251-c375f5752815
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780094801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.1780094801
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.2593628623
Short name T279
Test name
Test status
Simulation time 103783310 ps
CPU time 0.71 seconds
Started Aug 18 05:41:37 PM PDT 24
Finished Aug 18 05:41:38 PM PDT 24
Peak memory 195492 kb
Host smart-733572a0-3ffb-4caf-8b7c-cace32c8edf4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593628623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.2593628623
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.4018501714
Short name T220
Test name
Test status
Simulation time 305398270 ps
CPU time 3.12 seconds
Started Aug 18 05:41:36 PM PDT 24
Finished Aug 18 05:41:40 PM PDT 24
Peak memory 198248 kb
Host smart-c0a40a1e-f4b9-4c76-b55b-fa41f2cc83ad
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018501714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.4018501714
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.3305823927
Short name T373
Test name
Test status
Simulation time 102160500 ps
CPU time 1.93 seconds
Started Aug 18 05:41:49 PM PDT 24
Finished Aug 18 05:41:51 PM PDT 24
Peak memory 195940 kb
Host smart-1d4ba609-c12c-49ae-840c-179d0e4e2391
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305823927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.3305823927
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.2981911965
Short name T191
Test name
Test status
Simulation time 27576992 ps
CPU time 0.84 seconds
Started Aug 18 05:41:38 PM PDT 24
Finished Aug 18 05:41:39 PM PDT 24
Peak memory 196264 kb
Host smart-85b864b5-2977-4fbc-b62f-b784a0357ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981911965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.2981911965
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.2786990114
Short name T629
Test name
Test status
Simulation time 34488952 ps
CPU time 0.82 seconds
Started Aug 18 05:41:36 PM PDT 24
Finished Aug 18 05:41:36 PM PDT 24
Peak memory 195616 kb
Host smart-63588f6d-103f-4a94-8d0a-52cdc284d88a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786990114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.2786990114
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.3634834969
Short name T270
Test name
Test status
Simulation time 177262121 ps
CPU time 3.05 seconds
Started Aug 18 05:41:27 PM PDT 24
Finished Aug 18 05:41:30 PM PDT 24
Peak memory 198116 kb
Host smart-31c46e1d-7b08-4d0e-b087-7ccd10647834
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634834969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.3634834969
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.1979147523
Short name T441
Test name
Test status
Simulation time 818722581 ps
CPU time 1.32 seconds
Started Aug 18 05:41:36 PM PDT 24
Finished Aug 18 05:41:38 PM PDT 24
Peak memory 198280 kb
Host smart-630866cf-603c-4a6e-a47d-89a0b4adff61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979147523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.1979147523
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.16877204
Short name T331
Test name
Test status
Simulation time 430865932 ps
CPU time 1.08 seconds
Started Aug 18 05:41:44 PM PDT 24
Finished Aug 18 05:41:45 PM PDT 24
Peak memory 195956 kb
Host smart-3350e88e-fdf0-4c53-b0ad-d01ea1ae3497
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16877204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.16877204
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.3575670956
Short name T252
Test name
Test status
Simulation time 3314381359 ps
CPU time 81.36 seconds
Started Aug 18 05:41:38 PM PDT 24
Finished Aug 18 05:43:00 PM PDT 24
Peak memory 198336 kb
Host smart-93c7794f-8e0d-4dd3-a533-25ea6cbfaa08
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575670956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.3575670956
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_stress_all_with_rand_reset.575518861
Short name T66
Test name
Test status
Simulation time 25943837834 ps
CPU time 197.22 seconds
Started Aug 18 05:41:49 PM PDT 24
Finished Aug 18 05:45:07 PM PDT 24
Peak memory 198512 kb
Host smart-4d3421e9-6870-4cfc-ab49-06f5fb63fbe6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=575518861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_stress_all_with_rand_reset.575518861
Directory /workspace/42.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.gpio_alert_test.1684001406
Short name T495
Test name
Test status
Simulation time 39848218 ps
CPU time 0.56 seconds
Started Aug 18 05:41:33 PM PDT 24
Finished Aug 18 05:41:34 PM PDT 24
Peak memory 194792 kb
Host smart-5f46bafd-c4f4-4a51-ad6f-654b3d3ed268
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684001406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.1684001406
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.1718398034
Short name T255
Test name
Test status
Simulation time 166383318 ps
CPU time 0.61 seconds
Started Aug 18 05:41:37 PM PDT 24
Finished Aug 18 05:41:38 PM PDT 24
Peak memory 194840 kb
Host smart-7d44a080-ad4b-4e2d-8e74-04f08d09c7b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718398034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.1718398034
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.2817119559
Short name T377
Test name
Test status
Simulation time 921435457 ps
CPU time 15.02 seconds
Started Aug 18 05:42:20 PM PDT 24
Finished Aug 18 05:42:35 PM PDT 24
Peak memory 197032 kb
Host smart-73d575ff-1f53-4081-8902-7a1838d813a5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817119559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.2817119559
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.932662583
Short name T549
Test name
Test status
Simulation time 28945687 ps
CPU time 0.78 seconds
Started Aug 18 05:41:44 PM PDT 24
Finished Aug 18 05:41:44 PM PDT 24
Peak memory 194796 kb
Host smart-fec50b6a-1911-4920-978e-647cf60c4467
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932662583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.932662583
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.3946383320
Short name T340
Test name
Test status
Simulation time 206090684 ps
CPU time 1.28 seconds
Started Aug 18 05:41:23 PM PDT 24
Finished Aug 18 05:41:24 PM PDT 24
Peak memory 197380 kb
Host smart-e82c3f73-050a-446b-97d8-f1b292c55f78
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946383320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.3946383320
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.1068087951
Short name T435
Test name
Test status
Simulation time 77633094 ps
CPU time 1.01 seconds
Started Aug 18 05:41:31 PM PDT 24
Finished Aug 18 05:41:33 PM PDT 24
Peak memory 196488 kb
Host smart-2a230a8d-c0e2-4ed8-be83-386801e36a79
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068087951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.1068087951
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.403777400
Short name T155
Test name
Test status
Simulation time 81668658 ps
CPU time 1.87 seconds
Started Aug 18 05:41:35 PM PDT 24
Finished Aug 18 05:41:37 PM PDT 24
Peak memory 196164 kb
Host smart-c286741c-1075-44de-9190-db784d43ffe5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403777400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger.
403777400
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.2982597484
Short name T409
Test name
Test status
Simulation time 538397203 ps
CPU time 1 seconds
Started Aug 18 05:41:37 PM PDT 24
Finished Aug 18 05:41:38 PM PDT 24
Peak memory 196212 kb
Host smart-7c919f7e-23de-4050-9f9d-3556768636ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982597484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.2982597484
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.1821307462
Short name T11
Test name
Test status
Simulation time 22631462 ps
CPU time 0.66 seconds
Started Aug 18 05:41:47 PM PDT 24
Finished Aug 18 05:41:48 PM PDT 24
Peak memory 194416 kb
Host smart-90b7c606-13b8-4bd2-9f24-5cf1525d830c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821307462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.1821307462
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.3635319803
Short name T24
Test name
Test status
Simulation time 313122770 ps
CPU time 2.94 seconds
Started Aug 18 05:41:33 PM PDT 24
Finished Aug 18 05:41:36 PM PDT 24
Peak memory 198124 kb
Host smart-2746bef2-7722-4bda-8341-5f2ed7218983
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635319803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.3635319803
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.4006579460
Short name T497
Test name
Test status
Simulation time 51336529 ps
CPU time 0.93 seconds
Started Aug 18 05:41:37 PM PDT 24
Finished Aug 18 05:41:38 PM PDT 24
Peak memory 196580 kb
Host smart-cd9185f4-ad48-4f3d-96c0-3247f71b1b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006579460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.4006579460
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.3572590463
Short name T611
Test name
Test status
Simulation time 130789197 ps
CPU time 0.82 seconds
Started Aug 18 05:41:32 PM PDT 24
Finished Aug 18 05:41:33 PM PDT 24
Peak memory 195236 kb
Host smart-1b0154ca-7e44-4bf8-a9d9-ea9012b3ff51
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572590463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.3572590463
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.1431237159
Short name T329
Test name
Test status
Simulation time 880521440 ps
CPU time 25.15 seconds
Started Aug 18 05:41:21 PM PDT 24
Finished Aug 18 05:41:46 PM PDT 24
Peak memory 198232 kb
Host smart-94ac1c8e-b893-4f10-aaf7-d037442255c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431237159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.1431237159
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_stress_all_with_rand_reset.1749737456
Short name T569
Test name
Test status
Simulation time 8211190518 ps
CPU time 149.64 seconds
Started Aug 18 05:41:40 PM PDT 24
Finished Aug 18 05:44:09 PM PDT 24
Peak memory 198596 kb
Host smart-ae6e3dc9-7184-4fa1-8755-9f0bf95491e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1749737456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_stress_all_with_rand_reset.1749737456
Directory /workspace/43.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.gpio_alert_test.2456358185
Short name T57
Test name
Test status
Simulation time 19838670 ps
CPU time 0.54 seconds
Started Aug 18 05:41:38 PM PDT 24
Finished Aug 18 05:41:39 PM PDT 24
Peak memory 194012 kb
Host smart-d48a699d-69dd-4a8a-a9f2-bf65bae4ff86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456358185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.2456358185
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.2707629866
Short name T620
Test name
Test status
Simulation time 131800934 ps
CPU time 0.93 seconds
Started Aug 18 05:41:52 PM PDT 24
Finished Aug 18 05:41:53 PM PDT 24
Peak memory 196676 kb
Host smart-355e7c08-2076-48ea-b4a1-73a693a660a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707629866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.2707629866
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.2401721064
Short name T451
Test name
Test status
Simulation time 680261771 ps
CPU time 3.15 seconds
Started Aug 18 05:41:38 PM PDT 24
Finished Aug 18 05:41:41 PM PDT 24
Peak memory 196872 kb
Host smart-ff5bb20e-e39c-4a3f-a3c0-1e30f5b8b143
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401721064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.2401721064
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.732989368
Short name T399
Test name
Test status
Simulation time 103560817 ps
CPU time 0.67 seconds
Started Aug 18 05:41:28 PM PDT 24
Finished Aug 18 05:41:29 PM PDT 24
Peak memory 194756 kb
Host smart-12eb0a1c-4af2-4954-bc96-18db3c51c88a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732989368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.732989368
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.1912985769
Short name T537
Test name
Test status
Simulation time 44272382 ps
CPU time 1.14 seconds
Started Aug 18 05:41:31 PM PDT 24
Finished Aug 18 05:41:33 PM PDT 24
Peak memory 196112 kb
Host smart-1c542ccc-e53b-4d99-bea9-10e8a15a2e3f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912985769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.1912985769
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.2631888453
Short name T598
Test name
Test status
Simulation time 81902932 ps
CPU time 2.95 seconds
Started Aug 18 05:41:31 PM PDT 24
Finished Aug 18 05:41:34 PM PDT 24
Peak memory 196600 kb
Host smart-6905a9c4-e6c0-4629-acfb-999d15e3e917
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631888453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.2631888453
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.452259373
Short name T636
Test name
Test status
Simulation time 165459748 ps
CPU time 1.7 seconds
Started Aug 18 05:41:46 PM PDT 24
Finished Aug 18 05:41:48 PM PDT 24
Peak memory 196148 kb
Host smart-e008e09c-c50d-4c2d-8027-344c71e09a1e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452259373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger.
452259373
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.447675810
Short name T222
Test name
Test status
Simulation time 35637903 ps
CPU time 0.88 seconds
Started Aug 18 05:41:44 PM PDT 24
Finished Aug 18 05:41:45 PM PDT 24
Peak memory 196916 kb
Host smart-c5f8b9d5-ee01-4fc2-a997-5d1fa851652b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447675810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.447675810
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.1007700691
Short name T668
Test name
Test status
Simulation time 68039962 ps
CPU time 0.71 seconds
Started Aug 18 05:41:43 PM PDT 24
Finished Aug 18 05:41:44 PM PDT 24
Peak memory 195572 kb
Host smart-f8387bef-2d20-4457-81fa-65bc3e2901a4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007700691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.1007700691
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.4291851435
Short name T572
Test name
Test status
Simulation time 1305327306 ps
CPU time 4.71 seconds
Started Aug 18 05:41:42 PM PDT 24
Finished Aug 18 05:41:47 PM PDT 24
Peak memory 198108 kb
Host smart-06787e88-4211-437b-b75f-8f9b441098a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291851435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.4291851435
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.1371357251
Short name T325
Test name
Test status
Simulation time 44459055 ps
CPU time 1.23 seconds
Started Aug 18 05:41:32 PM PDT 24
Finished Aug 18 05:41:34 PM PDT 24
Peak memory 198136 kb
Host smart-e43d7fc8-3690-4080-87e1-94d46778d6de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371357251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.1371357251
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.3347062614
Short name T235
Test name
Test status
Simulation time 58840103 ps
CPU time 1.17 seconds
Started Aug 18 05:41:30 PM PDT 24
Finished Aug 18 05:41:31 PM PDT 24
Peak memory 195884 kb
Host smart-00946feb-eb54-499a-9e06-b52ac0793542
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347062614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.3347062614
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.152316605
Short name T146
Test name
Test status
Simulation time 3920497683 ps
CPU time 93.82 seconds
Started Aug 18 05:41:30 PM PDT 24
Finished Aug 18 05:43:04 PM PDT 24
Peak memory 198388 kb
Host smart-53805506-a67a-432d-876d-9b2c23bc5bd7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152316605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.g
pio_stress_all.152316605
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_alert_test.1894844670
Short name T55
Test name
Test status
Simulation time 111395238 ps
CPU time 0.56 seconds
Started Aug 18 05:41:33 PM PDT 24
Finished Aug 18 05:41:34 PM PDT 24
Peak memory 194032 kb
Host smart-50e4e343-3a2e-4a52-819f-a995dc090ad6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894844670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.1894844670
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.2146663468
Short name T187
Test name
Test status
Simulation time 37616467 ps
CPU time 0.77 seconds
Started Aug 18 05:41:26 PM PDT 24
Finished Aug 18 05:41:27 PM PDT 24
Peak memory 196208 kb
Host smart-db86bc86-5711-45ec-89f3-47617a490154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146663468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.2146663468
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.3638206609
Short name T440
Test name
Test status
Simulation time 2512234821 ps
CPU time 15.62 seconds
Started Aug 18 05:41:37 PM PDT 24
Finished Aug 18 05:41:53 PM PDT 24
Peak memory 196940 kb
Host smart-d6ef633c-b458-45d8-bb29-f77cc51bd139
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638206609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.3638206609
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.2824713696
Short name T143
Test name
Test status
Simulation time 157838385 ps
CPU time 0.71 seconds
Started Aug 18 05:41:40 PM PDT 24
Finished Aug 18 05:41:41 PM PDT 24
Peak memory 195544 kb
Host smart-a97b8018-93cc-4ea3-b819-76a7e2a04266
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824713696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.2824713696
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.1583976119
Short name T71
Test name
Test status
Simulation time 125737551 ps
CPU time 0.87 seconds
Started Aug 18 05:41:32 PM PDT 24
Finished Aug 18 05:41:33 PM PDT 24
Peak memory 196756 kb
Host smart-1cd768f5-e659-4e02-a035-b1b9e556e53e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583976119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.1583976119
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.1906292315
Short name T184
Test name
Test status
Simulation time 79940220 ps
CPU time 3.22 seconds
Started Aug 18 05:41:36 PM PDT 24
Finished Aug 18 05:41:39 PM PDT 24
Peak memory 198184 kb
Host smart-bfeece44-bd81-4882-ab99-9d525f10521b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906292315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.1906292315
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.304104494
Short name T341
Test name
Test status
Simulation time 307160437 ps
CPU time 1.83 seconds
Started Aug 18 05:41:38 PM PDT 24
Finished Aug 18 05:41:40 PM PDT 24
Peak memory 196184 kb
Host smart-64b457f6-0a5b-43b3-8a8b-7378e1de6813
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304104494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger.
304104494
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.1160250668
Short name T596
Test name
Test status
Simulation time 50480641 ps
CPU time 1.16 seconds
Started Aug 18 05:41:45 PM PDT 24
Finished Aug 18 05:41:46 PM PDT 24
Peak memory 196280 kb
Host smart-d662eb1b-c9db-4bb3-ab56-2abb02e1b7ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160250668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.1160250668
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.2870998904
Short name T319
Test name
Test status
Simulation time 88400868 ps
CPU time 0.79 seconds
Started Aug 18 05:41:54 PM PDT 24
Finished Aug 18 05:41:55 PM PDT 24
Peak memory 197560 kb
Host smart-9e8b7abd-b7c1-4ce5-909f-dfaad0203acb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870998904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.2870998904
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.2610020318
Short name T228
Test name
Test status
Simulation time 131213533 ps
CPU time 3.29 seconds
Started Aug 18 05:41:39 PM PDT 24
Finished Aug 18 05:41:43 PM PDT 24
Peak memory 198184 kb
Host smart-72df532c-bae3-4baf-82fc-42bf433c9cdd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610020318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.2610020318
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.3620231773
Short name T266
Test name
Test status
Simulation time 179259543 ps
CPU time 1.11 seconds
Started Aug 18 05:41:35 PM PDT 24
Finished Aug 18 05:41:36 PM PDT 24
Peak memory 195980 kb
Host smart-6aaea03a-26e3-42f1-b0dc-0c8da814df06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620231773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.3620231773
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.958336081
Short name T488
Test name
Test status
Simulation time 43211900 ps
CPU time 0.92 seconds
Started Aug 18 05:41:39 PM PDT 24
Finished Aug 18 05:41:40 PM PDT 24
Peak memory 195732 kb
Host smart-de519f95-f4c6-4ec4-b667-49d9a948280f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958336081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.958336081
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.2538998995
Short name T365
Test name
Test status
Simulation time 29592602513 ps
CPU time 149.89 seconds
Started Aug 18 05:41:48 PM PDT 24
Finished Aug 18 05:44:18 PM PDT 24
Peak memory 198336 kb
Host smart-042fa434-579c-49a5-aae5-402473297445
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538998995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.2538998995
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_alert_test.4229260432
Short name T179
Test name
Test status
Simulation time 14597041 ps
CPU time 0.55 seconds
Started Aug 18 05:41:41 PM PDT 24
Finished Aug 18 05:41:42 PM PDT 24
Peak memory 194256 kb
Host smart-5e2f80c9-7cfb-405a-9cfd-2209e9451fb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229260432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.4229260432
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.470658057
Short name T26
Test name
Test status
Simulation time 27276425 ps
CPU time 0.92 seconds
Started Aug 18 05:41:35 PM PDT 24
Finished Aug 18 05:41:36 PM PDT 24
Peak memory 197308 kb
Host smart-07f383e2-0759-42cf-821c-d59052f8e765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470658057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.470658057
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.4083867737
Short name T406
Test name
Test status
Simulation time 388461876 ps
CPU time 5.69 seconds
Started Aug 18 05:41:57 PM PDT 24
Finished Aug 18 05:42:03 PM PDT 24
Peak memory 196864 kb
Host smart-0de0d2a0-9838-4768-87bb-6718f73c8c73
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083867737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.4083867737
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.1935980457
Short name T239
Test name
Test status
Simulation time 327575233 ps
CPU time 0.64 seconds
Started Aug 18 05:41:46 PM PDT 24
Finished Aug 18 05:41:47 PM PDT 24
Peak memory 194652 kb
Host smart-d957c624-8ce6-492b-b642-4c09b7530585
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935980457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.1935980457
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.669511724
Short name T692
Test name
Test status
Simulation time 34918441 ps
CPU time 0.8 seconds
Started Aug 18 05:41:58 PM PDT 24
Finished Aug 18 05:41:59 PM PDT 24
Peak memory 195372 kb
Host smart-60e95bd9-02cb-4460-88f7-2081d897e6c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669511724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.669511724
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.1575219127
Short name T196
Test name
Test status
Simulation time 151331137 ps
CPU time 2.79 seconds
Started Aug 18 05:41:33 PM PDT 24
Finished Aug 18 05:41:35 PM PDT 24
Peak memory 198184 kb
Host smart-997f1a26-1ab9-45fa-a408-bd18c23d22c2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575219127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.1575219127
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.2538277373
Short name T197
Test name
Test status
Simulation time 490427344 ps
CPU time 2.94 seconds
Started Aug 18 05:41:40 PM PDT 24
Finished Aug 18 05:41:44 PM PDT 24
Peak memory 198248 kb
Host smart-c820c3b8-99cf-4a0f-823b-648e6f590b43
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538277373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.2538277373
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.1428523340
Short name T591
Test name
Test status
Simulation time 170362180 ps
CPU time 0.96 seconds
Started Aug 18 05:41:48 PM PDT 24
Finished Aug 18 05:41:50 PM PDT 24
Peak memory 196100 kb
Host smart-74a35620-decd-4a7b-b7c2-77ebd8a08dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428523340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.1428523340
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.1912071911
Short name T302
Test name
Test status
Simulation time 281659645 ps
CPU time 0.79 seconds
Started Aug 18 05:42:01 PM PDT 24
Finished Aug 18 05:42:02 PM PDT 24
Peak memory 195456 kb
Host smart-a57a6246-0dda-4543-b421-a98935f70962
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912071911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.1912071911
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.3468361057
Short name T73
Test name
Test status
Simulation time 334688880 ps
CPU time 2.29 seconds
Started Aug 18 05:41:35 PM PDT 24
Finished Aug 18 05:41:37 PM PDT 24
Peak memory 198192 kb
Host smart-73f91af4-ce40-4e4f-abde-e4676d2f780c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468361057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.3468361057
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.1409722155
Short name T610
Test name
Test status
Simulation time 77567312 ps
CPU time 1.21 seconds
Started Aug 18 05:41:44 PM PDT 24
Finished Aug 18 05:41:46 PM PDT 24
Peak memory 196460 kb
Host smart-1813f25a-f331-4055-ab59-6adc3de034a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409722155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.1409722155
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.187889896
Short name T109
Test name
Test status
Simulation time 51171417 ps
CPU time 1.06 seconds
Started Aug 18 05:41:42 PM PDT 24
Finished Aug 18 05:41:43 PM PDT 24
Peak memory 196384 kb
Host smart-8a203214-3999-406a-aa29-325b50aa50ef
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187889896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.187889896
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.229091606
Short name T691
Test name
Test status
Simulation time 8044466591 ps
CPU time 98.39 seconds
Started Aug 18 05:41:49 PM PDT 24
Finished Aug 18 05:43:27 PM PDT 24
Peak memory 198340 kb
Host smart-ac95fa71-a922-43fc-9f03-649cd40478e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229091606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.g
pio_stress_all.229091606
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_alert_test.2708740284
Short name T348
Test name
Test status
Simulation time 21058948 ps
CPU time 0.57 seconds
Started Aug 18 05:41:48 PM PDT 24
Finished Aug 18 05:41:49 PM PDT 24
Peak memory 194004 kb
Host smart-2a442ff0-4f3b-4c13-9453-8e47cdf05e13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708740284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.2708740284
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.3298125265
Short name T504
Test name
Test status
Simulation time 53497485 ps
CPU time 0.7 seconds
Started Aug 18 05:41:39 PM PDT 24
Finished Aug 18 05:41:39 PM PDT 24
Peak memory 194272 kb
Host smart-df151233-0b95-4319-ab48-bc32d49af1da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298125265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.3298125265
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.1351719404
Short name T214
Test name
Test status
Simulation time 685397475 ps
CPU time 19.42 seconds
Started Aug 18 05:42:13 PM PDT 24
Finished Aug 18 05:42:37 PM PDT 24
Peak memory 196436 kb
Host smart-a246cf57-03df-43ea-a5bd-fdfbdb933133
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351719404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.1351719404
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.3846854496
Short name T182
Test name
Test status
Simulation time 135786774 ps
CPU time 0.98 seconds
Started Aug 18 05:41:48 PM PDT 24
Finished Aug 18 05:41:49 PM PDT 24
Peak memory 196444 kb
Host smart-dd45675d-a78c-4565-af3b-96c43db921b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846854496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.3846854496
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.596724587
Short name T425
Test name
Test status
Simulation time 1291889825 ps
CPU time 1.12 seconds
Started Aug 18 05:41:38 PM PDT 24
Finished Aug 18 05:41:40 PM PDT 24
Peak memory 196912 kb
Host smart-fe31a7a6-c4ae-4ecc-a28a-1af3cad9e032
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596724587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.596724587
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.699985989
Short name T475
Test name
Test status
Simulation time 34369694 ps
CPU time 1.43 seconds
Started Aug 18 05:41:43 PM PDT 24
Finished Aug 18 05:41:45 PM PDT 24
Peak memory 196692 kb
Host smart-1920621e-5475-472a-901a-d372d3e39fca
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699985989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 47.gpio_intr_with_filter_rand_intr_event.699985989
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.422563575
Short name T349
Test name
Test status
Simulation time 151695835 ps
CPU time 1.89 seconds
Started Aug 18 05:41:36 PM PDT 24
Finished Aug 18 05:41:39 PM PDT 24
Peak memory 196836 kb
Host smart-5853173c-0aee-49af-b98a-8dd6630a9c4e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422563575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger.
422563575
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.3207582819
Short name T562
Test name
Test status
Simulation time 95240470 ps
CPU time 1.17 seconds
Started Aug 18 05:41:42 PM PDT 24
Finished Aug 18 05:41:43 PM PDT 24
Peak memory 196256 kb
Host smart-c86734b1-4045-4c5e-99a3-21b241f5a8cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207582819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.3207582819
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.1758459623
Short name T664
Test name
Test status
Simulation time 774168221 ps
CPU time 1 seconds
Started Aug 18 05:41:58 PM PDT 24
Finished Aug 18 05:41:59 PM PDT 24
Peak memory 196064 kb
Host smart-65611b9f-eec9-45df-9825-3bcae6bd3e23
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758459623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.1758459623
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.2872456587
Short name T364
Test name
Test status
Simulation time 126741343 ps
CPU time 2.36 seconds
Started Aug 18 05:41:50 PM PDT 24
Finished Aug 18 05:41:52 PM PDT 24
Peak memory 198132 kb
Host smart-37205337-6f06-46db-beb5-47a145811f82
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872456587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.2872456587
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.4168560861
Short name T708
Test name
Test status
Simulation time 66469519 ps
CPU time 0.95 seconds
Started Aug 18 05:41:43 PM PDT 24
Finished Aug 18 05:41:44 PM PDT 24
Peak memory 196520 kb
Host smart-bed56d1e-cd73-483b-b890-d8f175a1e662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168560861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.4168560861
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.2599008376
Short name T515
Test name
Test status
Simulation time 43842508 ps
CPU time 0.98 seconds
Started Aug 18 05:41:52 PM PDT 24
Finished Aug 18 05:41:53 PM PDT 24
Peak memory 196576 kb
Host smart-5c73de44-80a9-4987-b463-6c033e7d03f5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599008376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.2599008376
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.801629111
Short name T307
Test name
Test status
Simulation time 11899479847 ps
CPU time 76.99 seconds
Started Aug 18 05:41:48 PM PDT 24
Finished Aug 18 05:43:06 PM PDT 24
Peak memory 198360 kb
Host smart-ac00c8a8-196e-4a16-8707-e61caf6d1098
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801629111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.g
pio_stress_all.801629111
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_stress_all_with_rand_reset.908073486
Short name T709
Test name
Test status
Simulation time 10510444454 ps
CPU time 88.09 seconds
Started Aug 18 05:41:54 PM PDT 24
Finished Aug 18 05:43:27 PM PDT 24
Peak memory 198584 kb
Host smart-d9d5f41f-52d0-4058-ab6c-cf32ddfc1461
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=908073486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_stress_all_with_rand_reset.908073486
Directory /workspace/47.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.gpio_alert_test.4133967889
Short name T216
Test name
Test status
Simulation time 15368315 ps
CPU time 0.61 seconds
Started Aug 18 05:42:09 PM PDT 24
Finished Aug 18 05:42:10 PM PDT 24
Peak memory 194208 kb
Host smart-02e7a621-e048-40f8-b3be-3ce061244cc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133967889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.4133967889
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.1116870070
Short name T442
Test name
Test status
Simulation time 114234456 ps
CPU time 0.89 seconds
Started Aug 18 05:41:44 PM PDT 24
Finished Aug 18 05:41:45 PM PDT 24
Peak memory 196888 kb
Host smart-0d6d9062-f423-418f-ba39-820e2635adef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116870070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.1116870070
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.146960641
Short name T626
Test name
Test status
Simulation time 1922543928 ps
CPU time 22.03 seconds
Started Aug 18 05:41:47 PM PDT 24
Finished Aug 18 05:42:09 PM PDT 24
Peak memory 197152 kb
Host smart-7a201b2c-3b08-43e1-b6d6-86c45d62489a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146960641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stres
s.146960641
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.2138740381
Short name T8
Test name
Test status
Simulation time 348084294 ps
CPU time 1.03 seconds
Started Aug 18 05:42:12 PM PDT 24
Finished Aug 18 05:42:14 PM PDT 24
Peak memory 196728 kb
Host smart-e2056a5d-4e35-423d-afbf-b8c416a27147
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138740381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.2138740381
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.3705450323
Short name T644
Test name
Test status
Simulation time 65532053 ps
CPU time 0.76 seconds
Started Aug 18 05:41:53 PM PDT 24
Finished Aug 18 05:41:54 PM PDT 24
Peak memory 195408 kb
Host smart-02446d1c-b13e-49a1-907c-6dbd7fff9299
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705450323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.3705450323
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.406106804
Short name T153
Test name
Test status
Simulation time 41338617 ps
CPU time 1.63 seconds
Started Aug 18 05:41:54 PM PDT 24
Finished Aug 18 05:41:55 PM PDT 24
Peak memory 198260 kb
Host smart-7ecb9e7a-f029-488f-b34d-9d4ad6196c6e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406106804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 48.gpio_intr_with_filter_rand_intr_event.406106804
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.873881086
Short name T135
Test name
Test status
Simulation time 631606703 ps
CPU time 2.89 seconds
Started Aug 18 05:41:43 PM PDT 24
Finished Aug 18 05:41:46 PM PDT 24
Peak memory 198200 kb
Host smart-9b73c21a-f016-4f41-a6cc-052c038e084f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873881086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger.
873881086
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.2552459881
Short name T168
Test name
Test status
Simulation time 130978878 ps
CPU time 1.2 seconds
Started Aug 18 05:41:52 PM PDT 24
Finished Aug 18 05:41:54 PM PDT 24
Peak memory 196992 kb
Host smart-0e9312bf-a086-4263-b766-81fcf65ca3ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552459881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.2552459881
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.785673865
Short name T688
Test name
Test status
Simulation time 26807376 ps
CPU time 0.72 seconds
Started Aug 18 05:41:53 PM PDT 24
Finished Aug 18 05:41:54 PM PDT 24
Peak memory 196220 kb
Host smart-01f8e8c2-c9b2-49f7-ab31-60ea8a487b2f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785673865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullup
_pulldown.785673865
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.4159824368
Short name T703
Test name
Test status
Simulation time 422579240 ps
CPU time 4.69 seconds
Started Aug 18 05:41:37 PM PDT 24
Finished Aug 18 05:41:42 PM PDT 24
Peak memory 198056 kb
Host smart-f79d58a9-562b-4de7-b1cf-2703de936a99
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159824368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.4159824368
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.835705085
Short name T698
Test name
Test status
Simulation time 78160965 ps
CPU time 1.15 seconds
Started Aug 18 05:41:53 PM PDT 24
Finished Aug 18 05:41:55 PM PDT 24
Peak memory 195896 kb
Host smart-fbbb95ac-a7cc-4ace-b03b-5033100d9e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835705085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.835705085
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.2934763269
Short name T681
Test name
Test status
Simulation time 43294006 ps
CPU time 0.78 seconds
Started Aug 18 05:41:44 PM PDT 24
Finished Aug 18 05:41:45 PM PDT 24
Peak memory 196168 kb
Host smart-167ad67b-1a90-430e-8a46-e9d142f7a0be
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934763269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.2934763269
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.1598172257
Short name T361
Test name
Test status
Simulation time 209033548088 ps
CPU time 152.5 seconds
Started Aug 18 05:41:58 PM PDT 24
Finished Aug 18 05:44:30 PM PDT 24
Peak memory 198324 kb
Host smart-e66c9a43-9569-4569-8178-6a281bb74aae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598172257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.1598172257
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_alert_test.1269173404
Short name T553
Test name
Test status
Simulation time 28097667 ps
CPU time 0.54 seconds
Started Aug 18 05:41:56 PM PDT 24
Finished Aug 18 05:41:58 PM PDT 24
Peak memory 194720 kb
Host smart-99b40a4d-33a7-444d-83d3-f67d89963962
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269173404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.1269173404
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.52342296
Short name T418
Test name
Test status
Simulation time 34928206 ps
CPU time 0.68 seconds
Started Aug 18 05:41:46 PM PDT 24
Finished Aug 18 05:41:47 PM PDT 24
Peak memory 194344 kb
Host smart-9bd2b774-55f8-4518-8f1c-b63ccf4c0385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52342296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.52342296
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.2193939833
Short name T543
Test name
Test status
Simulation time 102735314 ps
CPU time 5.28 seconds
Started Aug 18 05:41:58 PM PDT 24
Finished Aug 18 05:42:04 PM PDT 24
Peak memory 197340 kb
Host smart-fcc43cb9-ed2b-4c78-9af6-7933a94aa06b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193939833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.2193939833
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.2497816591
Short name T261
Test name
Test status
Simulation time 104648628 ps
CPU time 0.75 seconds
Started Aug 18 05:41:45 PM PDT 24
Finished Aug 18 05:41:46 PM PDT 24
Peak memory 196700 kb
Host smart-a9e77e65-3702-44d9-97d1-b0e8a94bc6e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497816591 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.2497816591
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.2692214328
Short name T385
Test name
Test status
Simulation time 29601756 ps
CPU time 0.79 seconds
Started Aug 18 05:42:12 PM PDT 24
Finished Aug 18 05:42:13 PM PDT 24
Peak memory 195452 kb
Host smart-29bf9679-500f-46ba-aa8e-fbeb5fe4c576
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692214328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.2692214328
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.3340811498
Short name T367
Test name
Test status
Simulation time 279487800 ps
CPU time 2.81 seconds
Started Aug 18 05:41:42 PM PDT 24
Finished Aug 18 05:41:45 PM PDT 24
Peak memory 198220 kb
Host smart-c32cbd01-fc2d-4586-9de4-5e2efdf205b6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340811498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.3340811498
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.1239069340
Short name T297
Test name
Test status
Simulation time 114161127 ps
CPU time 1.03 seconds
Started Aug 18 05:41:42 PM PDT 24
Finished Aug 18 05:41:43 PM PDT 24
Peak memory 195628 kb
Host smart-8edc90d2-9ef9-4042-9a73-cc9900875731
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239069340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.1239069340
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.1599425010
Short name T585
Test name
Test status
Simulation time 14081355 ps
CPU time 0.74 seconds
Started Aug 18 05:42:08 PM PDT 24
Finished Aug 18 05:42:09 PM PDT 24
Peak memory 195388 kb
Host smart-84b757d6-8af2-4d69-96c5-b0669150d8a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599425010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.1599425010
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.1373670124
Short name T108
Test name
Test status
Simulation time 80756257 ps
CPU time 0.92 seconds
Started Aug 18 05:41:46 PM PDT 24
Finished Aug 18 05:41:47 PM PDT 24
Peak memory 196744 kb
Host smart-d1a8133a-fc42-4469-ab5a-c3c9c4213208
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373670124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.1373670124
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.285183590
Short name T137
Test name
Test status
Simulation time 90237682 ps
CPU time 1.77 seconds
Started Aug 18 05:41:44 PM PDT 24
Finished Aug 18 05:41:46 PM PDT 24
Peak memory 198140 kb
Host smart-32c63830-a513-41c5-a597-f099867bad3f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285183590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ran
dom_long_reg_writes_reg_reads.285183590
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.190211688
Short name T502
Test name
Test status
Simulation time 175514249 ps
CPU time 0.88 seconds
Started Aug 18 05:42:25 PM PDT 24
Finished Aug 18 05:42:26 PM PDT 24
Peak memory 196424 kb
Host smart-5a430a75-4f0c-4eaf-a9ad-8ab20bf5214c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190211688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.190211688
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.2614186491
Short name T113
Test name
Test status
Simulation time 244711040 ps
CPU time 0.86 seconds
Started Aug 18 05:42:08 PM PDT 24
Finished Aug 18 05:42:09 PM PDT 24
Peak memory 196400 kb
Host smart-ac4a53d7-0c1c-48ca-8662-b6038d8b5998
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614186491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.2614186491
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.726724196
Short name T169
Test name
Test status
Simulation time 41128720431 ps
CPU time 180.86 seconds
Started Aug 18 05:41:42 PM PDT 24
Finished Aug 18 05:44:43 PM PDT 24
Peak memory 198332 kb
Host smart-a021af81-c2e4-47f6-a431-b2fa6190d35c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726724196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.g
pio_stress_all.726724196
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_alert_test.211415001
Short name T39
Test name
Test status
Simulation time 13436364 ps
CPU time 0.57 seconds
Started Aug 18 05:40:42 PM PDT 24
Finished Aug 18 05:40:43 PM PDT 24
Peak memory 194032 kb
Host smart-a467143b-ebd2-4db3-87dd-288fcc2d4d72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211415001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.211415001
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.2588850922
Short name T586
Test name
Test status
Simulation time 50740262 ps
CPU time 0.97 seconds
Started Aug 18 05:40:39 PM PDT 24
Finished Aug 18 05:40:40 PM PDT 24
Peak memory 196208 kb
Host smart-36fd86a4-0a58-4a71-95b6-d2316f474303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588850922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.2588850922
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.373056195
Short name T618
Test name
Test status
Simulation time 820916328 ps
CPU time 24.59 seconds
Started Aug 18 05:40:35 PM PDT 24
Finished Aug 18 05:40:59 PM PDT 24
Peak memory 198172 kb
Host smart-f5e0cf08-fc1e-4133-8cc4-3ad4230e8ee1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373056195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stress
.373056195
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.870586839
Short name T2
Test name
Test status
Simulation time 60500441 ps
CPU time 0.83 seconds
Started Aug 18 05:40:25 PM PDT 24
Finished Aug 18 05:40:26 PM PDT 24
Peak memory 195936 kb
Host smart-2298e35b-1961-4ebf-97ec-4e5baa8ea032
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870586839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.870586839
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.3051202990
Short name T203
Test name
Test status
Simulation time 151029076 ps
CPU time 1.41 seconds
Started Aug 18 05:40:27 PM PDT 24
Finished Aug 18 05:40:28 PM PDT 24
Peak memory 198132 kb
Host smart-b7e5f931-24e2-432c-9db8-9e5849e804bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051202990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.3051202990
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.2965200052
Short name T468
Test name
Test status
Simulation time 314736404 ps
CPU time 3.46 seconds
Started Aug 18 05:40:16 PM PDT 24
Finished Aug 18 05:40:20 PM PDT 24
Peak memory 198068 kb
Host smart-93587f60-1803-4261-bb3d-d3ee8e3211d9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965200052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.2965200052
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.2768240092
Short name T69
Test name
Test status
Simulation time 78717582 ps
CPU time 1.2 seconds
Started Aug 18 05:40:51 PM PDT 24
Finished Aug 18 05:40:52 PM PDT 24
Peak memory 195832 kb
Host smart-9d3026f1-3afb-4c9f-b828-d360ea8b0397
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768240092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
2768240092
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.3839631381
Short name T411
Test name
Test status
Simulation time 34393076 ps
CPU time 0.65 seconds
Started Aug 18 05:40:28 PM PDT 24
Finished Aug 18 05:40:31 PM PDT 24
Peak memory 195192 kb
Host smart-a4fe4d7b-a112-4eb0-9a5e-636f702f40d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839631381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.3839631381
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.3430776256
Short name T615
Test name
Test status
Simulation time 61908289 ps
CPU time 0.72 seconds
Started Aug 18 05:40:31 PM PDT 24
Finished Aug 18 05:40:32 PM PDT 24
Peak memory 195100 kb
Host smart-296143b6-ca70-4153-97af-564a8e8b9939
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430776256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.3430776256
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.251723651
Short name T296
Test name
Test status
Simulation time 227091828 ps
CPU time 2.68 seconds
Started Aug 18 05:40:19 PM PDT 24
Finished Aug 18 05:40:22 PM PDT 24
Peak memory 198124 kb
Host smart-b06c7e29-e541-4f12-bff3-3369578ceddc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251723651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand
om_long_reg_writes_reg_reads.251723651
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.2362511064
Short name T301
Test name
Test status
Simulation time 138608177 ps
CPU time 1.1 seconds
Started Aug 18 05:40:35 PM PDT 24
Finished Aug 18 05:40:36 PM PDT 24
Peak memory 195900 kb
Host smart-64a9557d-052b-4d81-ab10-1650fdf2f3fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362511064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.2362511064
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.4017928088
Short name T448
Test name
Test status
Simulation time 43799572 ps
CPU time 1.05 seconds
Started Aug 18 05:40:28 PM PDT 24
Finished Aug 18 05:40:29 PM PDT 24
Peak memory 195940 kb
Host smart-7067ac29-cfb7-4c8d-bb5c-4600a4e6cbe9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017928088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.4017928088
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_alert_test.857525535
Short name T263
Test name
Test status
Simulation time 46830951 ps
CPU time 0.57 seconds
Started Aug 18 05:40:31 PM PDT 24
Finished Aug 18 05:40:32 PM PDT 24
Peak memory 194228 kb
Host smart-2ca9feca-da64-4dfe-bb8c-f5fb3039d5c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857525535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.857525535
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.3244519721
Short name T251
Test name
Test status
Simulation time 52140871 ps
CPU time 0.65 seconds
Started Aug 18 05:40:15 PM PDT 24
Finished Aug 18 05:40:16 PM PDT 24
Peak memory 194840 kb
Host smart-37c24f5f-e0de-4fba-956f-2cc258f26b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244519721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.3244519721
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.3233817249
Short name T395
Test name
Test status
Simulation time 2644656773 ps
CPU time 21.07 seconds
Started Aug 18 05:40:33 PM PDT 24
Finished Aug 18 05:40:55 PM PDT 24
Peak memory 197656 kb
Host smart-23ef799f-da78-4c63-bdf9-25193e5992fe
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233817249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.3233817249
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.739006228
Short name T162
Test name
Test status
Simulation time 36687432 ps
CPU time 0.71 seconds
Started Aug 18 05:40:19 PM PDT 24
Finished Aug 18 05:40:20 PM PDT 24
Peak memory 194796 kb
Host smart-2d3fd424-70e4-43df-b120-c25a15000f0d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739006228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.739006228
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.2051258659
Short name T167
Test name
Test status
Simulation time 107945159 ps
CPU time 0.89 seconds
Started Aug 18 05:40:20 PM PDT 24
Finished Aug 18 05:40:21 PM PDT 24
Peak memory 196892 kb
Host smart-737b2ad6-abda-49c4-b2cd-39b5ab88dd32
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051258659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.2051258659
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.2742464967
Short name T173
Test name
Test status
Simulation time 265257338 ps
CPU time 2.77 seconds
Started Aug 18 05:40:12 PM PDT 24
Finished Aug 18 05:40:15 PM PDT 24
Peak memory 198224 kb
Host smart-ccd69a13-c54f-45fe-ba75-63fbde1244bd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742464967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.2742464967
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.623832783
Short name T512
Test name
Test status
Simulation time 305243033 ps
CPU time 3.19 seconds
Started Aug 18 05:40:47 PM PDT 24
Finished Aug 18 05:40:50 PM PDT 24
Peak memory 195916 kb
Host smart-99603464-bddc-4ab9-b29a-62a461336859
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623832783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.623832783
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.398169692
Short name T645
Test name
Test status
Simulation time 51110934 ps
CPU time 1 seconds
Started Aug 18 05:40:30 PM PDT 24
Finished Aug 18 05:40:31 PM PDT 24
Peak memory 195968 kb
Host smart-4bbeebe5-ae31-4533-a76a-92b12660a4d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398169692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.398169692
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.3435792042
Short name T246
Test name
Test status
Simulation time 34682987 ps
CPU time 1.23 seconds
Started Aug 18 05:40:12 PM PDT 24
Finished Aug 18 05:40:14 PM PDT 24
Peak memory 196972 kb
Host smart-83e585d8-e243-4329-ac8b-892fc7b94792
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435792042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup
_pulldown.3435792042
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.1443293222
Short name T370
Test name
Test status
Simulation time 887341483 ps
CPU time 5.03 seconds
Started Aug 18 05:40:33 PM PDT 24
Finished Aug 18 05:40:39 PM PDT 24
Peak memory 198084 kb
Host smart-4333535e-5e34-473d-8ce6-b55afcd24342
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443293222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran
dom_long_reg_writes_reg_reads.1443293222
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.1489675989
Short name T195
Test name
Test status
Simulation time 55155581 ps
CPU time 1.02 seconds
Started Aug 18 05:40:43 PM PDT 24
Finished Aug 18 05:40:45 PM PDT 24
Peak memory 196412 kb
Host smart-ffb14b04-4748-4743-84c8-3e3a84b42c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489675989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.1489675989
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.1735526545
Short name T624
Test name
Test status
Simulation time 207285607 ps
CPU time 0.98 seconds
Started Aug 18 05:40:38 PM PDT 24
Finished Aug 18 05:40:40 PM PDT 24
Peak memory 196676 kb
Host smart-6b79fe82-8f76-4754-a842-9d0c00a81cf5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735526545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.1735526545
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.1276330693
Short name T446
Test name
Test status
Simulation time 6619126447 ps
CPU time 49.16 seconds
Started Aug 18 05:40:30 PM PDT 24
Finished Aug 18 05:41:19 PM PDT 24
Peak memory 198400 kb
Host smart-06d9d0fc-4293-49d1-b2f2-0f1ea7457e5d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276330693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.1276330693
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_alert_test.2963962170
Short name T651
Test name
Test status
Simulation time 22258880 ps
CPU time 0.58 seconds
Started Aug 18 05:40:19 PM PDT 24
Finished Aug 18 05:40:19 PM PDT 24
Peak memory 194232 kb
Host smart-66286a66-547b-4ac6-9380-37418fe98c1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963962170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.2963962170
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.3057455844
Short name T599
Test name
Test status
Simulation time 113024518 ps
CPU time 0.93 seconds
Started Aug 18 05:40:31 PM PDT 24
Finished Aug 18 05:40:32 PM PDT 24
Peak memory 196036 kb
Host smart-a79c16d9-5bcf-441d-9552-9edf60e8360f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057455844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.3057455844
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.2281537539
Short name T552
Test name
Test status
Simulation time 657186758 ps
CPU time 21.39 seconds
Started Aug 18 05:40:45 PM PDT 24
Finished Aug 18 05:41:06 PM PDT 24
Peak memory 198160 kb
Host smart-e5fe2b97-e094-476c-b048-163011407848
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281537539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.2281537539
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.3792865964
Short name T23
Test name
Test status
Simulation time 35328821 ps
CPU time 0.65 seconds
Started Aug 18 05:40:33 PM PDT 24
Finished Aug 18 05:40:34 PM PDT 24
Peak memory 194644 kb
Host smart-0c81f9c3-6a49-4b2c-8198-c8984d3e82fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792865964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.3792865964
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.3942678297
Short name T447
Test name
Test status
Simulation time 96008967 ps
CPU time 0.91 seconds
Started Aug 18 05:40:21 PM PDT 24
Finished Aug 18 05:40:22 PM PDT 24
Peak memory 196172 kb
Host smart-d0910130-b20d-454f-bdd0-9d3c147e0923
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942678297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.3942678297
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.2124314237
Short name T345
Test name
Test status
Simulation time 234053543 ps
CPU time 2.38 seconds
Started Aug 18 05:40:39 PM PDT 24
Finished Aug 18 05:40:41 PM PDT 24
Peak memory 198124 kb
Host smart-a033ab07-c031-44f6-bfb3-e871820d5ee1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124314237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.2124314237
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.4214059094
Short name T141
Test name
Test status
Simulation time 472444586 ps
CPU time 2.18 seconds
Started Aug 18 05:40:32 PM PDT 24
Finished Aug 18 05:40:35 PM PDT 24
Peak memory 198228 kb
Host smart-8c302c36-16fb-4c63-82c4-bd6f39e7df9e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214059094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
4214059094
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.4110075307
Short name T654
Test name
Test status
Simulation time 32327119 ps
CPU time 1.11 seconds
Started Aug 18 05:40:32 PM PDT 24
Finished Aug 18 05:40:34 PM PDT 24
Peak memory 197032 kb
Host smart-632e3e4e-fd52-493e-b762-f89255885b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110075307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.4110075307
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.2596037120
Short name T541
Test name
Test status
Simulation time 59984691 ps
CPU time 1.27 seconds
Started Aug 18 05:40:21 PM PDT 24
Finished Aug 18 05:40:23 PM PDT 24
Peak memory 195976 kb
Host smart-acba0abb-5b94-4b7c-8bef-19213cc19e27
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596037120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.2596037120
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.1797886665
Short name T10
Test name
Test status
Simulation time 1095890327 ps
CPU time 6.68 seconds
Started Aug 18 05:40:41 PM PDT 24
Finished Aug 18 05:40:48 PM PDT 24
Peak memory 198136 kb
Host smart-abf7b22f-dc54-4b10-9036-117794692466
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797886665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.1797886665
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.3127623825
Short name T530
Test name
Test status
Simulation time 39314226 ps
CPU time 0.85 seconds
Started Aug 18 05:40:48 PM PDT 24
Finished Aug 18 05:40:54 PM PDT 24
Peak memory 195256 kb
Host smart-db35dff8-d98a-467e-9dc8-0efe82975d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127623825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.3127623825
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.3033426564
Short name T560
Test name
Test status
Simulation time 34124502 ps
CPU time 0.87 seconds
Started Aug 18 05:40:33 PM PDT 24
Finished Aug 18 05:40:34 PM PDT 24
Peak memory 196232 kb
Host smart-c6bcf9fe-26e0-45d7-b017-dbe9409099a9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033426564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.3033426564
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.3335873863
Short name T401
Test name
Test status
Simulation time 72735520723 ps
CPU time 168.13 seconds
Started Aug 18 05:40:46 PM PDT 24
Finished Aug 18 05:43:34 PM PDT 24
Peak memory 198368 kb
Host smart-befa6650-946b-4735-9432-dc41e8c4ba3d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335873863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.g
pio_stress_all.3335873863
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_stress_all_with_rand_reset.424380824
Short name T609
Test name
Test status
Simulation time 1209504000 ps
CPU time 9.25 seconds
Started Aug 18 05:40:19 PM PDT 24
Finished Aug 18 05:40:29 PM PDT 24
Peak memory 198344 kb
Host smart-bfe37d09-6807-46bf-bd3b-4d90e6806ee6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=424380824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_stress_all_with_rand_reset.424380824
Directory /workspace/7.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.gpio_alert_test.2962350540
Short name T715
Test name
Test status
Simulation time 25079496 ps
CPU time 0.57 seconds
Started Aug 18 05:40:44 PM PDT 24
Finished Aug 18 05:40:45 PM PDT 24
Peak memory 194276 kb
Host smart-d106db7c-93e3-4f54-a3a2-5688929fcf5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962350540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.2962350540
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.3197273588
Short name T525
Test name
Test status
Simulation time 29534962 ps
CPU time 0.8 seconds
Started Aug 18 05:40:45 PM PDT 24
Finished Aug 18 05:40:46 PM PDT 24
Peak memory 196456 kb
Host smart-e1f2ea93-0ce9-4c00-9eb3-3d7e8590a320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197273588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.3197273588
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.3868866824
Short name T551
Test name
Test status
Simulation time 624763906 ps
CPU time 4.53 seconds
Started Aug 18 05:40:50 PM PDT 24
Finished Aug 18 05:40:55 PM PDT 24
Peak memory 195600 kb
Host smart-e1f624b2-d179-4619-bf5d-33eb6b44d6e4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868866824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.3868866824
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.4263199020
Short name T614
Test name
Test status
Simulation time 313070552 ps
CPU time 0.8 seconds
Started Aug 18 05:40:41 PM PDT 24
Finished Aug 18 05:40:42 PM PDT 24
Peak memory 196084 kb
Host smart-767a18f7-de31-4faf-ab64-ff750d336f4d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263199020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.4263199020
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.1197223382
Short name T53
Test name
Test status
Simulation time 71241006 ps
CPU time 1.03 seconds
Started Aug 18 05:40:31 PM PDT 24
Finished Aug 18 05:40:34 PM PDT 24
Peak memory 196240 kb
Host smart-ecf06996-cef4-4e6d-a955-23ba3da8f2ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197223382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.1197223382
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.2089947246
Short name T189
Test name
Test status
Simulation time 47969716 ps
CPU time 1.86 seconds
Started Aug 18 05:40:30 PM PDT 24
Finished Aug 18 05:40:32 PM PDT 24
Peak memory 196460 kb
Host smart-da644c34-faef-4a9b-8d84-2dec5ae496d6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089947246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.2089947246
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.3971804372
Short name T111
Test name
Test status
Simulation time 537756154 ps
CPU time 2.62 seconds
Started Aug 18 05:40:34 PM PDT 24
Finished Aug 18 05:40:37 PM PDT 24
Peak memory 197140 kb
Host smart-c34bdffd-6674-4747-afd2-1033ba0d2c0d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971804372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
3971804372
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.4186371132
Short name T285
Test name
Test status
Simulation time 36397399 ps
CPU time 0.86 seconds
Started Aug 18 05:40:41 PM PDT 24
Finished Aug 18 05:40:42 PM PDT 24
Peak memory 197320 kb
Host smart-bcf03ffc-1c30-4bdb-87ec-0b3826988666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186371132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.4186371132
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.3289983484
Short name T284
Test name
Test status
Simulation time 392953957 ps
CPU time 0.93 seconds
Started Aug 18 05:40:42 PM PDT 24
Finished Aug 18 05:40:43 PM PDT 24
Peak memory 196680 kb
Host smart-05e8dc9c-cd8f-4d1c-9446-5549229df7a9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289983484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.3289983484
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.69899622
Short name T180
Test name
Test status
Simulation time 152207941 ps
CPU time 2.52 seconds
Started Aug 18 05:40:41 PM PDT 24
Finished Aug 18 05:40:43 PM PDT 24
Peak memory 198176 kb
Host smart-243f80b5-6f81-4601-b68e-a7c32831433f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69899622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rando
m_long_reg_writes_reg_reads.69899622
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.558302216
Short name T229
Test name
Test status
Simulation time 31218146 ps
CPU time 0.75 seconds
Started Aug 18 05:40:30 PM PDT 24
Finished Aug 18 05:40:30 PM PDT 24
Peak memory 195152 kb
Host smart-4f5e6133-4aaf-4a2d-a143-6843595ff98c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558302216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.558302216
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.1107478555
Short name T482
Test name
Test status
Simulation time 61627657 ps
CPU time 0.99 seconds
Started Aug 18 05:40:26 PM PDT 24
Finished Aug 18 05:40:27 PM PDT 24
Peak memory 196684 kb
Host smart-00c0a43d-ff33-47dd-a68a-4c0f8f83390b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107478555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.1107478555
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.292674463
Short name T115
Test name
Test status
Simulation time 2002289594 ps
CPU time 47.66 seconds
Started Aug 18 05:40:38 PM PDT 24
Finished Aug 18 05:41:26 PM PDT 24
Peak memory 198156 kb
Host smart-bd418d5c-9e6e-4067-8949-604d6ef34042
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292674463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gp
io_stress_all.292674463
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_alert_test.449540587
Short name T677
Test name
Test status
Simulation time 27329353 ps
CPU time 0.56 seconds
Started Aug 18 05:40:49 PM PDT 24
Finished Aug 18 05:40:50 PM PDT 24
Peak memory 194764 kb
Host smart-8d58e346-f9ed-4c2c-92ee-505c23059c6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449540587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.449540587
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.2645224970
Short name T290
Test name
Test status
Simulation time 29740882 ps
CPU time 0.78 seconds
Started Aug 18 05:40:48 PM PDT 24
Finished Aug 18 05:40:49 PM PDT 24
Peak memory 195472 kb
Host smart-d7a1c4f7-accc-486b-b686-341cd7e61c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645224970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.2645224970
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.3093519327
Short name T481
Test name
Test status
Simulation time 374714437 ps
CPU time 9.66 seconds
Started Aug 18 05:40:48 PM PDT 24
Finished Aug 18 05:40:58 PM PDT 24
Peak memory 197276 kb
Host smart-90176abc-d1be-4140-92cb-1b4e95eaaebd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093519327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.3093519327
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.3247641852
Short name T671
Test name
Test status
Simulation time 31164524 ps
CPU time 0.61 seconds
Started Aug 18 05:40:31 PM PDT 24
Finished Aug 18 05:40:31 PM PDT 24
Peak memory 194456 kb
Host smart-4fd5efaf-def6-437a-8c60-7158129ec041
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247641852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.3247641852
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.709053631
Short name T394
Test name
Test status
Simulation time 89897802 ps
CPU time 1.4 seconds
Started Aug 18 05:40:47 PM PDT 24
Finished Aug 18 05:40:49 PM PDT 24
Peak memory 197088 kb
Host smart-e5a6fd46-8a3a-4f98-9ac3-b91120cf3e35
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709053631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.709053631
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.1196177935
Short name T268
Test name
Test status
Simulation time 696487604 ps
CPU time 1.48 seconds
Started Aug 18 05:41:00 PM PDT 24
Finished Aug 18 05:41:02 PM PDT 24
Peak memory 196468 kb
Host smart-8d3496e1-fb35-421d-b849-36814121e749
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196177935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.1196177935
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.1866458579
Short name T595
Test name
Test status
Simulation time 145689724 ps
CPU time 1.52 seconds
Started Aug 18 05:40:36 PM PDT 24
Finished Aug 18 05:40:37 PM PDT 24
Peak memory 195928 kb
Host smart-3590d34a-0f24-4743-a3d5-aa289dcd622f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866458579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
1866458579
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.3364289965
Short name T679
Test name
Test status
Simulation time 87364392 ps
CPU time 0.94 seconds
Started Aug 18 05:40:33 PM PDT 24
Finished Aug 18 05:40:34 PM PDT 24
Peak memory 196096 kb
Host smart-7d93ae95-a07c-48f4-851e-0575eb3021c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364289965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.3364289965
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.3369624640
Short name T277
Test name
Test status
Simulation time 126918852 ps
CPU time 1.21 seconds
Started Aug 18 05:40:59 PM PDT 24
Finished Aug 18 05:41:00 PM PDT 24
Peak memory 198196 kb
Host smart-b00500bb-44f9-4dd4-967a-6e528757f8a9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369624640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.3369624640
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.190203607
Short name T274
Test name
Test status
Simulation time 32530206 ps
CPU time 1.55 seconds
Started Aug 18 05:40:46 PM PDT 24
Finished Aug 18 05:40:47 PM PDT 24
Peak memory 198192 kb
Host smart-bc6ceaf7-b686-45d2-b5dd-a0508b9ee746
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190203607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand
om_long_reg_writes_reg_reads.190203607
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.2725554662
Short name T548
Test name
Test status
Simulation time 41445124 ps
CPU time 0.9 seconds
Started Aug 18 05:40:46 PM PDT 24
Finished Aug 18 05:40:47 PM PDT 24
Peak memory 196120 kb
Host smart-cb518152-c3af-41c7-b540-260e6f35593b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725554662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.2725554662
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.3884888340
Short name T561
Test name
Test status
Simulation time 152518633 ps
CPU time 1.21 seconds
Started Aug 18 05:40:36 PM PDT 24
Finished Aug 18 05:40:37 PM PDT 24
Peak memory 195908 kb
Host smart-154e5222-fa88-427a-8de1-0076b33ced11
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884888340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.3884888340
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.4193383469
Short name T321
Test name
Test status
Simulation time 26562436458 ps
CPU time 170.94 seconds
Started Aug 18 05:40:39 PM PDT 24
Finished Aug 18 05:43:30 PM PDT 24
Peak memory 198348 kb
Host smart-8951d4aa-4d16-4fd3-80d2-d165f71caf9b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193383469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.4193383469
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.3854803418
Short name T900
Test name
Test status
Simulation time 207043206 ps
CPU time 1.24 seconds
Started Aug 18 05:31:04 PM PDT 24
Finished Aug 18 05:31:05 PM PDT 24
Peak memory 197116 kb
Host smart-ada29403-25fc-4a9a-9cce-bf4af40dbd00
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3854803418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.3854803418
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2464992611
Short name T882
Test name
Test status
Simulation time 45444325 ps
CPU time 0.85 seconds
Started Aug 18 05:31:20 PM PDT 24
Finished Aug 18 05:31:21 PM PDT 24
Peak memory 191132 kb
Host smart-1dc8e845-c1bb-4fdf-9f35-a24ca9f86cd8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464992611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2464992611
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.3476398188
Short name T933
Test name
Test status
Simulation time 143114101 ps
CPU time 1.02 seconds
Started Aug 18 05:31:34 PM PDT 24
Finished Aug 18 05:31:35 PM PDT 24
Peak memory 191336 kb
Host smart-eb6b9674-4b46-42ad-ac6f-a9083a5f0d19
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3476398188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.3476398188
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1889639605
Short name T843
Test name
Test status
Simulation time 183913108 ps
CPU time 1.13 seconds
Started Aug 18 05:31:24 PM PDT 24
Finished Aug 18 05:31:25 PM PDT 24
Peak memory 191360 kb
Host smart-f7177d80-406a-41d2-a681-55900e9871ee
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889639605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1889639605
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.3836398965
Short name T905
Test name
Test status
Simulation time 324718054 ps
CPU time 1.2 seconds
Started Aug 18 05:31:18 PM PDT 24
Finished Aug 18 05:31:19 PM PDT 24
Peak memory 191368 kb
Host smart-f5b74d26-9610-42ef-b15b-cbc88a8aafd2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3836398965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.3836398965
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2863021244
Short name T847
Test name
Test status
Simulation time 196568460 ps
CPU time 1.4 seconds
Started Aug 18 05:31:24 PM PDT 24
Finished Aug 18 05:31:26 PM PDT 24
Peak memory 191356 kb
Host smart-dd5a8bc7-2dd5-4727-9481-374840688ba6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863021244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2863021244
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.546688779
Short name T937
Test name
Test status
Simulation time 103248857 ps
CPU time 1.1 seconds
Started Aug 18 05:31:15 PM PDT 24
Finished Aug 18 05:31:17 PM PDT 24
Peak memory 191356 kb
Host smart-793f1298-0c65-4466-96ca-1572731d77f5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=546688779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.546688779
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3061377478
Short name T846
Test name
Test status
Simulation time 82278129 ps
CPU time 1.3 seconds
Started Aug 18 05:31:40 PM PDT 24
Finished Aug 18 05:31:41 PM PDT 24
Peak memory 191328 kb
Host smart-5146962a-2f7a-4837-b3f9-67eea09e3da7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061377478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3061377478
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.3850186281
Short name T874
Test name
Test status
Simulation time 179985570 ps
CPU time 1.06 seconds
Started Aug 18 05:31:20 PM PDT 24
Finished Aug 18 05:31:21 PM PDT 24
Peak memory 197320 kb
Host smart-97c79823-8bd3-46fb-bb8e-e83dfb5a2ca5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3850186281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.3850186281
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4222371705
Short name T866
Test name
Test status
Simulation time 263719747 ps
CPU time 1.19 seconds
Started Aug 18 05:31:21 PM PDT 24
Finished Aug 18 05:31:22 PM PDT 24
Peak memory 191328 kb
Host smart-34e22cdf-0457-46e8-b177-a00fbb87d117
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222371705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4222371705
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.1388119202
Short name T883
Test name
Test status
Simulation time 298299084 ps
CPU time 1.4 seconds
Started Aug 18 05:31:20 PM PDT 24
Finished Aug 18 05:31:21 PM PDT 24
Peak memory 191296 kb
Host smart-8d97aa9a-ff63-4196-b0be-5e647a3451c3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1388119202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.1388119202
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.637005772
Short name T898
Test name
Test status
Simulation time 81952399 ps
CPU time 1.23 seconds
Started Aug 18 05:31:18 PM PDT 24
Finished Aug 18 05:31:19 PM PDT 24
Peak memory 191352 kb
Host smart-a6656f1c-20ce-43ba-b07f-bf61eac2fd7b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637005772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.637005772
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.3205855816
Short name T917
Test name
Test status
Simulation time 162468328 ps
CPU time 0.96 seconds
Started Aug 18 05:31:17 PM PDT 24
Finished Aug 18 05:31:18 PM PDT 24
Peak memory 191296 kb
Host smart-c7dd09b9-98e5-4358-8337-5abe0f158404
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3205855816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.3205855816
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3719686577
Short name T909
Test name
Test status
Simulation time 40683042 ps
CPU time 1.15 seconds
Started Aug 18 05:31:11 PM PDT 24
Finished Aug 18 05:31:12 PM PDT 24
Peak memory 191340 kb
Host smart-2b689e7d-a28b-4141-b47b-f54850ffeb18
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719686577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3719686577
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.570697282
Short name T854
Test name
Test status
Simulation time 687368791 ps
CPU time 0.98 seconds
Started Aug 18 05:31:24 PM PDT 24
Finished Aug 18 05:31:25 PM PDT 24
Peak memory 195944 kb
Host smart-938fec95-c5b8-4761-b1ab-d436818d8f54
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=570697282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.570697282
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1135409577
Short name T932
Test name
Test status
Simulation time 97291334 ps
CPU time 1.36 seconds
Started Aug 18 05:31:24 PM PDT 24
Finished Aug 18 05:31:26 PM PDT 24
Peak memory 191324 kb
Host smart-805ca3ce-1270-4270-9143-45878e988a4d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135409577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1135409577
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.2380884901
Short name T916
Test name
Test status
Simulation time 114327500 ps
CPU time 0.88 seconds
Started Aug 18 05:31:23 PM PDT 24
Finished Aug 18 05:31:24 PM PDT 24
Peak memory 191124 kb
Host smart-dc866b70-af9b-4b7e-83bd-a70cbaead31c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2380884901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.2380884901
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1484505926
Short name T870
Test name
Test status
Simulation time 73748305 ps
CPU time 1.12 seconds
Started Aug 18 05:31:21 PM PDT 24
Finished Aug 18 05:31:22 PM PDT 24
Peak memory 191292 kb
Host smart-c9345c0b-5bb3-44e4-88f7-dcc60b17cc72
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484505926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1484505926
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.2043432877
Short name T858
Test name
Test status
Simulation time 72352815 ps
CPU time 1.17 seconds
Started Aug 18 05:31:34 PM PDT 24
Finished Aug 18 05:31:35 PM PDT 24
Peak memory 191236 kb
Host smart-68ea8efa-ad11-4abc-b398-6737852085f5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2043432877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.2043432877
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2095409808
Short name T869
Test name
Test status
Simulation time 33421374 ps
CPU time 0.84 seconds
Started Aug 18 05:31:30 PM PDT 24
Finished Aug 18 05:31:31 PM PDT 24
Peak memory 195660 kb
Host smart-b6b63f6e-a67e-4fe8-b33a-bee01ba67887
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095409808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2095409808
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.3472173702
Short name T856
Test name
Test status
Simulation time 131112559 ps
CPU time 1.33 seconds
Started Aug 18 05:31:25 PM PDT 24
Finished Aug 18 05:31:27 PM PDT 24
Peak memory 191572 kb
Host smart-00a920c7-988f-4fb9-afb8-be065439fcd2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3472173702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.3472173702
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3460685213
Short name T887
Test name
Test status
Simulation time 54590191 ps
CPU time 0.74 seconds
Started Aug 18 05:31:20 PM PDT 24
Finished Aug 18 05:31:20 PM PDT 24
Peak memory 191132 kb
Host smart-d64ca6a4-0337-4222-a5f8-e24085386b86
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460685213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3460685213
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.2542231844
Short name T850
Test name
Test status
Simulation time 30535605 ps
CPU time 0.9 seconds
Started Aug 18 05:31:22 PM PDT 24
Finished Aug 18 05:31:23 PM PDT 24
Peak memory 191124 kb
Host smart-977338aa-77a4-41c5-9c7f-e68a15982542
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2542231844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.2542231844
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.464402377
Short name T857
Test name
Test status
Simulation time 226508527 ps
CPU time 1.11 seconds
Started Aug 18 05:31:26 PM PDT 24
Finished Aug 18 05:31:28 PM PDT 24
Peak memory 196212 kb
Host smart-26fa6477-bd69-43eb-a843-764fd6a2442f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464402377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.464402377
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.613253036
Short name T889
Test name
Test status
Simulation time 91877031 ps
CPU time 0.87 seconds
Started Aug 18 05:31:28 PM PDT 24
Finished Aug 18 05:31:29 PM PDT 24
Peak memory 191056 kb
Host smart-3ae7ff17-8162-4df5-877e-39e16d7fd3ef
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=613253036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.613253036
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2906377347
Short name T861
Test name
Test status
Simulation time 579645924 ps
CPU time 1.23 seconds
Started Aug 18 05:31:14 PM PDT 24
Finished Aug 18 05:31:15 PM PDT 24
Peak memory 191332 kb
Host smart-bb78433c-35af-40e8-8985-89567392801d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906377347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2906377347
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.1643326503
Short name T875
Test name
Test status
Simulation time 276094346 ps
CPU time 1.31 seconds
Started Aug 18 05:31:24 PM PDT 24
Finished Aug 18 05:31:31 PM PDT 24
Peak memory 191360 kb
Host smart-a916e75e-93c8-4a45-8fe1-de4e77fe2029
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1643326503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.1643326503
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3557992165
Short name T902
Test name
Test status
Simulation time 32319207 ps
CPU time 0.78 seconds
Started Aug 18 05:31:20 PM PDT 24
Finished Aug 18 05:31:21 PM PDT 24
Peak memory 195764 kb
Host smart-a80ec0ef-9680-4d6d-a1ab-446f40c45654
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557992165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3557992165
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.533992475
Short name T862
Test name
Test status
Simulation time 221925015 ps
CPU time 1.45 seconds
Started Aug 18 05:31:29 PM PDT 24
Finished Aug 18 05:31:30 PM PDT 24
Peak memory 197708 kb
Host smart-2307df7a-f1a6-43b4-94c8-30f545d07450
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=533992475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.533992475
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.71813809
Short name T910
Test name
Test status
Simulation time 73114862 ps
CPU time 1.36 seconds
Started Aug 18 05:31:25 PM PDT 24
Finished Aug 18 05:31:26 PM PDT 24
Peak memory 191312 kb
Host smart-c3836975-4e71-4484-954b-36fdd589c75b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71813809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.71813809
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.3410321202
Short name T936
Test name
Test status
Simulation time 137233746 ps
CPU time 1.06 seconds
Started Aug 18 05:31:24 PM PDT 24
Finished Aug 18 05:31:25 PM PDT 24
Peak memory 191224 kb
Host smart-ae85be17-e48c-4893-9e1a-6c5f8d403125
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3410321202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.3410321202
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2029363675
Short name T877
Test name
Test status
Simulation time 85662477 ps
CPU time 1.14 seconds
Started Aug 18 05:31:27 PM PDT 24
Finished Aug 18 05:31:29 PM PDT 24
Peak memory 191336 kb
Host smart-b502a515-f832-4724-88c6-f7c1aa407d0d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029363675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2029363675
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.1083873299
Short name T855
Test name
Test status
Simulation time 38206976 ps
CPU time 1.1 seconds
Started Aug 18 05:31:16 PM PDT 24
Finished Aug 18 05:31:17 PM PDT 24
Peak memory 191336 kb
Host smart-de1ae0b1-bb60-45ad-b92d-56cf50d68601
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1083873299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.1083873299
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4209886962
Short name T908
Test name
Test status
Simulation time 267984843 ps
CPU time 1.25 seconds
Started Aug 18 05:31:25 PM PDT 24
Finished Aug 18 05:31:27 PM PDT 24
Peak memory 197172 kb
Host smart-4945b48a-65ae-4424-8752-c28d75e848d3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209886962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4209886962
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.2215896147
Short name T904
Test name
Test status
Simulation time 304744605 ps
CPU time 1.03 seconds
Started Aug 18 05:31:27 PM PDT 24
Finished Aug 18 05:31:28 PM PDT 24
Peak memory 191352 kb
Host smart-35d22880-bf25-4abf-aa4b-ea34f467b0a2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2215896147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.2215896147
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.802775750
Short name T894
Test name
Test status
Simulation time 39445910 ps
CPU time 0.93 seconds
Started Aug 18 05:31:19 PM PDT 24
Finished Aug 18 05:31:20 PM PDT 24
Peak memory 190288 kb
Host smart-9af9b512-dfbd-49c5-9b7b-a63d987762af
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802775750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.802775750
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.4249219206
Short name T903
Test name
Test status
Simulation time 83299532 ps
CPU time 1.26 seconds
Started Aug 18 05:31:29 PM PDT 24
Finished Aug 18 05:31:30 PM PDT 24
Peak memory 190516 kb
Host smart-83780e9b-2eab-4a04-8f76-6a37929f281a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4249219206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.4249219206
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2948144702
Short name T940
Test name
Test status
Simulation time 46595619 ps
CPU time 1.32 seconds
Started Aug 18 05:31:22 PM PDT 24
Finished Aug 18 05:31:23 PM PDT 24
Peak memory 197660 kb
Host smart-ae266d26-0eab-4bb5-8531-d9f190672ada
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948144702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2948144702
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.3272044341
Short name T868
Test name
Test status
Simulation time 40339678 ps
CPU time 1.12 seconds
Started Aug 18 05:31:22 PM PDT 24
Finished Aug 18 05:31:23 PM PDT 24
Peak memory 191308 kb
Host smart-8dcc22a1-1eea-4954-bded-39936a877196
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3272044341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.3272044341
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1020246243
Short name T842
Test name
Test status
Simulation time 46745167 ps
CPU time 0.9 seconds
Started Aug 18 05:31:20 PM PDT 24
Finished Aug 18 05:31:21 PM PDT 24
Peak memory 196984 kb
Host smart-5b444fa0-b403-4e40-bbca-c64cc2af03f0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020246243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1020246243
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.1914054880
Short name T849
Test name
Test status
Simulation time 57201583 ps
CPU time 1 seconds
Started Aug 18 05:31:17 PM PDT 24
Finished Aug 18 05:31:19 PM PDT 24
Peak memory 191320 kb
Host smart-38b3ddd2-b770-4c45-8614-078dff9d0b56
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1914054880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.1914054880
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3420924981
Short name T884
Test name
Test status
Simulation time 98700274 ps
CPU time 1.34 seconds
Started Aug 18 05:31:23 PM PDT 24
Finished Aug 18 05:31:24 PM PDT 24
Peak memory 197700 kb
Host smart-2faf963f-2530-498e-868d-b859f4f88130
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420924981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3420924981
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.1546636503
Short name T930
Test name
Test status
Simulation time 160618663 ps
CPU time 1.22 seconds
Started Aug 18 05:31:21 PM PDT 24
Finished Aug 18 05:31:22 PM PDT 24
Peak memory 191256 kb
Host smart-77739a83-8914-4ccf-8124-c364cc2e7355
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1546636503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.1546636503
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2599508986
Short name T893
Test name
Test status
Simulation time 152456028 ps
CPU time 1.08 seconds
Started Aug 18 05:31:25 PM PDT 24
Finished Aug 18 05:31:27 PM PDT 24
Peak memory 191260 kb
Host smart-a443e0f8-aa9d-4432-9faa-28a317332dd8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599508986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2599508986
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.1063027672
Short name T851
Test name
Test status
Simulation time 49988155 ps
CPU time 1.02 seconds
Started Aug 18 05:31:40 PM PDT 24
Finished Aug 18 05:31:41 PM PDT 24
Peak memory 190516 kb
Host smart-ace5b844-b189-41cc-932d-14b814216579
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1063027672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.1063027672
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1925254776
Short name T901
Test name
Test status
Simulation time 42312791 ps
CPU time 1.17 seconds
Started Aug 18 05:31:24 PM PDT 24
Finished Aug 18 05:31:25 PM PDT 24
Peak memory 191296 kb
Host smart-e174fb5e-f920-40ac-942c-3ddade5b725f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925254776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1925254776
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.104964367
Short name T872
Test name
Test status
Simulation time 243858773 ps
CPU time 1.18 seconds
Started Aug 18 05:31:17 PM PDT 24
Finished Aug 18 05:31:23 PM PDT 24
Peak memory 191268 kb
Host smart-0a9bc34a-e920-487f-bb39-e208e4a88dfa
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=104964367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.104964367
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2919935994
Short name T924
Test name
Test status
Simulation time 160230483 ps
CPU time 1.21 seconds
Started Aug 18 05:31:27 PM PDT 24
Finished Aug 18 05:31:29 PM PDT 24
Peak memory 191356 kb
Host smart-10077e82-9999-40f3-879b-e2ed5cd802ef
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919935994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2919935994
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.3423434498
Short name T918
Test name
Test status
Simulation time 55877804 ps
CPU time 1.16 seconds
Started Aug 18 05:31:26 PM PDT 24
Finished Aug 18 05:31:27 PM PDT 24
Peak memory 191240 kb
Host smart-f9e26cb1-3241-4140-a5de-1eab03d3584f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3423434498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.3423434498
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4053311216
Short name T906
Test name
Test status
Simulation time 176852833 ps
CPU time 0.83 seconds
Started Aug 18 05:31:40 PM PDT 24
Finished Aug 18 05:31:41 PM PDT 24
Peak memory 191124 kb
Host smart-9ea591b4-0739-4612-bdd9-d9e943bfaf28
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053311216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4053311216
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.2116093770
Short name T885
Test name
Test status
Simulation time 730890523 ps
CPU time 1.11 seconds
Started Aug 18 05:31:31 PM PDT 24
Finished Aug 18 05:31:32 PM PDT 24
Peak memory 197184 kb
Host smart-9b62058a-0b02-46ab-9161-1cdf3d556f38
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2116093770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.2116093770
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.418574843
Short name T921
Test name
Test status
Simulation time 322226906 ps
CPU time 1.46 seconds
Started Aug 18 05:31:19 PM PDT 24
Finished Aug 18 05:31:21 PM PDT 24
Peak memory 197656 kb
Host smart-c7a23492-4ee7-4d6f-9211-b9205db9f291
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418574843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.418574843
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.4257032645
Short name T886
Test name
Test status
Simulation time 69306095 ps
CPU time 1.03 seconds
Started Aug 18 05:31:23 PM PDT 24
Finished Aug 18 05:31:24 PM PDT 24
Peak memory 191352 kb
Host smart-3d88cca5-7c7f-4ad8-a599-9c41fc3a70ba
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4257032645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.4257032645
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.395761731
Short name T907
Test name
Test status
Simulation time 490088713 ps
CPU time 1.14 seconds
Started Aug 18 05:31:29 PM PDT 24
Finished Aug 18 05:31:30 PM PDT 24
Peak memory 191244 kb
Host smart-48540fab-902f-4d0b-87e7-b5023cd1816e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395761731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.395761731
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.990606033
Short name T860
Test name
Test status
Simulation time 31489257 ps
CPU time 0.99 seconds
Started Aug 18 05:31:44 PM PDT 24
Finished Aug 18 05:31:45 PM PDT 24
Peak memory 191252 kb
Host smart-135c165a-e999-4477-8721-e19c6646a73b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=990606033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.990606033
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.718346887
Short name T928
Test name
Test status
Simulation time 29663583 ps
CPU time 0.99 seconds
Started Aug 18 05:31:40 PM PDT 24
Finished Aug 18 05:31:41 PM PDT 24
Peak memory 197704 kb
Host smart-c22105d4-f774-477a-8321-d160bffd1847
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718346887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.718346887
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.678517198
Short name T920
Test name
Test status
Simulation time 165213641 ps
CPU time 0.73 seconds
Started Aug 18 05:31:32 PM PDT 24
Finished Aug 18 05:31:33 PM PDT 24
Peak memory 191164 kb
Host smart-e32497ef-4bd2-4fed-8a35-6254ef3bc315
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=678517198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.678517198
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3393670357
Short name T845
Test name
Test status
Simulation time 51296116 ps
CPU time 0.98 seconds
Started Aug 18 05:31:46 PM PDT 24
Finished Aug 18 05:31:47 PM PDT 24
Peak memory 191336 kb
Host smart-be814c66-f275-42e8-bfc5-b359e85eeedb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393670357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3393670357
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.1628470548
Short name T927
Test name
Test status
Simulation time 66643637 ps
CPU time 1.12 seconds
Started Aug 18 05:31:34 PM PDT 24
Finished Aug 18 05:31:35 PM PDT 24
Peak memory 191324 kb
Host smart-cc83b134-4252-4afd-b83b-916351bfc30c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1628470548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.1628470548
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1521835958
Short name T915
Test name
Test status
Simulation time 89793501 ps
CPU time 1.4 seconds
Started Aug 18 05:31:50 PM PDT 24
Finished Aug 18 05:31:51 PM PDT 24
Peak memory 191324 kb
Host smart-c8326f55-f8e9-40a3-b6a7-17cd5f3872b8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521835958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1521835958
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.23101887
Short name T878
Test name
Test status
Simulation time 180149793 ps
CPU time 1.4 seconds
Started Aug 18 05:31:32 PM PDT 24
Finished Aug 18 05:31:34 PM PDT 24
Peak memory 191328 kb
Host smart-e1fbb861-7d1a-4010-8336-64e9f45d1d2e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=23101887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.23101887
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.911398096
Short name T876
Test name
Test status
Simulation time 72871928 ps
CPU time 0.76 seconds
Started Aug 18 05:31:34 PM PDT 24
Finished Aug 18 05:31:35 PM PDT 24
Peak memory 191076 kb
Host smart-675ffdea-ed10-4a7a-84da-3b2c78572775
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911398096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.911398096
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.3400299590
Short name T892
Test name
Test status
Simulation time 133644368 ps
CPU time 0.95 seconds
Started Aug 18 05:31:48 PM PDT 24
Finished Aug 18 05:31:49 PM PDT 24
Peak memory 195836 kb
Host smart-0def1c59-bbe5-4968-ab9f-5a25bc87451c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3400299590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.3400299590
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4071699040
Short name T926
Test name
Test status
Simulation time 83889812 ps
CPU time 1.29 seconds
Started Aug 18 05:31:45 PM PDT 24
Finished Aug 18 05:31:46 PM PDT 24
Peak memory 191272 kb
Host smart-917342f4-41c7-43a2-a2d3-5298c1ffcc99
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071699040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4071699040
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.2641616505
Short name T919
Test name
Test status
Simulation time 106340588 ps
CPU time 1.03 seconds
Started Aug 18 05:31:54 PM PDT 24
Finished Aug 18 05:31:55 PM PDT 24
Peak memory 191304 kb
Host smart-3cab305a-74f2-4efa-8638-56f2b5d7980f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2641616505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.2641616505
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.627377959
Short name T879
Test name
Test status
Simulation time 67165304 ps
CPU time 1.15 seconds
Started Aug 18 05:31:40 PM PDT 24
Finished Aug 18 05:31:41 PM PDT 24
Peak memory 197232 kb
Host smart-7761da1d-374f-4bba-a6b2-b96a9480105d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627377959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.627377959
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.1875269369
Short name T865
Test name
Test status
Simulation time 251142550 ps
CPU time 1.03 seconds
Started Aug 18 05:31:25 PM PDT 24
Finished Aug 18 05:31:26 PM PDT 24
Peak memory 191364 kb
Host smart-3f70cc13-7d85-45f2-93a0-be2cf456e848
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1875269369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.1875269369
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1452876324
Short name T853
Test name
Test status
Simulation time 88750782 ps
CPU time 0.72 seconds
Started Aug 18 05:31:41 PM PDT 24
Finished Aug 18 05:31:42 PM PDT 24
Peak memory 191108 kb
Host smart-ecdc5e24-d676-4eb6-a6c3-f50eccc04900
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452876324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1452876324
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.3094220552
Short name T911
Test name
Test status
Simulation time 794665354 ps
CPU time 1.34 seconds
Started Aug 18 05:31:24 PM PDT 24
Finished Aug 18 05:31:26 PM PDT 24
Peak memory 197680 kb
Host smart-7ee7b4ca-b3df-4649-8603-bdc919311f7d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3094220552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.3094220552
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2191245887
Short name T844
Test name
Test status
Simulation time 54480474 ps
CPU time 1.1 seconds
Started Aug 18 05:31:33 PM PDT 24
Finished Aug 18 05:31:35 PM PDT 24
Peak memory 191280 kb
Host smart-18060531-3478-4ad9-b7a6-6a23ef959ac3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191245887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2191245887
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.2603899494
Short name T912
Test name
Test status
Simulation time 54683565 ps
CPU time 0.8 seconds
Started Aug 18 05:31:39 PM PDT 24
Finished Aug 18 05:31:40 PM PDT 24
Peak memory 191364 kb
Host smart-2821b2cc-a745-4a98-a977-4d0746be67d4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2603899494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.2603899494
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.862335561
Short name T923
Test name
Test status
Simulation time 131289803 ps
CPU time 1.27 seconds
Started Aug 18 05:31:41 PM PDT 24
Finished Aug 18 05:31:43 PM PDT 24
Peak memory 196328 kb
Host smart-4149b03e-4d4c-4683-b044-b8532936ec3c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862335561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.862335561
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.4177680859
Short name T935
Test name
Test status
Simulation time 236494012 ps
CPU time 0.86 seconds
Started Aug 18 05:31:23 PM PDT 24
Finished Aug 18 05:31:24 PM PDT 24
Peak memory 191068 kb
Host smart-1a9ad3e8-9058-4435-ae29-5991e6a49d55
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4177680859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.4177680859
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2443590209
Short name T925
Test name
Test status
Simulation time 285186707 ps
CPU time 0.78 seconds
Started Aug 18 05:31:37 PM PDT 24
Finished Aug 18 05:31:38 PM PDT 24
Peak memory 191104 kb
Host smart-2d12eb4a-57da-499e-bf01-d3ae998a25bb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443590209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2443590209
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.3480801649
Short name T899
Test name
Test status
Simulation time 95186561 ps
CPU time 1 seconds
Started Aug 18 05:31:50 PM PDT 24
Finished Aug 18 05:31:52 PM PDT 24
Peak memory 191340 kb
Host smart-e94f512b-26e2-4cf7-ac62-fec123dfbe87
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3480801649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.3480801649
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2405973069
Short name T891
Test name
Test status
Simulation time 202526379 ps
CPU time 0.99 seconds
Started Aug 18 05:31:38 PM PDT 24
Finished Aug 18 05:31:39 PM PDT 24
Peak memory 191296 kb
Host smart-7f9134c6-9dec-4417-acfd-f105c29978b8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405973069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2405973069
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.2467451143
Short name T880
Test name
Test status
Simulation time 34518146 ps
CPU time 0.87 seconds
Started Aug 18 05:31:34 PM PDT 24
Finished Aug 18 05:31:35 PM PDT 24
Peak memory 195656 kb
Host smart-b5294ce8-b093-4477-9359-72c4f6f43000
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2467451143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.2467451143
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3925725708
Short name T864
Test name
Test status
Simulation time 215114025 ps
CPU time 1.37 seconds
Started Aug 18 05:31:38 PM PDT 24
Finished Aug 18 05:31:40 PM PDT 24
Peak memory 191356 kb
Host smart-b43f5b41-7aa4-4d57-98f4-7e650d60ac9e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925725708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3925725708
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.963518685
Short name T914
Test name
Test status
Simulation time 363986231 ps
CPU time 1.13 seconds
Started Aug 18 05:31:41 PM PDT 24
Finished Aug 18 05:31:42 PM PDT 24
Peak memory 191380 kb
Host smart-f9dc9fae-7d55-4857-bdae-67a52c01cbf2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=963518685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.963518685
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1814591977
Short name T867
Test name
Test status
Simulation time 172186278 ps
CPU time 1.34 seconds
Started Aug 18 05:31:40 PM PDT 24
Finished Aug 18 05:31:42 PM PDT 24
Peak memory 197656 kb
Host smart-751d19f5-5b99-4f7b-8add-621b19bd9796
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814591977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1814591977
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.2462183354
Short name T934
Test name
Test status
Simulation time 417118787 ps
CPU time 0.9 seconds
Started Aug 18 05:31:29 PM PDT 24
Finished Aug 18 05:31:29 PM PDT 24
Peak memory 191352 kb
Host smart-31fc396c-a14d-463c-8ad6-1ab2cd8f9f70
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2462183354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.2462183354
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.870825723
Short name T859
Test name
Test status
Simulation time 315454517 ps
CPU time 1.49 seconds
Started Aug 18 05:31:41 PM PDT 24
Finished Aug 18 05:31:43 PM PDT 24
Peak memory 191296 kb
Host smart-19cf4b20-9187-44c6-ab38-f8b27505b87e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870825723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.870825723
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.1053533652
Short name T852
Test name
Test status
Simulation time 35239238 ps
CPU time 0.99 seconds
Started Aug 18 05:31:33 PM PDT 24
Finished Aug 18 05:31:34 PM PDT 24
Peak memory 196204 kb
Host smart-79c4514a-90e6-41a4-8ab7-673f4421b730
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1053533652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.1053533652
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1064906609
Short name T863
Test name
Test status
Simulation time 273978806 ps
CPU time 1.21 seconds
Started Aug 18 05:31:41 PM PDT 24
Finished Aug 18 05:31:42 PM PDT 24
Peak memory 191300 kb
Host smart-4c58d5c6-f106-44f6-a670-14c46f46349c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064906609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1064906609
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.1054797959
Short name T922
Test name
Test status
Simulation time 80430791 ps
CPU time 1.24 seconds
Started Aug 18 05:31:40 PM PDT 24
Finished Aug 18 05:31:41 PM PDT 24
Peak memory 191288 kb
Host smart-4862f81c-5554-454e-88cb-eb514489d2ba
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1054797959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.1054797959
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.555412168
Short name T941
Test name
Test status
Simulation time 270603640 ps
CPU time 1.15 seconds
Started Aug 18 05:31:35 PM PDT 24
Finished Aug 18 05:31:37 PM PDT 24
Peak memory 191296 kb
Host smart-8688a348-931a-4a7f-8a9e-5ad1bde7ef5a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555412168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.555412168
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.3690904529
Short name T896
Test name
Test status
Simulation time 184972069 ps
CPU time 1.37 seconds
Started Aug 18 05:31:46 PM PDT 24
Finished Aug 18 05:31:47 PM PDT 24
Peak memory 191360 kb
Host smart-7276f728-4afe-48e6-b957-ba254fbe48d8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3690904529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.3690904529
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.881990929
Short name T897
Test name
Test status
Simulation time 122405180 ps
CPU time 1.03 seconds
Started Aug 18 05:31:37 PM PDT 24
Finished Aug 18 05:31:38 PM PDT 24
Peak memory 191328 kb
Host smart-4a5dd775-5516-4610-abe1-42db77c13962
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881990929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.881990929
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.3945266871
Short name T871
Test name
Test status
Simulation time 73835420 ps
CPU time 1.25 seconds
Started Aug 18 05:31:43 PM PDT 24
Finished Aug 18 05:31:45 PM PDT 24
Peak memory 191284 kb
Host smart-249c14fd-6839-49bb-8550-7314bf13865f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3945266871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.3945266871
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3351993878
Short name T931
Test name
Test status
Simulation time 68296148 ps
CPU time 1.17 seconds
Started Aug 18 05:31:40 PM PDT 24
Finished Aug 18 05:31:42 PM PDT 24
Peak memory 191256 kb
Host smart-e93832a9-ad04-470e-b1bb-03787cededd3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351993878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3351993878
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.2371354988
Short name T888
Test name
Test status
Simulation time 105824475 ps
CPU time 1.18 seconds
Started Aug 18 05:31:27 PM PDT 24
Finished Aug 18 05:31:29 PM PDT 24
Peak memory 195964 kb
Host smart-b2ec5a3a-a6dc-4e31-a8ec-4b6a2fd1ed7a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2371354988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.2371354988
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2973851834
Short name T913
Test name
Test status
Simulation time 30815896 ps
CPU time 0.79 seconds
Started Aug 18 05:31:23 PM PDT 24
Finished Aug 18 05:31:24 PM PDT 24
Peak memory 195640 kb
Host smart-b660053d-f912-4215-b7e5-13d987329f9b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973851834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2973851834
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.3638957917
Short name T873
Test name
Test status
Simulation time 62478835 ps
CPU time 1.1 seconds
Started Aug 18 05:31:28 PM PDT 24
Finished Aug 18 05:31:29 PM PDT 24
Peak memory 191316 kb
Host smart-e88633c3-e7a7-4347-9c54-7467159f9b12
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3638957917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.3638957917
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.119214961
Short name T938
Test name
Test status
Simulation time 1346261879 ps
CPU time 1.23 seconds
Started Aug 18 05:31:29 PM PDT 24
Finished Aug 18 05:31:31 PM PDT 24
Peak memory 197520 kb
Host smart-34eed889-f020-464c-9a47-17237f20506b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119214961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.119214961
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.3938918211
Short name T890
Test name
Test status
Simulation time 272640415 ps
CPU time 1.32 seconds
Started Aug 18 05:31:22 PM PDT 24
Finished Aug 18 05:31:23 PM PDT 24
Peak memory 191260 kb
Host smart-bf7575b4-9bc4-4a43-8366-842fc0d7c96b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3938918211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.3938918211
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2079605530
Short name T848
Test name
Test status
Simulation time 60776593 ps
CPU time 1.1 seconds
Started Aug 18 05:31:16 PM PDT 24
Finished Aug 18 05:31:17 PM PDT 24
Peak memory 196240 kb
Host smart-289f35d1-0434-48bd-9d50-3cc15affee9d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079605530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2079605530
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.2620451945
Short name T895
Test name
Test status
Simulation time 98452179 ps
CPU time 1.37 seconds
Started Aug 18 05:31:19 PM PDT 24
Finished Aug 18 05:31:21 PM PDT 24
Peak memory 191308 kb
Host smart-0b3ba16b-c3df-4811-836a-a1e764473099
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2620451945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.2620451945
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1928365735
Short name T929
Test name
Test status
Simulation time 91290257 ps
CPU time 1.43 seconds
Started Aug 18 05:31:20 PM PDT 24
Finished Aug 18 05:31:22 PM PDT 24
Peak memory 191340 kb
Host smart-5a81c99f-1455-448c-af62-ba804ca005a3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928365735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1928365735
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.3980998521
Short name T881
Test name
Test status
Simulation time 58011438 ps
CPU time 1.11 seconds
Started Aug 18 05:31:34 PM PDT 24
Finished Aug 18 05:31:36 PM PDT 24
Peak memory 190488 kb
Host smart-52dc2c70-8408-4446-8faa-8bea70a266de
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3980998521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.3980998521
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3751355597
Short name T939
Test name
Test status
Simulation time 354157781 ps
CPU time 1.06 seconds
Started Aug 18 05:31:19 PM PDT 24
Finished Aug 18 05:31:20 PM PDT 24
Peak memory 191332 kb
Host smart-d46bb0b0-58f4-4f0d-be45-1cdda5c15e00
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751355597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3751355597
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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