Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	1777654	1			T24	1		T25	38		T1	798
all_pins[1]	1777654	1			T24	1		T25	38		T1	798
all_pins[2]	1777654	1			T24	1		T25	38		T1	798
all_pins[3]	1777654	1			T24	1		T25	38		T1	798
all_pins[4]	1777654	1			T24	1		T25	38		T1	798
all_pins[5]	1777654	1			T24	1		T25	38		T1	798
all_pins[6]	1777654	1			T24	1		T25	38		T1	798
all_pins[7]	1777654	1			T24	1		T25	38		T1	798
all_pins[8]	1777654	1			T24	1		T25	38		T1	798
all_pins[9]	1777654	1			T24	1		T25	38		T1	798
all_pins[10]	1777654	1			T24	1		T25	38		T1	798
all_pins[11]	1777654	1			T24	1		T25	38		T1	798
all_pins[12]	1777654	1			T24	1		T25	38		T1	798
all_pins[13]	1777654	1			T24	1		T25	38		T1	798
all_pins[14]	1777654	1			T24	1		T25	38		T1	798
all_pins[15]	1777654	1			T24	1		T25	38		T1	798
all_pins[16]	1777654	1			T24	1		T25	38		T1	798
all_pins[17]	1777654	1			T24	1		T25	38		T1	798
all_pins[18]	1777654	1			T24	1		T25	38		T1	798
all_pins[19]	1777654	1			T24	1		T25	38		T1	798
all_pins[20]	1777654	1			T24	1		T25	38		T1	798
all_pins[21]	1777654	1			T24	1		T25	38		T1	798
all_pins[22]	1777654	1			T24	1		T25	38		T1	798
all_pins[23]	1777654	1			T24	1		T25	38		T1	798
all_pins[24]	1777654	1			T24	1		T25	38		T1	798
all_pins[25]	1777654	1			T24	1		T25	38		T1	798
all_pins[26]	1777654	1			T24	1		T25	38		T1	798
all_pins[27]	1777654	1			T24	1		T25	38		T1	798
all_pins[28]	1777654	1			T24	1		T25	38		T1	798
all_pins[29]	1777654	1			T24	1		T25	38		T1	798
all_pins[30]	1777654	1			T24	1		T25	38		T1	798
all_pins[31]	1777654	1			T24	1		T25	38		T1	798

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	35375440	1			T24	32		T25	650		T1	15951
values[0x1]	21509488	1			T25	566		T1	9585		T11	21413
transitions[0x0=>0x1]	12883736	1			T25	288		T1	5627		T11	12947
transitions[0x1=>0x0]	12883576	1			T25	288		T1	5627		T11	12947

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	1107344	1			T24	1		T25	20		T1	478
all_pins[0]	values[0x1]	670310	1			T25	18		T1	320		T11	588
all_pins[0]	transitions[0x0=>0x1]	415430	1			T25	7		T1	203		T11	368
all_pins[0]	transitions[0x1=>0x0]	417252	1			T25	11		T1	133		T11	499
all_pins[1]	values[0x0]	1106783	1			T24	1		T25	17		T1	456
all_pins[1]	values[0x1]	670871	1			T25	21		T1	342		T11	683
all_pins[1]	transitions[0x0=>0x1]	402523	1			T25	10		T1	215		T11	404
all_pins[1]	transitions[0x1=>0x0]	401962	1			T25	7		T1	193		T11	309
all_pins[2]	values[0x0]	1106586	1			T24	1		T25	20		T1	548
all_pins[2]	values[0x1]	671068	1			T25	18		T1	250		T11	621
all_pins[2]	transitions[0x0=>0x1]	401323	1			T25	7		T1	144		T11	393
all_pins[2]	transitions[0x1=>0x0]	401126	1			T25	10		T1	236		T11	455
all_pins[3]	values[0x0]	1102835	1			T24	1		T25	25		T1	492
all_pins[3]	values[0x1]	674819	1			T25	13		T1	306		T11	709
all_pins[3]	transitions[0x0=>0x1]	403836	1			T25	8		T1	206		T11	464
all_pins[3]	transitions[0x1=>0x0]	400085	1			T25	13		T1	150		T11	376
all_pins[4]	values[0x0]	1104967	1			T24	1		T25	29		T1	496
all_pins[4]	values[0x1]	672687	1			T25	9		T1	302		T11	633
all_pins[4]	transitions[0x0=>0x1]	402309	1			T25	5		T1	179		T11	377
all_pins[4]	transitions[0x1=>0x0]	404441	1			T25	9		T1	183		T11	453
all_pins[5]	values[0x0]	1103693	1			T24	1		T25	21		T1	470
all_pins[5]	values[0x1]	673961	1			T25	17		T1	328		T11	667
all_pins[5]	transitions[0x0=>0x1]	402841	1			T25	15		T1	176		T11	435
all_pins[5]	transitions[0x1=>0x0]	401567	1			T25	7		T1	150		T11	401
all_pins[6]	values[0x0]	1105335	1			T24	1		T25	25		T1	494
all_pins[6]	values[0x1]	672319	1			T25	13		T1	304		T11	759
all_pins[6]	transitions[0x0=>0x1]	401118	1			T25	7		T1	174		T11	516
all_pins[6]	transitions[0x1=>0x0]	402760	1			T25	11		T1	198		T11	424
all_pins[7]	values[0x0]	1103366	1			T24	1		T25	19		T1	471
all_pins[7]	values[0x1]	674288	1			T25	19		T1	327		T11	676
all_pins[7]	transitions[0x0=>0x1]	402964	1			T25	12		T1	184		T11	346
all_pins[7]	transitions[0x1=>0x0]	400995	1			T25	6		T1	161		T11	429
all_pins[8]	values[0x0]	1104332	1			T24	1		T25	17		T1	503
all_pins[8]	values[0x1]	673322	1			T25	21		T1	295		T11	576
all_pins[8]	transitions[0x0=>0x1]	401777	1			T25	9		T1	151		T11	323
all_pins[8]	transitions[0x1=>0x0]	402743	1			T25	7		T1	183		T11	423
all_pins[9]	values[0x0]	1106281	1			T24	1		T25	29		T1	482
all_pins[9]	values[0x1]	671373	1			T25	9		T1	316		T11	686
all_pins[9]	transitions[0x0=>0x1]	400859	1			T25	3		T1	169		T11	461
all_pins[9]	transitions[0x1=>0x0]	402808	1			T25	15		T1	148		T11	351
all_pins[10]	values[0x0]	1108300	1			T24	1		T25	14		T1	489
all_pins[10]	values[0x1]	669354	1			T25	24		T1	309		T11	758
all_pins[10]	transitions[0x0=>0x1]	401793	1			T25	17		T1	162		T11	465
all_pins[10]	transitions[0x1=>0x0]	403812	1			T25	2		T1	169		T11	393
all_pins[11]	values[0x0]	1106210	1			T24	1		T25	14		T1	524
all_pins[11]	values[0x1]	671444	1			T25	24		T1	274		T11	658
all_pins[11]	transitions[0x0=>0x1]	402690	1			T25	6		T1	171		T11	343
all_pins[11]	transitions[0x1=>0x0]	400600	1			T25	6		T1	206		T11	443
all_pins[12]	values[0x0]	1108181	1			T24	1		T25	23		T1	499
all_pins[12]	values[0x1]	669473	1			T25	15		T1	299		T11	613
all_pins[12]	transitions[0x0=>0x1]	402225	1			T25	4		T1	188		T11	361
all_pins[12]	transitions[0x1=>0x0]	404196	1			T25	13		T1	163		T11	406
all_pins[13]	values[0x0]	1106439	1			T24	1		T25	18		T1	529
all_pins[13]	values[0x1]	671215	1			T25	20		T1	269		T11	691
all_pins[13]	transitions[0x0=>0x1]	402486	1			T25	11		T1	164		T11	441
all_pins[13]	transitions[0x1=>0x0]	400744	1			T25	6		T1	194		T11	363
all_pins[14]	values[0x0]	1103922	1			T24	1		T25	14		T1	488
all_pins[14]	values[0x1]	673732	1			T25	24		T1	310		T11	670
all_pins[14]	transitions[0x0=>0x1]	404164	1			T25	14		T1	187		T11	401
all_pins[14]	transitions[0x1=>0x0]	401647	1			T25	10		T1	146		T11	422
all_pins[15]	values[0x0]	1104153	1			T24	1		T25	13		T1	527
all_pins[15]	values[0x1]	673501	1			T25	25		T1	271		T11	667
all_pins[15]	transitions[0x0=>0x1]	402297	1			T25	12		T1	176		T11	381
all_pins[15]	transitions[0x1=>0x0]	402528	1			T25	11		T1	215		T11	384
all_pins[16]	values[0x0]	1104360	1			T24	1		T25	23		T1	513
all_pins[16]	values[0x1]	673294	1			T25	15		T1	285		T11	724
all_pins[16]	transitions[0x0=>0x1]	403099	1			T25	2		T1	165		T11	407
all_pins[16]	transitions[0x1=>0x0]	403306	1			T25	12		T1	151		T11	350
all_pins[17]	values[0x0]	1105841	1			T24	1		T25	24		T1	471
all_pins[17]	values[0x1]	671813	1			T25	14		T1	327		T11	699
all_pins[17]	transitions[0x0=>0x1]	403177	1			T25	10		T1	182		T11	416
all_pins[17]	transitions[0x1=>0x0]	404658	1			T25	11		T1	140		T11	441
all_pins[18]	values[0x0]	1105289	1			T24	1		T25	26		T1	495
all_pins[18]	values[0x1]	672365	1			T25	12		T1	303		T11	710
all_pins[18]	transitions[0x0=>0x1]	401688	1			T25	9		T1	160		T11	426
all_pins[18]	transitions[0x1=>0x0]	401136	1			T25	11		T1	184		T11	415
all_pins[19]	values[0x0]	1108647	1			T24	1		T25	21		T1	377
all_pins[19]	values[0x1]	669007	1			T25	17		T1	421		T11	574
all_pins[19]	transitions[0x0=>0x1]	398481	1			T25	12		T1	260		T11	351
all_pins[19]	transitions[0x1=>0x0]	401839	1			T25	7		T1	142		T11	487
all_pins[20]	values[0x0]	1102755	1			T24	1		T25	28		T1	457
all_pins[20]	values[0x1]	674899	1			T25	10		T1	341		T11	643
all_pins[20]	transitions[0x0=>0x1]	405556	1			T25	5		T1	140		T11	443
all_pins[20]	transitions[0x1=>0x0]	399664	1			T25	12		T1	220		T11	374
all_pins[21]	values[0x0]	1105949	1			T24	1		T25	17		T1	493
all_pins[21]	values[0x1]	671705	1			T25	21		T1	305		T11	655
all_pins[21]	transitions[0x0=>0x1]	399685	1			T25	15		T1	161		T11	409
all_pins[21]	transitions[0x1=>0x0]	402879	1			T25	4		T1	197		T11	397
all_pins[22]	values[0x0]	1107376	1			T24	1		T25	13		T1	503
all_pins[22]	values[0x1]	670278	1			T25	25		T1	295		T11	692
all_pins[22]	transitions[0x0=>0x1]	400268	1			T25	10		T1	144		T11	387
all_pins[22]	transitions[0x1=>0x0]	401695	1			T25	6		T1	154		T11	350
all_pins[23]	values[0x0]	1107078	1			T24	1		T25	15		T1	461
all_pins[23]	values[0x1]	670576	1			T25	23		T1	337		T11	742
all_pins[23]	transitions[0x0=>0x1]	401586	1			T25	4		T1	201		T11	436
all_pins[23]	transitions[0x1=>0x0]	401288	1			T25	6		T1	159		T11	386
all_pins[24]	values[0x0]	1104019	1			T24	1		T25	25		T1	535
all_pins[24]	values[0x1]	673635	1			T25	13		T1	263		T11	612
all_pins[24]	transitions[0x0=>0x1]	403856	1			T25	5		T1	154		T11	326
all_pins[24]	transitions[0x1=>0x0]	400797	1			T25	15		T1	228		T11	456
all_pins[25]	values[0x0]	1106103	1			T24	1		T25	17		T1	560
all_pins[25]	values[0x1]	671551	1			T25	21		T1	238		T11	573
all_pins[25]	transitions[0x0=>0x1]	401011	1			T25	14		T1	142		T11	368
all_pins[25]	transitions[0x1=>0x0]	403095	1			T25	6		T1	167		T11	407
all_pins[26]	values[0x0]	1104068	1			T24	1		T25	20		T1	480
all_pins[26]	values[0x1]	673586	1			T25	18		T1	318		T11	693
all_pins[26]	transitions[0x0=>0x1]	402485	1			T25	8		T1	229		T11	443
all_pins[26]	transitions[0x1=>0x0]	400450	1			T25	11		T1	149		T11	323
all_pins[27]	values[0x0]	1104346	1			T24	1		T25	25		T1	503
all_pins[27]	values[0x1]	673308	1			T25	13		T1	295		T11	585
all_pins[27]	transitions[0x0=>0x1]	401892	1			T25	5		T1	200		T11	327
all_pins[27]	transitions[0x1=>0x0]	402170	1			T25	10		T1	223		T11	435
all_pins[28]	values[0x0]	1106893	1			T24	1		T25	25		T1	508
all_pins[28]	values[0x1]	670761	1			T25	13		T1	290		T11	626
all_pins[28]	transitions[0x0=>0x1]	401490	1			T25	6		T1	181		T11	392
all_pins[28]	transitions[0x1=>0x0]	404037	1			T25	6		T1	186		T11	351
all_pins[29]	values[0x0]	1103419	1			T24	1		T25	20		T1	560
all_pins[29]	values[0x1]	674235	1			T25	18		T1	238		T11	740
all_pins[29]	transitions[0x0=>0x1]	403717	1			T25	11		T1	127		T11	491
all_pins[29]	transitions[0x1=>0x0]	400243	1			T25	6		T1	179		T11	377
all_pins[30]	values[0x0]	1105208	1			T24	1		T25	17		T1	541
all_pins[30]	values[0x1]	672446	1			T25	21		T1	257		T11	771
all_pins[30]	transitions[0x0=>0x1]	402599	1			T25	13		T1	184		T11	464
all_pins[30]	transitions[0x1=>0x0]	404388	1			T25	10		T1	165		T11	433
all_pins[31]	values[0x0]	1105362	1			T24	1		T25	16		T1	548
all_pins[31]	values[0x1]	672292	1			T25	22		T1	250		T11	719
all_pins[31]	transitions[0x0=>0x1]	402511	1			T25	12		T1	148		T11	382
all_pins[31]	transitions[0x1=>0x0]	402665	1			T25	11		T1	155		T11	434