Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	7032746	1			T24	205		T25	600		T1	1984
all_values[1]	7032746	1			T24	205		T25	600		T1	1984
all_values[2]	7032746	1			T24	205		T25	600		T1	1984
all_values[3]	7032746	1			T24	205		T25	600		T1	1984
all_values[4]	7032746	1			T24	205		T25	600		T1	1984
all_values[5]	7032746	1			T24	205		T25	600		T1	1984
all_values[6]	7032746	1			T24	205		T25	600		T1	1984
all_values[7]	7032746	1			T24	205		T25	600		T1	1984
all_values[8]	7032746	1			T24	205		T25	600		T1	1984
all_values[9]	7032746	1			T24	205		T25	600		T1	1984
all_values[10]	7032746	1			T24	205		T25	600		T1	1984
all_values[11]	7032746	1			T24	205		T25	600		T1	1984
all_values[12]	7032746	1			T24	205		T25	600		T1	1984
all_values[13]	7032746	1			T24	205		T25	600		T1	1984
all_values[14]	7032746	1			T24	205		T25	600		T1	1984
all_values[15]	7032746	1			T24	205		T25	600		T1	1984
all_values[16]	7032746	1			T24	205		T25	600		T1	1984
all_values[17]	7032746	1			T24	205		T25	600		T1	1984
all_values[18]	7032746	1			T24	205		T25	600		T1	1984
all_values[19]	7032746	1			T24	205		T25	600		T1	1984
all_values[20]	7032746	1			T24	205		T25	600		T1	1984
all_values[21]	7032746	1			T24	205		T25	600		T1	1984
all_values[22]	7032746	1			T24	205		T25	600		T1	1984
all_values[23]	7032746	1			T24	205		T25	600		T1	1984
all_values[24]	7032746	1			T24	205		T25	600		T1	1984
all_values[25]	7032746	1			T24	205		T25	600		T1	1984
all_values[26]	7032746	1			T24	205		T25	600		T1	1984
all_values[27]	7032746	1			T24	205		T25	600		T1	1984
all_values[28]	7032746	1			T24	205		T25	600		T1	1984
all_values[29]	7032746	1			T24	205		T25	600		T1	1984
all_values[30]	7032746	1			T24	205		T25	600		T1	1984
all_values[31]	7032746	1			T24	205		T25	600		T1	1984

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

147585630

1

T24

6560

T25

19200

T1

31729

auto[1]

77462242

1

T1

31759

T11

86860

T18

3510

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

85351927

1

T24

6560

T25

19200

T1

7842

auto[1]

139695945

1

T1

55646

T11

153457

T18

6430

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

222870221

1

T24

6560

T25

19200

T1

60920

auto[1]

2177651

1

T1

2568

T11

2518

T26

58422

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	2421772	1			T24	205		T25	600		T1	91
all_values[0]	auto[0]	auto[0]	auto[1]	2159195	1			T1	860		T11	2254		T18	113
all_values[0]	auto[0]	auto[1]	auto[0]	243364	1			T1	106		T11	221		T18	17
all_values[0]	auto[0]	auto[1]	auto[1]	2140576	1			T1	842		T11	2446		T18	89
all_values[0]	auto[1]	auto[0]	auto[1]	34015	1			T1	39		T11	37		T26	920
all_values[0]	auto[1]	auto[1]	auto[1]	33824	1			T1	46		T11	44		T26	917
all_values[1]	auto[0]	auto[0]	auto[0]	2427195	1			T24	205		T25	600		T1	94
all_values[1]	auto[0]	auto[0]	auto[1]	2155843	1			T1	783		T11	2758		T18	75
all_values[1]	auto[0]	auto[1]	auto[0]	240220	1			T1	83		T11	210		T18	12
all_values[1]	auto[0]	auto[1]	auto[1]	2141404	1			T1	940		T11	2029		T18	127
all_values[1]	auto[1]	auto[0]	auto[1]	34417	1			T1	43		T11	39		T26	917
all_values[1]	auto[1]	auto[1]	auto[1]	33667	1			T1	41		T11	45		T26	927
all_values[2]	auto[0]	auto[0]	auto[0]	2425055	1			T24	205		T25	600		T1	155
all_values[2]	auto[0]	auto[0]	auto[1]	2130741	1			T1	928		T11	2776		T18	165
all_values[2]	auto[0]	auto[1]	auto[0]	246533	1			T1	129		T11	191		T18	5
all_values[2]	auto[0]	auto[1]	auto[1]	2162429	1			T1	684		T11	2013		T18	41
all_values[2]	auto[1]	auto[0]	auto[1]	34515	1			T1	52		T11	51		T26	1051
all_values[2]	auto[1]	auto[1]	auto[1]	33473	1			T1	36		T11	38		T26	831
all_values[3]	auto[0]	auto[0]	auto[0]	2423511	1			T24	205		T25	600		T1	123
all_values[3]	auto[0]	auto[0]	auto[1]	2144373	1			T1	655		T11	2471		T18	121
all_values[3]	auto[0]	auto[1]	auto[0]	242924	1			T1	204		T11	355		T18	14
all_values[3]	auto[0]	auto[1]	auto[1]	2154178	1			T1	917		T11	2072		T18	65
all_values[3]	auto[1]	auto[0]	auto[1]	33645	1			T1	35		T11	40		T26	907
all_values[3]	auto[1]	auto[1]	auto[1]	34115	1			T1	50		T11	41		T26	936
all_values[4]	auto[0]	auto[0]	auto[0]	2427844	1			T24	205		T25	600		T1	127
all_values[4]	auto[0]	auto[0]	auto[1]	2168221	1			T1	852		T11	2757		T18	124
all_values[4]	auto[0]	auto[1]	auto[0]	244804	1			T1	124		T11	282		T18	6
all_values[4]	auto[0]	auto[1]	auto[1]	2124007	1			T1	802		T11	1872		T18	90
all_values[4]	auto[1]	auto[0]	auto[1]	34246	1			T1	34		T11	46		T26	899
all_values[4]	auto[1]	auto[1]	auto[1]	33624	1			T1	45		T11	29		T26	903
all_values[5]	auto[0]	auto[0]	auto[0]	2422490	1			T24	205		T25	600		T1	93
all_values[5]	auto[0]	auto[0]	auto[1]	2152670	1			T1	716		T11	1956		T18	112
all_values[5]	auto[0]	auto[1]	auto[0]	240035	1			T1	128		T11	261		T18	11
all_values[5]	auto[0]	auto[1]	auto[1]	2149462	1			T1	968		T11	2709		T18	88
all_values[5]	auto[1]	auto[0]	auto[1]	34325	1			T1	28		T11	49		T26	945
all_values[5]	auto[1]	auto[1]	auto[1]	33764	1			T1	51		T11	38		T26	913
all_values[6]	auto[0]	auto[0]	auto[0]	2424317	1			T24	205		T25	600		T1	120
all_values[6]	auto[0]	auto[0]	auto[1]	2164155	1			T1	754		T11	2609		T18	107
all_values[6]	auto[0]	auto[1]	auto[0]	243513	1			T1	179		T11	215		T18	17
all_values[6]	auto[0]	auto[1]	auto[1]	2132824	1			T1	845		T11	2255		T18	97
all_values[6]	auto[1]	auto[0]	auto[1]	33860	1			T1	39		T11	29		T26	893
all_values[6]	auto[1]	auto[1]	auto[1]	34077	1			T1	47		T11	42		T26	920
all_values[7]	auto[0]	auto[0]	auto[0]	2421849	1			T24	205		T25	600		T1	119
all_values[7]	auto[0]	auto[0]	auto[1]	2143799	1			T1	726		T11	1890		T18	94
all_values[7]	auto[0]	auto[1]	auto[0]	243373	1			T1	103		T11	309		T18	14
all_values[7]	auto[0]	auto[1]	auto[1]	2155686	1			T1	960		T11	2804		T18	91
all_values[7]	auto[1]	auto[0]	auto[1]	34290	1			T1	38		T11	27		T26	945
all_values[7]	auto[1]	auto[1]	auto[1]	33749	1			T1	38		T11	41		T26	888
all_values[8]	auto[0]	auto[0]	auto[0]	2428196	1			T24	205		T25	600		T1	126
all_values[8]	auto[0]	auto[0]	auto[1]	2151690	1			T1	691		T11	3075		T18	80
all_values[8]	auto[0]	auto[1]	auto[0]	245248	1			T1	184		T11	270		T18	1
all_values[8]	auto[0]	auto[1]	auto[1]	2139777	1			T1	888		T11	1658		T18	127
all_values[8]	auto[1]	auto[0]	auto[1]	34191	1			T1	36		T11	43		T26	877
all_values[8]	auto[1]	auto[1]	auto[1]	33644	1			T1	59		T11	42		T26	945
all_values[9]	auto[0]	auto[0]	auto[0]	2424629	1			T24	205		T25	600		T1	120
all_values[9]	auto[0]	auto[0]	auto[1]	2161301	1			T1	809		T11	2108		T18	98
all_values[9]	auto[0]	auto[1]	auto[0]	241673	1			T1	117		T11	181		T18	5
all_values[9]	auto[0]	auto[1]	auto[1]	2137235	1			T1	854		T11	2750		T18	110
all_values[9]	auto[1]	auto[0]	auto[1]	34228	1			T1	44		T11	31		T26	913
all_values[9]	auto[1]	auto[1]	auto[1]	33680	1			T1	40		T11	34		T26	899
all_values[10]	auto[0]	auto[0]	auto[0]	2424124	1			T24	205		T25	600		T1	135
all_values[10]	auto[0]	auto[0]	auto[1]	2176841	1			T1	803		T11	1750		T18	92
all_values[10]	auto[0]	auto[1]	auto[0]	245951	1			T1	147		T11	324		T18	6
all_values[10]	auto[0]	auto[1]	auto[1]	2118022	1			T1	813		T11	2993		T18	116
all_values[10]	auto[1]	auto[0]	auto[1]	34456	1			T1	49		T11	23		T26	914
all_values[10]	auto[1]	auto[1]	auto[1]	33352	1			T1	37		T11	45		T26	901
all_values[11]	auto[0]	auto[0]	auto[0]	2425362	1			T24	205		T25	600		T1	176
all_values[11]	auto[0]	auto[0]	auto[1]	2152946	1			T1	776		T11	2060		T18	131
all_values[11]	auto[0]	auto[1]	auto[0]	243206	1			T1	130		T11	273		T18	9
all_values[11]	auto[0]	auto[1]	auto[1]	2143064	1			T1	830		T11	2596		T18	77
all_values[11]	auto[1]	auto[0]	auto[1]	34509	1			T1	38		T11	47		T26	886
all_values[11]	auto[1]	auto[1]	auto[1]	33659	1			T1	34		T11	39		T26	980
all_values[12]	auto[0]	auto[0]	auto[0]	2425187	1			T24	205		T25	600		T1	147
all_values[12]	auto[0]	auto[0]	auto[1]	2162817	1			T1	942		T11	2122		T18	85
all_values[12]	auto[0]	auto[1]	auto[0]	243152	1			T1	63		T11	335		T18	4
all_values[12]	auto[0]	auto[1]	auto[1]	2133367	1			T1	762		T11	2588		T18	131
all_values[12]	auto[1]	auto[0]	auto[1]	34697	1			T1	39		T11	38		T26	932
all_values[12]	auto[1]	auto[1]	auto[1]	33526	1			T1	31		T11	31		T26	891
all_values[13]	auto[0]	auto[0]	auto[0]	2425765	1			T24	205		T25	600		T1	129
all_values[13]	auto[0]	auto[0]	auto[1]	2158247	1			T1	856		T11	2034		T18	95
all_values[13]	auto[0]	auto[1]	auto[0]	243082	1			T1	99		T11	249		T18	14
all_values[13]	auto[0]	auto[1]	auto[1]	2137605	1			T1	829		T11	2685		T18	101
all_values[13]	auto[1]	auto[0]	auto[1]	34624	1			T1	39		T11	37		T26	883
all_values[13]	auto[1]	auto[1]	auto[1]	33423	1			T1	32		T11	37		T26	954
all_values[14]	auto[0]	auto[0]	auto[0]	2423309	1			T24	205		T25	600		T1	57
all_values[14]	auto[0]	auto[0]	auto[1]	2150593	1			T1	942		T11	2194		T18	82
all_values[14]	auto[0]	auto[1]	auto[0]	243544	1			T1	94		T11	246		T18	11
all_values[14]	auto[0]	auto[1]	auto[1]	2147012	1			T1	804		T11	2526		T18	127
all_values[14]	auto[1]	auto[0]	auto[1]	34274	1			T1	52		T11	40		T26	930
all_values[14]	auto[1]	auto[1]	auto[1]	34014	1			T1	35		T11	46		T26	934
all_values[15]	auto[0]	auto[0]	auto[0]	2424156	1			T24	205		T25	600		T1	160
all_values[15]	auto[0]	auto[0]	auto[1]	2142387	1			T1	771		T11	2034		T18	115
all_values[15]	auto[0]	auto[1]	auto[0]	242549	1			T1	155		T11	220		T18	9
all_values[15]	auto[0]	auto[1]	auto[1]	2155554	1			T1	826		T11	2671		T18	82
all_values[15]	auto[1]	auto[0]	auto[1]	34110	1			T1	32		T11	42		T26	882
all_values[15]	auto[1]	auto[1]	auto[1]	33990	1			T1	40		T11	35		T26	934
all_values[16]	auto[0]	auto[0]	auto[0]	2422134	1			T24	205		T25	600		T1	103
all_values[16]	auto[0]	auto[0]	auto[1]	2160727	1			T1	889		T11	1838		T18	132
all_values[16]	auto[0]	auto[1]	auto[0]	242149	1			T1	109		T11	303		T18	11
all_values[16]	auto[0]	auto[1]	auto[1]	2139491	1			T1	799		T11	2781		T18	58
all_values[16]	auto[1]	auto[0]	auto[1]	34437	1			T1	39		T11	41		T26	926
all_values[16]	auto[1]	auto[1]	auto[1]	33808	1			T1	45		T11	42		T26	914
all_values[17]	auto[0]	auto[0]	auto[0]	2425412	1			T24	205		T25	600		T1	121
all_values[17]	auto[0]	auto[0]	auto[1]	2144316	1			T1	801		T11	2102		T18	67
all_values[17]	auto[0]	auto[1]	auto[0]	243190	1			T1	74		T11	291		T18	19
all_values[17]	auto[0]	auto[1]	auto[1]	2151820	1			T1	903		T11	2599		T18	126
all_values[17]	auto[1]	auto[0]	auto[1]	34123	1			T1	38		T11	36		T26	848
all_values[17]	auto[1]	auto[1]	auto[1]	33885	1			T1	47		T11	33		T26	941
all_values[18]	auto[0]	auto[0]	auto[0]	2422954	1			T24	205		T25	600		T1	87
all_values[18]	auto[0]	auto[0]	auto[1]	2150647	1			T1	890		T11	1933		T18	103
all_values[18]	auto[0]	auto[1]	auto[0]	245823	1			T1	126		T11	252		T18	26
all_values[18]	auto[0]	auto[1]	auto[1]	2145501	1			T1	805		T11	2780		T18	85
all_values[18]	auto[1]	auto[0]	auto[1]	33947	1			T1	39		T11	42		T26	942
all_values[18]	auto[1]	auto[1]	auto[1]	33874	1			T1	37		T11	44		T26	871
all_values[19]	auto[0]	auto[0]	auto[0]	2426394	1			T24	205		T25	600		T1	93
all_values[19]	auto[0]	auto[0]	auto[1]	2158411	1			T1	569		T11	3142		T18	71
all_values[19]	auto[0]	auto[1]	auto[0]	239968	1			T1	126		T11	249		T18	9
all_values[19]	auto[0]	auto[1]	auto[1]	2140193	1			T1	1126		T11	1587		T18	136
all_values[19]	auto[1]	auto[0]	auto[1]	34631	1			T1	23		T11	55		T26	949
all_values[19]	auto[1]	auto[1]	auto[1]	33149	1			T1	47		T11	26		T26	850
all_values[20]	auto[0]	auto[0]	auto[0]	2423568	1			T24	205		T25	600		T1	81
all_values[20]	auto[0]	auto[0]	auto[1]	2135484	1			T1	817		T11	2277		T18	96
all_values[20]	auto[0]	auto[1]	auto[0]	243338	1			T1	141		T11	273		T18	11
all_values[20]	auto[0]	auto[1]	auto[1]	2162083	1			T1	867		T11	2484		T18	80
all_values[20]	auto[1]	auto[0]	auto[1]	34301	1			T1	35		T11	36		T26	983
all_values[20]	auto[1]	auto[1]	auto[1]	33972	1			T1	43		T11	39		T26	846
all_values[21]	auto[0]	auto[0]	auto[0]	2424607	1			T24	205		T25	600		T1	141
all_values[21]	auto[0]	auto[0]	auto[1]	2159988	1			T1	820		T11	3042		T18	93
all_values[21]	auto[0]	auto[1]	auto[0]	242295	1			T1	112		T11	136		T18	3
all_values[21]	auto[0]	auto[1]	auto[1]	2137824	1			T1	838		T11	1811		T18	123
all_values[21]	auto[1]	auto[0]	auto[1]	34279	1			T1	42		T11	44		T26	958
all_values[21]	auto[1]	auto[1]	auto[1]	33753	1			T1	31		T11	32		T26	896
all_values[22]	auto[0]	auto[0]	auto[0]	2427350	1			T24	205		T25	600		T1	115
all_values[22]	auto[0]	auto[0]	auto[1]	2151653	1			T1	953		T11	1960		T18	124
all_values[22]	auto[0]	auto[1]	auto[0]	242834	1			T1	64		T11	239		T18	9
all_values[22]	auto[0]	auto[1]	auto[1]	2142645	1			T1	783		T11	2750		T18	79
all_values[22]	auto[1]	auto[0]	auto[1]	34198	1			T1	35		T11	36		T26	905
all_values[22]	auto[1]	auto[1]	auto[1]	34066	1			T1	34		T11	48		T26	947
all_values[23]	auto[0]	auto[0]	auto[0]	2423792	1			T24	205		T25	600		T1	119
all_values[23]	auto[0]	auto[0]	auto[1]	2149900	1			T1	609		T11	1946		T18	73
all_values[23]	auto[0]	auto[1]	auto[0]	242975	1			T1	163		T11	250		T18	24
all_values[23]	auto[0]	auto[1]	auto[1]	2148071	1			T1	1021		T11	2761		T18	124
all_values[23]	auto[1]	auto[0]	auto[1]	34176	1			T1	25		T11	48		T26	879
all_values[23]	auto[1]	auto[1]	auto[1]	33832	1			T1	47		T11	29		T26	888
all_values[24]	auto[0]	auto[0]	auto[0]	2417764	1			T24	205		T25	600		T1	83
all_values[24]	auto[0]	auto[0]	auto[1]	2147635	1			T1	940		T11	2109		T18	110
all_values[24]	auto[0]	auto[1]	auto[0]	245130	1			T1	163		T11	305		T18	7
all_values[24]	auto[0]	auto[1]	auto[1]	2154247	1			T1	710		T11	2606		T18	106
all_values[24]	auto[1]	auto[0]	auto[1]	34385	1			T1	55		T11	50		T26	868
all_values[24]	auto[1]	auto[1]	auto[1]	33585	1			T1	33		T11	37		T26	942
all_values[25]	auto[0]	auto[0]	auto[0]	2424386	1			T24	205		T25	600		T1	118
all_values[25]	auto[0]	auto[0]	auto[1]	2149837	1			T1	1059		T11	2766		T18	102
all_values[25]	auto[0]	auto[1]	auto[0]	241825	1			T1	119		T11	312		T18	1
all_values[25]	auto[0]	auto[1]	auto[1]	2148750	1			T1	604		T11	1890		T18	101
all_values[25]	auto[1]	auto[0]	auto[1]	34402	1			T1	51		T11	42		T26	895
all_values[25]	auto[1]	auto[1]	auto[1]	33546	1			T1	33		T11	39		T26	901
all_values[26]	auto[0]	auto[0]	auto[0]	2425586	1			T24	205		T25	600		T1	107
all_values[26]	auto[0]	auto[0]	auto[1]	2148282	1			T1	715		T11	1842		T18	104
all_values[26]	auto[0]	auto[1]	auto[0]	241220	1			T1	145		T11	343		T18	12
all_values[26]	auto[0]	auto[1]	auto[1]	2149478	1			T1	933		T11	2866		T18	102
all_values[26]	auto[1]	auto[0]	auto[1]	34429	1			T1	37		T11	35		T26	960
all_values[26]	auto[1]	auto[1]	auto[1]	33751	1			T1	47		T11	44		T26	897
all_values[27]	auto[0]	auto[0]	auto[0]	2427859	1			T24	205		T25	600		T1	98
all_values[27]	auto[0]	auto[0]	auto[1]	2149043	1			T1	966		T11	2741		T18	80
all_values[27]	auto[0]	auto[1]	auto[0]	240411	1			T1	58		T11	242		T18	21
all_values[27]	auto[0]	auto[1]	auto[1]	2147082	1			T1	784		T11	1937		T18	122
all_values[27]	auto[1]	auto[0]	auto[1]	34391	1			T1	44		T11	46		T26	963
all_values[27]	auto[1]	auto[1]	auto[1]	33960	1			T1	34		T11	33		T26	878
all_values[28]	auto[0]	auto[0]	auto[0]	2421326	1			T24	205		T25	600		T1	127
all_values[28]	auto[0]	auto[0]	auto[1]	2161174	1			T1	928		T11	2786		T18	94
all_values[28]	auto[0]	auto[1]	auto[0]	241232	1			T1	99		T11	296		T18	15
all_values[28]	auto[0]	auto[1]	auto[1]	2141126	1			T1	750		T11	1875		T18	106
all_values[28]	auto[1]	auto[0]	auto[1]	34434	1			T1	47		T11	44		T26	965
all_values[28]	auto[1]	auto[1]	auto[1]	33454	1			T1	33		T11	27		T26	872
all_values[29]	auto[0]	auto[0]	auto[0]	2425046	1			T24	205		T25	600		T1	172
all_values[29]	auto[0]	auto[0]	auto[1]	2149096	1			T1	924		T11	2002		T18	105
all_values[29]	auto[0]	auto[1]	auto[0]	242479	1			T1	126		T11	219		T18	17
all_values[29]	auto[0]	auto[1]	auto[1]	2147838	1			T1	684		T11	2799		T18	87
all_values[29]	auto[1]	auto[0]	auto[1]	34451	1			T1	46		T11	44		T26	908
all_values[29]	auto[1]	auto[1]	auto[1]	33836	1			T1	32		T11	45		T26	893
all_values[30]	auto[0]	auto[0]	auto[0]	2421898	1			T24	205		T25	600		T1	235
all_values[30]	auto[0]	auto[0]	auto[1]	2163474	1			T1	860		T11	2512		T18	120
all_values[30]	auto[0]	auto[1]	auto[0]	243888	1			T1	145		T11	182		T18	6
all_values[30]	auto[0]	auto[1]	auto[1]	2135231	1			T1	661		T11	2314		T18	76
all_values[30]	auto[1]	auto[0]	auto[1]	34601	1			T1	51		T11	33		T26	884
all_values[30]	auto[1]	auto[1]	auto[1]	33654	1			T1	32		T11	42		T26	920
all_values[31]	auto[0]	auto[0]	auto[0]	2422791	1			T24	205		T25	600		T1	120
all_values[31]	auto[0]	auto[0]	auto[1]	2154335	1			T1	944		T11	1834		T18	119
all_values[31]	auto[0]	auto[1]	auto[0]	242371	1			T1	135		T11	337		T18	16
all_values[31]	auto[0]	auto[1]	auto[1]	2144891	1			T1	698		T11	2752		T18	78
all_values[31]	auto[1]	auto[0]	auto[1]	34594	1			T1	45		T11	37		T26	875
all_values[31]	auto[1]	auto[1]	auto[1]	33764	1			T1	42		T11	43		T26	891

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal