Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	7017885	1			T24	307		T25	600		T1	1863
bins_for_gpio_bits[1]	7017885	1			T24	307		T25	600		T1	1863
bins_for_gpio_bits[2]	7017885	1			T24	307		T25	600		T1	1863
bins_for_gpio_bits[3]	7017885	1			T24	307		T25	600		T1	1863
bins_for_gpio_bits[4]	7017885	1			T24	307		T25	600		T1	1863
bins_for_gpio_bits[5]	7017885	1			T24	307		T25	600		T1	1863
bins_for_gpio_bits[6]	7017885	1			T24	307		T25	600		T1	1863
bins_for_gpio_bits[7]	7017885	1			T24	307		T25	600		T1	1863
bins_for_gpio_bits[8]	7017885	1			T24	307		T25	600		T1	1863
bins_for_gpio_bits[9]	7017885	1			T24	307		T25	600		T1	1863
bins_for_gpio_bits[10]	7017885	1			T24	307		T25	600		T1	1863
bins_for_gpio_bits[11]	7017885	1			T24	307		T25	600		T1	1863
bins_for_gpio_bits[12]	7017885	1			T24	307		T25	600		T1	1863
bins_for_gpio_bits[13]	7017885	1			T24	307		T25	600		T1	1863
bins_for_gpio_bits[14]	7017885	1			T24	307		T25	600		T1	1863
bins_for_gpio_bits[15]	7017885	1			T24	307		T25	600		T1	1863
bins_for_gpio_bits[16]	7017885	1			T24	307		T25	600		T1	1863
bins_for_gpio_bits[17]	7017885	1			T24	307		T25	600		T1	1863
bins_for_gpio_bits[18]	7017885	1			T24	307		T25	600		T1	1863
bins_for_gpio_bits[19]	7017885	1			T24	307		T25	600		T1	1863
bins_for_gpio_bits[20]	7017885	1			T24	307		T25	600		T1	1863
bins_for_gpio_bits[21]	7017885	1			T24	307		T25	600		T1	1863
bins_for_gpio_bits[22]	7017885	1			T24	307		T25	600		T1	1863
bins_for_gpio_bits[23]	7017885	1			T24	307		T25	600		T1	1863
bins_for_gpio_bits[24]	7017885	1			T24	307		T25	600		T1	1863
bins_for_gpio_bits[25]	7017885	1			T24	307		T25	600		T1	1863
bins_for_gpio_bits[26]	7017885	1			T24	307		T25	600		T1	1863
bins_for_gpio_bits[27]	7017885	1			T24	307		T25	600		T1	1863
bins_for_gpio_bits[28]	7017885	1			T24	307		T25	600		T1	1863
bins_for_gpio_bits[29]	7017885	1			T24	307		T25	600		T1	1863
bins_for_gpio_bits[30]	7017885	1			T24	307		T25	600		T1	1863
bins_for_gpio_bits[31]	7017885	1			T24	307		T25	600		T1	1863

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

115790339

1

T24

6548

T25

9924

T1

14014

auto[1]

108781981

1

T24

3276

T25

9276

T1

45602

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

184734690

1

T24

6673

T25

19200

T1

34481

auto[1]

39837630

1

T24

3151

T1

25135

T11

50767

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

173143001

1

T24

6454

T25

19200

T1

30076

auto[1]

51429319

1

T24

3370

T1

29540

T11

72179

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	2441418	1			T24	102		T25	274		T1	15
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	2340330	1			T24	60		T25	326		T1	475
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	623510	1			T24	34		T1	430		T11	754
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	547852	1			T24	61		T1	23		T11	1359
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	444134	1			T1	489		T11	130		T12	39
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	620641	1			T24	50		T1	431		T11	748
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	2441706	1			T24	110		T25	299		T1	15
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	2339388	1			T24	40		T25	301		T1	544
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	627331	1			T24	49		T1	365		T11	835
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	546779	1			T24	56		T1	18		T11	1235
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	441093	1			T1	484		T11	113		T12	14
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	621588	1			T24	52		T1	437		T11	714
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	2439414	1			T24	105		T25	294		T1	12
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	2345435	1			T24	46		T25	306		T1	515
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	623124	1			T24	32		T1	447		T11	877
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	547277	1			T24	80		T1	21		T11	1258
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	442107	1			T1	575		T11	112		T12	22
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	620528	1			T24	44		T1	293		T11	822
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	2447701	1			T24	105		T25	308		T1	26
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	2334489	1			T24	53		T25	292		T1	625
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	627141	1			T24	49		T1	433		T11	826
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	544016	1			T24	44		T1	14		T11	1392
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	439926	1			T1	503		T11	128		T12	3
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	624612	1			T24	56		T1	262		T11	716
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	2455196	1			T24	78		T25	333		T1	12
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	2330774	1			T24	62		T25	267		T1	427
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	630977	1			T24	64		T1	544		T11	845
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	544317	1			T24	55		T1	20		T11	1129
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	437302	1			T1	502		T11	110		T12	1
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	619319	1			T24	48		T1	358		T11	878
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	2443807	1			T24	108		T25	299		T1	17
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	2341917	1			T24	50		T25	301		T1	423
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	628805	1			T24	38		T1	400		T11	788
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	545877	1			T24	61		T1	25		T11	1293
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	438468	1			T1	540		T11	96		T12	1
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	619011	1			T24	50		T1	458		T11	840
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	2447406	1			T24	114		T25	293		T1	21
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	2338304	1			T24	48		T25	307		T1	486
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	630586	1			T24	57		T1	367		T11	631
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	543087	1			T24	48		T1	20		T11	1482
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	436408	1			T1	463		T11	112		T12	35
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	622094	1			T24	40		T1	506		T11	868
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	2433867	1			T24	98		T25	320		T1	20
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	2345224	1			T24	54		T25	280		T1	573
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	625887	1			T24	44		T1	410		T11	897
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	549232	1			T24	46		T1	23		T11	1270
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	442823	1			T1	435		T11	136		T12	22
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	620852	1			T24	65		T1	402		T11	712
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	2446646	1			T24	105		T25	313		T1	18
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	2335355	1			T24	59		T25	287		T1	605
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	624809	1			T24	28		T1	337		T11	846
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	547921	1			T24	47		T1	21		T11	1360
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	445754	1			T1	546		T11	122		T12	18
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	617400	1			T24	68		T1	336		T11	821
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	2445240	1			T24	99		T25	279		T1	21
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	2335686	1			T24	61		T25	321		T1	574
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	629530	1			T24	76		T1	327		T11	780
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	543039	1			T24	19		T1	14		T11	1288
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	441320	1			T1	535		T11	109		T12	7
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	623070	1			T24	52		T1	392		T11	869
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	2452827	1			T24	123		T25	319		T1	40
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	2325813	1			T24	46		T25	281		T1	612
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	628728	1			T24	62		T1	458		T11	767
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	546557	1			T24	46		T1	5		T11	1359
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	440680	1			T1	381		T11	103		T12	8
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	623280	1			T24	30		T1	367		T11	734
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	2444390	1			T24	106		T25	284		T1	35
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	2336253	1			T24	43		T25	316		T1	492
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	625976	1			T24	38		T1	350		T11	716
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	547702	1			T24	74		T1	15		T11	1460
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	440068	1			T1	565		T11	126		T12	16
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	623496	1			T24	46		T1	406		T11	1000
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	2450823	1			T24	99		T25	310		T1	15
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	2334785	1			T24	51		T25	290		T1	411
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	624206	1			T24	38		T1	389		T11	737
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	543381	1			T24	61		T1	21		T11	1435
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	443004	1			T1	532		T11	93		T12	38
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	621686	1			T24	58		T1	495		T11	816
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	2442158	1			T24	96		T25	266		T1	20
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	2338248	1			T24	58		T25	334		T1	533
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	627840	1			T24	54		T1	434		T11	765
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	545034	1			T24	57		T1	28		T11	1338
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	440180	1			T1	445		T11	114		T12	16
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	624425	1			T24	42		T1	403		T11	742
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	2443331	1			T24	112		T25	297		T1	10
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	2336238	1			T24	50		T25	303		T1	505
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	626013	1			T24	29		T1	384		T11	686
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	547721	1			T24	64		T1	32		T11	1447
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	443863	1			T1	513		T11	113		T12	27
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	620719	1			T24	52		T1	419		T11	831
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	2442498	1			T24	96		T25	293		T1	19
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	2339648	1			T24	52		T25	307		T1	571
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	626373	1			T24	35		T1	359		T11	913
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	546925	1			T24	54		T1	18		T11	1302
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	440791	1			T1	522		T11	124		T12	21
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	621650	1			T24	70		T1	374		T11	684
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	2453805	1			T24	120		T25	290		T1	33
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	2334340	1			T24	42		T25	310		T1	553
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	624860	1			T24	70		T1	391		T11	786
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	547857	1			T24	28		T1	10		T11	1379
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	438669	1			T1	523		T11	83		T12	17
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	618354	1			T24	47		T1	353		T11	877
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	2455462	1			T24	95		T25	297		T1	23
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	2334332	1			T24	47		T25	303		T1	481
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	621578	1			T24	26		T1	304		T11	711
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	545603	1			T24	81		T1	21		T11	1336
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	443000	1			T1	585		T11	104		T12	39
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	617910	1			T24	58		T1	449		T11	776
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	2455898	1			T24	107		T25	331		T1	25
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	2331134	1			T24	53		T25	269		T1	566
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	625907	1			T24	35		T1	291		T11	605
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	545915	1			T24	54		T1	26		T11	1543
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	441335	1			T1	604		T11	116		T12	11
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	617696	1			T24	58		T1	351		T11	773
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	2445204	1			T24	101		T25	365		T1	19
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	2346043	1			T24	53		T25	235		T1	458
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	625759	1			T24	38		T1	454		T11	875
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	543747	1			T24	81		T1	22		T11	1233
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	440536	1			T1	510		T11	107		T12	13
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	616596	1			T24	34		T1	400		T11	787
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	2447866	1			T24	108		T25	346		T1	20
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	2338790	1			T24	45		T25	254		T1	451
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	623561	1			T24	58		T1	341		T11	738
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	546269	1			T24	50		T1	19		T11	1424
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	443081	1			T1	512		T11	119		T12	43
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	618318	1			T24	46		T1	520		T11	750
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	2443770	1			T24	87		T25	249		T1	28
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	2340635	1			T24	51		T25	351		T1	626
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	625641	1			T24	42		T1	353		T11	723
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	546960	1			T24	65		T1	25		T11	1377
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	442630	1			T1	571		T11	105		T12	23
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	618249	1			T24	62		T1	260		T11	830
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	2448095	1			T24	125		T25	321		T1	11
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	2337450	1			T24	47		T25	279		T1	440
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	621078	1			T24	43		T1	526		T11	698
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	550200	1			T24	46		T1	32		T11	1464
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	444236	1			T1	495		T11	95		T12	22
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	616826	1			T24	46		T1	359		T11	891
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	2436222	1			T24	96		T25	341		T1	23
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	2350675	1			T24	50		T25	259		T1	600
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	627717	1			T24	41		T1	445		T11	817
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	546510	1			T24	60		T1	19		T11	1207
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	439146	1			T1	409		T11	118		T12	18
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	617615	1			T24	60		T1	367		T11	849
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	2446651	1			T24	110		T25	361		T1	18
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	2344719	1			T24	55		T25	239		T1	454
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	621452	1			T24	54		T1	399		T11	804
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	546795	1			T24	38		T1	19		T11	1455
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	442321	1			T1	547		T11	122		T12	7
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	615947	1			T24	50		T1	426		T11	800
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	2446860	1			T24	109		T25	334		T1	33
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	2340388	1			T24	46		T25	266		T1	560
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	624351	1			T24	56		T1	331		T11	843
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	546313	1			T24	68		T1	12		T11	1275
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	441887	1			T1	522		T11	87		T12	23
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	618086	1			T24	28		T1	405		T11	648
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	2450347	1			T24	115		T25	327		T1	29
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	2344398	1			T24	44		T25	273		T1	577
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	623318	1			T24	68		T1	389		T11	773
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	544162	1			T24	36		T1	14		T11	1390
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	439877	1			T1	521		T11	158		T12	5
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	615783	1			T24	44		T1	333		T11	678
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	2450552	1			T24	113		T25	311		T1	32
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	2335107	1			T24	52		T25	289		T1	580
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	627661	1			T24	38		T1	457		T11	796
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	546493	1			T24	42		T1	12		T11	1406
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	439550	1			T1	443		T11	144		T12	32
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	618522	1			T24	62		T1	339		T11	819
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	2443314	1			T24	83		T25	325		T1	24
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	2345934	1			T24	55		T25	275		T1	367
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	623459	1			T24	34		T1	361		T11	983
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	547639	1			T24	77		T1	25		T11	1292
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	441328	1			T1	609		T11	117		T12	7
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	616211	1			T24	58		T1	477		T11	744
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	2445483	1			T24	103		T25	336		T1	29
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	2345548	1			T24	52		T25	264		T1	639
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	623018	1			T24	52		T1	422		T11	863
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	548586	1			T24	40		T1	9		T11	1319
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	437597	1			T1	451		T11	106		T12	40
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	617653	1			T24	60		T1	313		T11	880
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	2442690	1			T24	94		T25	315		T1	25
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	2340461	1			T24	50		T25	285		T1	432
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	621946	1			T24	56		T1	353		T11	850
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	549676	1			T24	46		T1	21		T11	1378
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	444377	1			T1	632		T11	100		T12	24
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	618735	1			T24	61		T1	400		T11	791
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	2456707	1			T24	123		T25	294		T1	26
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	2333110	1			T24	42		T25	306		T1	521
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	622554	1			T24	54		T1	435		T11	832
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	548847	1			T24	26		T1	10		T11	1275
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	440605	1			T1	513		T11	90		T12	16
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	616062	1			T24	62		T1	358		T11	719

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal