Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	7017885	1			T24	307		T25	600		T1	1863
bins_for_gpio_bits[1]	7017885	1			T24	307		T25	600		T1	1863
bins_for_gpio_bits[2]	7017885	1			T24	307		T25	600		T1	1863
bins_for_gpio_bits[3]	7017885	1			T24	307		T25	600		T1	1863
bins_for_gpio_bits[4]	7017885	1			T24	307		T25	600		T1	1863
bins_for_gpio_bits[5]	7017885	1			T24	307		T25	600		T1	1863
bins_for_gpio_bits[6]	7017885	1			T24	307		T25	600		T1	1863
bins_for_gpio_bits[7]	7017885	1			T24	307		T25	600		T1	1863
bins_for_gpio_bits[8]	7017885	1			T24	307		T25	600		T1	1863
bins_for_gpio_bits[9]	7017885	1			T24	307		T25	600		T1	1863
bins_for_gpio_bits[10]	7017885	1			T24	307		T25	600		T1	1863
bins_for_gpio_bits[11]	7017885	1			T24	307		T25	600		T1	1863
bins_for_gpio_bits[12]	7017885	1			T24	307		T25	600		T1	1863
bins_for_gpio_bits[13]	7017885	1			T24	307		T25	600		T1	1863
bins_for_gpio_bits[14]	7017885	1			T24	307		T25	600		T1	1863
bins_for_gpio_bits[15]	7017885	1			T24	307		T25	600		T1	1863
bins_for_gpio_bits[16]	7017885	1			T24	307		T25	600		T1	1863
bins_for_gpio_bits[17]	7017885	1			T24	307		T25	600		T1	1863
bins_for_gpio_bits[18]	7017885	1			T24	307		T25	600		T1	1863
bins_for_gpio_bits[19]	7017885	1			T24	307		T25	600		T1	1863
bins_for_gpio_bits[20]	7017885	1			T24	307		T25	600		T1	1863
bins_for_gpio_bits[21]	7017885	1			T24	307		T25	600		T1	1863
bins_for_gpio_bits[22]	7017885	1			T24	307		T25	600		T1	1863
bins_for_gpio_bits[23]	7017885	1			T24	307		T25	600		T1	1863
bins_for_gpio_bits[24]	7017885	1			T24	307		T25	600		T1	1863
bins_for_gpio_bits[25]	7017885	1			T24	307		T25	600		T1	1863
bins_for_gpio_bits[26]	7017885	1			T24	307		T25	600		T1	1863
bins_for_gpio_bits[27]	7017885	1			T24	307		T25	600		T1	1863
bins_for_gpio_bits[28]	7017885	1			T24	307		T25	600		T1	1863
bins_for_gpio_bits[29]	7017885	1			T24	307		T25	600		T1	1863
bins_for_gpio_bits[30]	7017885	1			T24	307		T25	600		T1	1863
bins_for_gpio_bits[31]	7017885	1			T24	307		T25	600		T1	1863

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

115790339

1

T24

6548

T25

9924

T1

14014

auto[1]

108781981

1

T24

3276

T25

9276

T1

45602

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

115784584

1

T24

6545

T25

9924

T1

14021

auto[1]

108787736

1

T24

3279

T25

9276

T1

45595

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	3500346	1			T24	187		T25	274		T1	405
bins_for_gpio_bits[0]	auto[0]	auto[1]	112247	1			T24	10		T1	64		T11	114
bins_for_gpio_bits[0]	auto[1]	auto[0]	112434	1			T24	10		T1	63		T11	114
bins_for_gpio_bits[0]	auto[1]	auto[1]	3292858	1			T24	100		T25	326		T1	1331
bins_for_gpio_bits[1]	auto[0]	auto[0]	3503334	1			T24	202		T25	299		T1	347
bins_for_gpio_bits[1]	auto[0]	auto[1]	112317	1			T24	13		T1	51		T11	116
bins_for_gpio_bits[1]	auto[1]	auto[0]	112482	1			T24	13		T1	51		T11	116
bins_for_gpio_bits[1]	auto[1]	auto[1]	3289752	1			T24	79		T25	301		T1	1414
bins_for_gpio_bits[2]	auto[0]	auto[0]	3497212	1			T24	201		T25	294		T1	422
bins_for_gpio_bits[2]	auto[0]	auto[1]	112439	1			T24	16		T1	59		T11	117
bins_for_gpio_bits[2]	auto[1]	auto[0]	112603	1			T24	16		T1	58		T11	117
bins_for_gpio_bits[2]	auto[1]	auto[1]	3295631	1			T24	74		T25	306		T1	1324
bins_for_gpio_bits[3]	auto[0]	auto[0]	3506134	1			T24	183		T25	308		T1	415
bins_for_gpio_bits[3]	auto[0]	auto[1]	112552	1			T24	15		T1	58		T11	123
bins_for_gpio_bits[3]	auto[1]	auto[0]	112724	1			T24	15		T1	58		T11	123
bins_for_gpio_bits[3]	auto[1]	auto[1]	3286475	1			T24	94		T25	292		T1	1332
bins_for_gpio_bits[4]	auto[0]	auto[0]	3517691	1			T24	181		T25	333		T1	519
bins_for_gpio_bits[4]	auto[0]	auto[1]	112644	1			T24	16		T1	57		T11	117
bins_for_gpio_bits[4]	auto[1]	auto[0]	112799	1			T24	16		T1	57		T11	117
bins_for_gpio_bits[4]	auto[1]	auto[1]	3274751	1			T24	94		T25	267		T1	1230
bins_for_gpio_bits[5]	auto[0]	auto[0]	3505656	1			T24	193		T25	299		T1	392
bins_for_gpio_bits[5]	auto[0]	auto[1]	112668	1			T24	14		T1	50		T11	138
bins_for_gpio_bits[5]	auto[1]	auto[0]	112833	1			T24	14		T1	50		T11	138
bins_for_gpio_bits[5]	auto[1]	auto[1]	3286728	1			T24	86		T25	301		T1	1371
bins_for_gpio_bits[6]	auto[0]	auto[0]	3507806	1			T24	205		T25	293		T1	359
bins_for_gpio_bits[6]	auto[0]	auto[1]	113070	1			T24	14		T1	49		T11	135
bins_for_gpio_bits[6]	auto[1]	auto[0]	113273	1			T24	14		T1	49		T11	135
bins_for_gpio_bits[6]	auto[1]	auto[1]	3283736	1			T24	74		T25	307		T1	1406
bins_for_gpio_bits[7]	auto[0]	auto[0]	3496088	1			T24	172		T25	320		T1	384
bins_for_gpio_bits[7]	auto[0]	auto[1]	112717	1			T24	15		T1	70		T11	122
bins_for_gpio_bits[7]	auto[1]	auto[0]	112898	1			T24	16		T1	69		T11	122
bins_for_gpio_bits[7]	auto[1]	auto[1]	3296182	1			T24	104		T25	280		T1	1340
bins_for_gpio_bits[8]	auto[0]	auto[0]	3507087	1			T24	168		T25	313		T1	330
bins_for_gpio_bits[8]	auto[0]	auto[1]	112097	1			T24	12		T1	46		T11	130
bins_for_gpio_bits[8]	auto[1]	auto[0]	112289	1			T24	12		T1	46		T11	130
bins_for_gpio_bits[8]	auto[1]	auto[1]	3286412	1			T24	115		T25	287		T1	1441
bins_for_gpio_bits[9]	auto[0]	auto[0]	3505039	1			T24	180		T25	279		T1	316
bins_for_gpio_bits[9]	auto[0]	auto[1]	112556	1			T24	14		T1	46		T11	141
bins_for_gpio_bits[9]	auto[1]	auto[0]	112770	1			T24	14		T1	46		T11	141
bins_for_gpio_bits[9]	auto[1]	auto[1]	3287520	1			T24	99		T25	321		T1	1455
bins_for_gpio_bits[10]	auto[0]	auto[0]	3514806	1			T24	220		T25	319		T1	436
bins_for_gpio_bits[10]	auto[0]	auto[1]	113120	1			T24	11		T1	67		T11	122
bins_for_gpio_bits[10]	auto[1]	auto[0]	113306	1			T24	11		T1	67		T11	122
bins_for_gpio_bits[10]	auto[1]	auto[1]	3276653	1			T24	65		T25	281		T1	1293
bins_for_gpio_bits[11]	auto[0]	auto[0]	3505414	1			T24	203		T25	284		T1	343
bins_for_gpio_bits[11]	auto[0]	auto[1]	112536	1			T24	15		T1	57		T11	156
bins_for_gpio_bits[11]	auto[1]	auto[0]	112654	1			T24	15		T1	57		T11	156
bins_for_gpio_bits[11]	auto[1]	auto[1]	3287281	1			T24	74		T25	316		T1	1406
bins_for_gpio_bits[12]	auto[0]	auto[0]	3505878	1			T24	186		T25	310		T1	374
bins_for_gpio_bits[12]	auto[0]	auto[1]	112351	1			T24	12		T1	52		T11	123
bins_for_gpio_bits[12]	auto[1]	auto[0]	112532	1			T24	12		T1	51		T11	123
bins_for_gpio_bits[12]	auto[1]	auto[1]	3287124	1			T24	97		T25	290		T1	1386
bins_for_gpio_bits[13]	auto[0]	auto[0]	3501836	1			T24	194		T25	266		T1	417
bins_for_gpio_bits[13]	auto[0]	auto[1]	112995	1			T24	13		T1	65		T11	120
bins_for_gpio_bits[13]	auto[1]	auto[0]	113196	1			T24	13		T1	65		T11	120
bins_for_gpio_bits[13]	auto[1]	auto[1]	3289858	1			T24	87		T25	334		T1	1316
bins_for_gpio_bits[14]	auto[0]	auto[0]	3504008	1			T24	189		T25	297		T1	366
bins_for_gpio_bits[14]	auto[0]	auto[1]	112858	1			T24	16		T1	60		T11	126
bins_for_gpio_bits[14]	auto[1]	auto[0]	113057	1			T24	16		T1	60		T11	126
bins_for_gpio_bits[14]	auto[1]	auto[1]	3287962	1			T24	86		T25	303		T1	1377
bins_for_gpio_bits[15]	auto[0]	auto[0]	3502748	1			T24	170		T25	293		T1	347
bins_for_gpio_bits[15]	auto[0]	auto[1]	112854	1			T24	15		T1	49		T11	124
bins_for_gpio_bits[15]	auto[1]	auto[0]	113048	1			T24	15		T1	49		T11	124
bins_for_gpio_bits[15]	auto[1]	auto[1]	3289235	1			T24	107		T25	307		T1	1418
bins_for_gpio_bits[16]	auto[0]	auto[0]	3513580	1			T24	206		T25	290		T1	376
bins_for_gpio_bits[16]	auto[0]	auto[1]	112798	1			T24	11		T1	58		T11	132
bins_for_gpio_bits[16]	auto[1]	auto[0]	112942	1			T24	12		T1	58		T11	132
bins_for_gpio_bits[16]	auto[1]	auto[1]	3278565	1			T24	78		T25	310		T1	1371
bins_for_gpio_bits[17]	auto[0]	auto[0]	3510365	1			T24	189		T25	297		T1	298
bins_for_gpio_bits[17]	auto[0]	auto[1]	112089	1			T24	13		T1	50		T11	129
bins_for_gpio_bits[17]	auto[1]	auto[0]	112278	1			T24	13		T1	50		T11	129
bins_for_gpio_bits[17]	auto[1]	auto[1]	3283153	1			T24	92		T25	303		T1	1465
bins_for_gpio_bits[18]	auto[0]	auto[0]	3514599	1			T24	180		T25	331		T1	295
bins_for_gpio_bits[18]	auto[0]	auto[1]	112937	1			T24	16		T1	47		T11	133
bins_for_gpio_bits[18]	auto[1]	auto[0]	113121	1			T24	16		T1	47		T11	133
bins_for_gpio_bits[18]	auto[1]	auto[1]	3277228	1			T24	95		T25	269		T1	1474
bins_for_gpio_bits[19]	auto[0]	auto[0]	3501992	1			T24	208		T25	365		T1	439
bins_for_gpio_bits[19]	auto[0]	auto[1]	112539	1			T24	12		T1	56		T11	136
bins_for_gpio_bits[19]	auto[1]	auto[0]	112718	1			T24	12		T1	56		T11	136
bins_for_gpio_bits[19]	auto[1]	auto[1]	3290636	1			T24	75		T25	235		T1	1312
bins_for_gpio_bits[20]	auto[0]	auto[0]	3504465	1			T24	199		T25	346		T1	319
bins_for_gpio_bits[20]	auto[0]	auto[1]	113031	1			T24	17		T1	62		T11	131
bins_for_gpio_bits[20]	auto[1]	auto[0]	113231	1			T24	17		T1	61		T11	131
bins_for_gpio_bits[20]	auto[1]	auto[1]	3287158	1			T24	74		T25	254		T1	1421
bins_for_gpio_bits[21]	auto[0]	auto[0]	3503547	1			T24	178		T25	249		T1	354
bins_for_gpio_bits[21]	auto[0]	auto[1]	112645	1			T24	16		T1	52		T11	129
bins_for_gpio_bits[21]	auto[1]	auto[0]	112824	1			T24	16		T1	52		T11	129
bins_for_gpio_bits[21]	auto[1]	auto[1]	3288869	1			T24	97		T25	351		T1	1405
bins_for_gpio_bits[22]	auto[0]	auto[0]	3507173	1			T24	204		T25	321		T1	507
bins_for_gpio_bits[22]	auto[0]	auto[1]	112022	1			T24	10		T1	63		T11	136
bins_for_gpio_bits[22]	auto[1]	auto[0]	112200	1			T24	10		T1	62		T11	136
bins_for_gpio_bits[22]	auto[1]	auto[1]	3286490	1			T24	83		T25	279		T1	1231
bins_for_gpio_bits[23]	auto[0]	auto[0]	3497581	1			T24	186		T25	341		T1	420
bins_for_gpio_bits[23]	auto[0]	auto[1]	112670	1			T24	11		T1	67		T11	140
bins_for_gpio_bits[23]	auto[1]	auto[0]	112868	1			T24	11		T1	67		T11	140
bins_for_gpio_bits[23]	auto[1]	auto[1]	3294766	1			T24	99		T25	259		T1	1309
bins_for_gpio_bits[24]	auto[0]	auto[0]	3502061	1			T24	188		T25	361		T1	382
bins_for_gpio_bits[24]	auto[0]	auto[1]	112656	1			T24	14		T1	54		T11	141
bins_for_gpio_bits[24]	auto[1]	auto[0]	112837	1			T24	14		T1	54		T11	141
bins_for_gpio_bits[24]	auto[1]	auto[1]	3290331	1			T24	91		T25	239		T1	1373
bins_for_gpio_bits[25]	auto[0]	auto[0]	3504578	1			T24	223		T25	334		T1	328
bins_for_gpio_bits[25]	auto[0]	auto[1]	112790	1			T24	10		T1	48		T11	113
bins_for_gpio_bits[25]	auto[1]	auto[0]	112946	1			T24	10		T1	48		T11	113
bins_for_gpio_bits[25]	auto[1]	auto[1]	3287571	1			T24	64		T25	266		T1	1439
bins_for_gpio_bits[26]	auto[0]	auto[0]	3505159	1			T24	207		T25	327		T1	369
bins_for_gpio_bits[26]	auto[0]	auto[1]	112490	1			T24	12		T1	64		T11	118
bins_for_gpio_bits[26]	auto[1]	auto[0]	112668	1			T24	12		T1	63		T11	118
bins_for_gpio_bits[26]	auto[1]	auto[1]	3287568	1			T24	76		T25	273		T1	1367
bins_for_gpio_bits[27]	auto[0]	auto[0]	3511814	1			T24	180		T25	311		T1	436
bins_for_gpio_bits[27]	auto[0]	auto[1]	112697	1			T24	13		T1	65		T11	127
bins_for_gpio_bits[27]	auto[1]	auto[0]	112892	1			T24	13		T1	65		T11	127
bins_for_gpio_bits[27]	auto[1]	auto[1]	3280482	1			T24	101		T25	289		T1	1297
bins_for_gpio_bits[28]	auto[0]	auto[0]	3501758	1			T24	180		T25	325		T1	361
bins_for_gpio_bits[28]	auto[0]	auto[1]	112461	1			T24	14		T1	49		T11	139
bins_for_gpio_bits[28]	auto[1]	auto[0]	112654	1			T24	14		T1	49		T11	139
bins_for_gpio_bits[28]	auto[1]	auto[1]	3291012	1			T24	99		T25	275		T1	1404
bins_for_gpio_bits[29]	auto[0]	auto[0]	3504284	1			T24	183		T25	336		T1	399
bins_for_gpio_bits[29]	auto[0]	auto[1]	112650	1			T24	12		T1	61		T11	148
bins_for_gpio_bits[29]	auto[1]	auto[0]	112803	1			T24	12		T1	61		T11	148
bins_for_gpio_bits[29]	auto[1]	auto[1]	3288148	1			T24	100		T25	264		T1	1342
bins_for_gpio_bits[30]	auto[0]	auto[0]	3501611	1			T24	180		T25	315		T1	355
bins_for_gpio_bits[30]	auto[0]	auto[1]	112542	1			T24	15		T1	44		T11	132
bins_for_gpio_bits[30]	auto[1]	auto[0]	112701	1			T24	16		T1	44		T11	132
bins_for_gpio_bits[30]	auto[1]	auto[1]	3291031	1			T24	96		T25	285		T1	1420
bins_for_gpio_bits[31]	auto[0]	auto[0]	3515659	1			T24	192		T25	294		T1	413
bins_for_gpio_bits[31]	auto[0]	auto[1]	112237	1			T24	11		T1	58		T11	131
bins_for_gpio_bits[31]	auto[1]	auto[0]	112449	1			T24	11		T1	58		T11	131
bins_for_gpio_bits[31]	auto[1]	auto[1]	3277540	1			T24	93		T25	306		T1	1334