Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4614982 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
990 |
| auto[1] |
2417764 |
1 |
|
|
T1 |
994 |
|
T11 |
2711 |
|
T18 |
106 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6729527 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1930 |
| auto[1] |
303219 |
1 |
|
|
T1 |
54 |
|
T11 |
249 |
|
T18 |
8 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4620035 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
822 |
| auto[1] |
2412711 |
1 |
|
|
T1 |
1162 |
|
T11 |
2460 |
|
T18 |
112 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1061075 |
1 |
|
|
T1 |
579 |
|
T11 |
1181 |
|
T18 |
52 |
| auto[1] |
auto[0] |
auto[1] |
153028 |
1 |
|
|
T1 |
30 |
|
T11 |
131 |
|
T18 |
4 |
| auto[1] |
auto[1] |
auto[0] |
1048417 |
1 |
|
|
T1 |
529 |
|
T11 |
1030 |
|
T18 |
52 |
| auto[1] |
auto[1] |
auto[1] |
150191 |
1 |
|
|
T1 |
24 |
|
T11 |
118 |
|
T18 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4617455 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
920 |
| auto[1] |
2415291 |
1 |
|
|
T1 |
1064 |
|
T11 |
2284 |
|
T18 |
139 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6728134 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1942 |
| auto[1] |
304612 |
1 |
|
|
T1 |
42 |
|
T11 |
323 |
|
T18 |
8 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4612189 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
954 |
| auto[1] |
2420557 |
1 |
|
|
T1 |
1030 |
|
T11 |
3038 |
|
T18 |
126 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1063417 |
1 |
|
|
T1 |
464 |
|
T11 |
1657 |
|
T18 |
49 |
| auto[1] |
auto[0] |
auto[1] |
152763 |
1 |
|
|
T1 |
22 |
|
T11 |
205 |
|
T18 |
3 |
| auto[1] |
auto[1] |
auto[0] |
1052528 |
1 |
|
|
T1 |
524 |
|
T11 |
1058 |
|
T18 |
69 |
| auto[1] |
auto[1] |
auto[1] |
151849 |
1 |
|
|
T1 |
20 |
|
T11 |
118 |
|
T18 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4635421 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
987 |
| auto[1] |
2397325 |
1 |
|
|
T1 |
997 |
|
T11 |
3362 |
|
T18 |
122 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6728797 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1949 |
| auto[1] |
303949 |
1 |
|
|
T1 |
35 |
|
T11 |
222 |
|
T18 |
12 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4619223 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1067 |
| auto[1] |
2413523 |
1 |
|
|
T1 |
917 |
|
T11 |
2375 |
|
T18 |
125 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1062573 |
1 |
|
|
T1 |
446 |
|
T11 |
806 |
|
T18 |
55 |
| auto[1] |
auto[0] |
auto[1] |
153605 |
1 |
|
|
T1 |
21 |
|
T11 |
82 |
|
T18 |
5 |
| auto[1] |
auto[1] |
auto[0] |
1047001 |
1 |
|
|
T1 |
436 |
|
T11 |
1347 |
|
T18 |
58 |
| auto[1] |
auto[1] |
auto[1] |
150344 |
1 |
|
|
T1 |
14 |
|
T11 |
140 |
|
T18 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4612817 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
990 |
| auto[1] |
2419929 |
1 |
|
|
T1 |
994 |
|
T11 |
2908 |
|
T18 |
86 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6729349 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1945 |
| auto[1] |
303397 |
1 |
|
|
T1 |
39 |
|
T11 |
257 |
|
T18 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4617326 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1032 |
| auto[1] |
2415420 |
1 |
|
|
T1 |
952 |
|
T11 |
2498 |
|
T18 |
74 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1061796 |
1 |
|
|
T1 |
455 |
|
T11 |
1145 |
|
T18 |
32 |
| auto[1] |
auto[0] |
auto[1] |
151755 |
1 |
|
|
T1 |
23 |
|
T11 |
107 |
|
T18 |
3 |
| auto[1] |
auto[1] |
auto[0] |
1050227 |
1 |
|
|
T1 |
458 |
|
T11 |
1096 |
|
T18 |
37 |
| auto[1] |
auto[1] |
auto[1] |
151642 |
1 |
|
|
T1 |
16 |
|
T11 |
150 |
|
T18 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4622701 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1128 |
| auto[1] |
2410045 |
1 |
|
|
T1 |
856 |
|
T11 |
2954 |
|
T18 |
135 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6728647 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1950 |
| auto[1] |
304099 |
1 |
|
|
T1 |
34 |
|
T11 |
273 |
|
T18 |
9 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4612711 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1046 |
| auto[1] |
2420035 |
1 |
|
|
T1 |
938 |
|
T11 |
2414 |
|
T18 |
117 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1066135 |
1 |
|
|
T1 |
546 |
|
T11 |
1161 |
|
T18 |
51 |
| auto[1] |
auto[0] |
auto[1] |
153796 |
1 |
|
|
T1 |
19 |
|
T11 |
153 |
|
T18 |
4 |
| auto[1] |
auto[1] |
auto[0] |
1049801 |
1 |
|
|
T1 |
358 |
|
T11 |
980 |
|
T18 |
57 |
| auto[1] |
auto[1] |
auto[1] |
150303 |
1 |
|
|
T1 |
15 |
|
T11 |
120 |
|
T18 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4618636 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1024 |
| auto[1] |
2414110 |
1 |
|
|
T1 |
960 |
|
T11 |
2971 |
|
T18 |
115 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6730293 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1945 |
| auto[1] |
302453 |
1 |
|
|
T1 |
39 |
|
T11 |
307 |
|
T18 |
8 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4621040 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1047 |
| auto[1] |
2411706 |
1 |
|
|
T1 |
937 |
|
T11 |
2656 |
|
T18 |
134 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1060247 |
1 |
|
|
T1 |
478 |
|
T11 |
1147 |
|
T18 |
70 |
| auto[1] |
auto[0] |
auto[1] |
151643 |
1 |
|
|
T1 |
20 |
|
T11 |
125 |
|
T18 |
3 |
| auto[1] |
auto[1] |
auto[0] |
1049006 |
1 |
|
|
T1 |
420 |
|
T11 |
1202 |
|
T18 |
56 |
| auto[1] |
auto[1] |
auto[1] |
150810 |
1 |
|
|
T1 |
19 |
|
T11 |
182 |
|
T18 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4608176 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1051 |
| auto[1] |
2424570 |
1 |
|
|
T1 |
933 |
|
T11 |
2818 |
|
T18 |
138 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6732474 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1947 |
| auto[1] |
300272 |
1 |
|
|
T1 |
37 |
|
T11 |
312 |
|
T18 |
7 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4638061 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1088 |
| auto[1] |
2394685 |
1 |
|
|
T1 |
896 |
|
T11 |
3128 |
|
T18 |
66 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1046390 |
1 |
|
|
T1 |
512 |
|
T11 |
1161 |
|
T18 |
27 |
| auto[1] |
auto[0] |
auto[1] |
150091 |
1 |
|
|
T1 |
26 |
|
T11 |
125 |
|
T18 |
4 |
| auto[1] |
auto[1] |
auto[0] |
1048023 |
1 |
|
|
T1 |
347 |
|
T11 |
1655 |
|
T18 |
32 |
| auto[1] |
auto[1] |
auto[1] |
150181 |
1 |
|
|
T1 |
11 |
|
T11 |
187 |
|
T18 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4600653 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
963 |
| auto[1] |
2432093 |
1 |
|
|
T1 |
1021 |
|
T11 |
2926 |
|
T18 |
91 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6726885 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1947 |
| auto[1] |
305861 |
1 |
|
|
T1 |
37 |
|
T11 |
194 |
|
T18 |
7 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4602878 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
811 |
| auto[1] |
2429868 |
1 |
|
|
T1 |
1173 |
|
T11 |
2219 |
|
T18 |
88 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1060049 |
1 |
|
|
T1 |
576 |
|
T11 |
1068 |
|
T18 |
60 |
| auto[1] |
auto[0] |
auto[1] |
152067 |
1 |
|
|
T1 |
21 |
|
T11 |
90 |
|
T18 |
7 |
| auto[1] |
auto[1] |
auto[0] |
1063958 |
1 |
|
|
T1 |
560 |
|
T11 |
957 |
|
T18 |
21 |
| auto[1] |
auto[1] |
auto[1] |
153794 |
1 |
|
|
T1 |
16 |
|
T11 |
104 |
|
T26 |
2921 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4617298 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1031 |
| auto[1] |
2415448 |
1 |
|
|
T1 |
953 |
|
T11 |
3126 |
|
T18 |
69 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6731177 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1940 |
| auto[1] |
301569 |
1 |
|
|
T1 |
44 |
|
T11 |
243 |
|
T18 |
7 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4634085 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
917 |
| auto[1] |
2398661 |
1 |
|
|
T1 |
1067 |
|
T11 |
2301 |
|
T18 |
132 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1046578 |
1 |
|
|
T1 |
510 |
|
T11 |
920 |
|
T18 |
85 |
| auto[1] |
auto[0] |
auto[1] |
150321 |
1 |
|
|
T1 |
26 |
|
T11 |
108 |
|
T18 |
6 |
| auto[1] |
auto[1] |
auto[0] |
1050514 |
1 |
|
|
T1 |
513 |
|
T11 |
1138 |
|
T18 |
40 |
| auto[1] |
auto[1] |
auto[1] |
151248 |
1 |
|
|
T1 |
18 |
|
T11 |
135 |
|
T18 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4603851 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
960 |
| auto[1] |
2428895 |
1 |
|
|
T1 |
1024 |
|
T11 |
2923 |
|
T18 |
145 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6732546 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1951 |
| auto[1] |
300200 |
1 |
|
|
T1 |
33 |
|
T11 |
208 |
|
T18 |
10 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4633941 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1033 |
| auto[1] |
2398805 |
1 |
|
|
T1 |
951 |
|
T11 |
2310 |
|
T18 |
110 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1045881 |
1 |
|
|
T1 |
430 |
|
T11 |
1158 |
|
T18 |
43 |
| auto[1] |
auto[0] |
auto[1] |
149673 |
1 |
|
|
T1 |
11 |
|
T11 |
113 |
|
T18 |
3 |
| auto[1] |
auto[1] |
auto[0] |
1052724 |
1 |
|
|
T1 |
488 |
|
T11 |
944 |
|
T18 |
57 |
| auto[1] |
auto[1] |
auto[1] |
150527 |
1 |
|
|
T1 |
22 |
|
T11 |
95 |
|
T18 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4607548 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1016 |
| auto[1] |
2425198 |
1 |
|
|
T1 |
968 |
|
T11 |
3076 |
|
T18 |
111 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6727918 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1948 |
| auto[1] |
304828 |
1 |
|
|
T1 |
36 |
|
T11 |
196 |
|
T18 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4608337 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
951 |
| auto[1] |
2424409 |
1 |
|
|
T1 |
1033 |
|
T11 |
2154 |
|
T18 |
73 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1063745 |
1 |
|
|
T1 |
510 |
|
T11 |
958 |
|
T18 |
24 |
| auto[1] |
auto[0] |
auto[1] |
152538 |
1 |
|
|
T1 |
16 |
|
T11 |
111 |
|
T26 |
3150 |
| auto[1] |
auto[1] |
auto[0] |
1055836 |
1 |
|
|
T1 |
487 |
|
T11 |
1000 |
|
T18 |
45 |
| auto[1] |
auto[1] |
auto[1] |
152290 |
1 |
|
|
T1 |
20 |
|
T11 |
85 |
|
T18 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4619436 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
685 |
| auto[1] |
2413310 |
1 |
|
|
T1 |
1299 |
|
T11 |
1862 |
|
T18 |
145 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6730999 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1947 |
| auto[1] |
301747 |
1 |
|
|
T1 |
37 |
|
T11 |
231 |
|
T18 |
11 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4632320 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
899 |
| auto[1] |
2400426 |
1 |
|
|
T1 |
1085 |
|
T11 |
2467 |
|
T18 |
129 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1059309 |
1 |
|
|
T1 |
371 |
|
T11 |
1399 |
|
T18 |
43 |
| auto[1] |
auto[0] |
auto[1] |
152514 |
1 |
|
|
T1 |
11 |
|
T11 |
157 |
|
T18 |
4 |
| auto[1] |
auto[1] |
auto[0] |
1039370 |
1 |
|
|
T1 |
677 |
|
T11 |
837 |
|
T18 |
75 |
| auto[1] |
auto[1] |
auto[1] |
149233 |
1 |
|
|
T1 |
26 |
|
T11 |
74 |
|
T18 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4590311 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1135 |
| auto[1] |
2442435 |
1 |
|
|
T1 |
849 |
|
T11 |
2242 |
|
T18 |
46 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6729487 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1949 |
| auto[1] |
303259 |
1 |
|
|
T1 |
35 |
|
T11 |
237 |
|
T18 |
8 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4621069 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
984 |
| auto[1] |
2411677 |
1 |
|
|
T1 |
1000 |
|
T11 |
2620 |
|
T18 |
104 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1050959 |
1 |
|
|
T1 |
547 |
|
T11 |
1216 |
|
T18 |
69 |
| auto[1] |
auto[0] |
auto[1] |
150655 |
1 |
|
|
T1 |
27 |
|
T11 |
125 |
|
T18 |
6 |
| auto[1] |
auto[1] |
auto[0] |
1057459 |
1 |
|
|
T1 |
418 |
|
T11 |
1167 |
|
T18 |
27 |
| auto[1] |
auto[1] |
auto[1] |
152604 |
1 |
|
|
T1 |
8 |
|
T11 |
112 |
|
T18 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4593353 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
933 |
| auto[1] |
2439393 |
1 |
|
|
T1 |
1051 |
|
T11 |
2796 |
|
T18 |
91 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6728327 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1940 |
| auto[1] |
304419 |
1 |
|
|
T1 |
44 |
|
T11 |
229 |
|
T18 |
7 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4607760 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1015 |
| auto[1] |
2424986 |
1 |
|
|
T1 |
969 |
|
T11 |
2073 |
|
T18 |
114 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1053809 |
1 |
|
|
T1 |
417 |
|
T11 |
1044 |
|
T18 |
66 |
| auto[1] |
auto[0] |
auto[1] |
150625 |
1 |
|
|
T1 |
14 |
|
T11 |
135 |
|
T18 |
5 |
| auto[1] |
auto[1] |
auto[0] |
1066758 |
1 |
|
|
T1 |
508 |
|
T11 |
800 |
|
T18 |
41 |
| auto[1] |
auto[1] |
auto[1] |
153794 |
1 |
|
|
T1 |
30 |
|
T11 |
94 |
|
T18 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4618874 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1003 |
| auto[1] |
2413872 |
1 |
|
|
T1 |
981 |
|
T11 |
1979 |
|
T18 |
126 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6727900 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1947 |
| auto[1] |
304846 |
1 |
|
|
T1 |
37 |
|
T11 |
289 |
|
T18 |
11 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4602510 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
994 |
| auto[1] |
2430236 |
1 |
|
|
T1 |
990 |
|
T11 |
2749 |
|
T18 |
135 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1068752 |
1 |
|
|
T1 |
459 |
|
T11 |
1609 |
|
T18 |
52 |
| auto[1] |
auto[0] |
auto[1] |
153128 |
1 |
|
|
T1 |
22 |
|
T11 |
208 |
|
T18 |
5 |
| auto[1] |
auto[1] |
auto[0] |
1056638 |
1 |
|
|
T1 |
494 |
|
T11 |
851 |
|
T18 |
72 |
| auto[1] |
auto[1] |
auto[1] |
151718 |
1 |
|
|
T1 |
15 |
|
T11 |
81 |
|
T18 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4613201 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1103 |
| auto[1] |
2419545 |
1 |
|
|
T1 |
881 |
|
T11 |
3037 |
|
T18 |
88 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6726997 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1934 |
| auto[1] |
305749 |
1 |
|
|
T1 |
50 |
|
T11 |
329 |
|
T18 |
11 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4607083 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
918 |
| auto[1] |
2425663 |
1 |
|
|
T1 |
1066 |
|
T11 |
3132 |
|
T18 |
145 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1066807 |
1 |
|
|
T1 |
582 |
|
T11 |
1236 |
|
T18 |
78 |
| auto[1] |
auto[0] |
auto[1] |
154347 |
1 |
|
|
T1 |
28 |
|
T11 |
143 |
|
T18 |
7 |
| auto[1] |
auto[1] |
auto[0] |
1053107 |
1 |
|
|
T1 |
434 |
|
T11 |
1567 |
|
T18 |
56 |
| auto[1] |
auto[1] |
auto[1] |
151402 |
1 |
|
|
T1 |
22 |
|
T11 |
186 |
|
T18 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4607868 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
753 |
| auto[1] |
2424878 |
1 |
|
|
T1 |
1231 |
|
T11 |
3040 |
|
T18 |
148 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6730023 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1938 |
| auto[1] |
302723 |
1 |
|
|
T1 |
46 |
|
T11 |
356 |
|
T18 |
12 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4624234 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1071 |
| auto[1] |
2408512 |
1 |
|
|
T1 |
913 |
|
T11 |
2997 |
|
T18 |
133 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1056554 |
1 |
|
|
T1 |
328 |
|
T11 |
1014 |
|
T18 |
52 |
| auto[1] |
auto[0] |
auto[1] |
151556 |
1 |
|
|
T1 |
8 |
|
T11 |
135 |
|
T18 |
6 |
| auto[1] |
auto[1] |
auto[0] |
1049235 |
1 |
|
|
T1 |
539 |
|
T11 |
1627 |
|
T18 |
69 |
| auto[1] |
auto[1] |
auto[1] |
151167 |
1 |
|
|
T1 |
38 |
|
T11 |
221 |
|
T18 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4599784 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1078 |
| auto[1] |
2432962 |
1 |
|
|
T1 |
906 |
|
T11 |
2948 |
|
T18 |
113 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6730823 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1938 |
| auto[1] |
301923 |
1 |
|
|
T1 |
46 |
|
T11 |
240 |
|
T18 |
11 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4629466 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
932 |
| auto[1] |
2403280 |
1 |
|
|
T1 |
1052 |
|
T11 |
2516 |
|
T18 |
144 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1049050 |
1 |
|
|
T1 |
524 |
|
T11 |
1118 |
|
T18 |
54 |
| auto[1] |
auto[0] |
auto[1] |
150277 |
1 |
|
|
T1 |
25 |
|
T11 |
123 |
|
T18 |
5 |
| auto[1] |
auto[1] |
auto[0] |
1052307 |
1 |
|
|
T1 |
482 |
|
T11 |
1158 |
|
T18 |
79 |
| auto[1] |
auto[1] |
auto[1] |
151646 |
1 |
|
|
T1 |
21 |
|
T11 |
117 |
|
T18 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4608625 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1228 |
| auto[1] |
2424121 |
1 |
|
|
T1 |
756 |
|
T11 |
2241 |
|
T18 |
102 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6730012 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1964 |
| auto[1] |
302734 |
1 |
|
|
T1 |
20 |
|
T11 |
179 |
|
T18 |
8 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4624004 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1216 |
| auto[1] |
2408742 |
1 |
|
|
T1 |
768 |
|
T11 |
2126 |
|
T18 |
125 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1052732 |
1 |
|
|
T1 |
499 |
|
T11 |
1056 |
|
T18 |
68 |
| auto[1] |
auto[0] |
auto[1] |
150633 |
1 |
|
|
T1 |
17 |
|
T11 |
99 |
|
T18 |
5 |
| auto[1] |
auto[1] |
auto[0] |
1053276 |
1 |
|
|
T1 |
249 |
|
T11 |
891 |
|
T18 |
49 |
| auto[1] |
auto[1] |
auto[1] |
152101 |
1 |
|
|
T1 |
3 |
|
T11 |
80 |
|
T18 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |