Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4609485 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
837 |
| auto[1] |
2423261 |
1 |
|
|
T1 |
1147 |
|
T11 |
3008 |
|
T18 |
99 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6727341 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1954 |
| auto[1] |
305405 |
1 |
|
|
T1 |
30 |
|
T11 |
211 |
|
T18 |
6 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4607253 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1097 |
| auto[1] |
2425493 |
1 |
|
|
T1 |
887 |
|
T11 |
2175 |
|
T18 |
80 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1059702 |
1 |
|
|
T1 |
350 |
|
T11 |
985 |
|
T18 |
34 |
| auto[1] |
auto[0] |
auto[1] |
152597 |
1 |
|
|
T1 |
14 |
|
T11 |
98 |
|
T18 |
5 |
| auto[1] |
auto[1] |
auto[0] |
1060386 |
1 |
|
|
T1 |
507 |
|
T11 |
979 |
|
T18 |
40 |
| auto[1] |
auto[1] |
auto[1] |
152808 |
1 |
|
|
T1 |
16 |
|
T11 |
113 |
|
T18 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |