Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4622332 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
913 |
| auto[1] |
2410414 |
1 |
|
|
T1 |
1071 |
|
T11 |
2512 |
|
T18 |
114 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6732660 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1957 |
| auto[1] |
300086 |
1 |
|
|
T1 |
27 |
|
T11 |
236 |
|
T18 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4633497 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1200 |
| auto[1] |
2399249 |
1 |
|
|
T1 |
784 |
|
T11 |
2404 |
|
T18 |
60 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1061411 |
1 |
|
|
T1 |
325 |
|
T11 |
962 |
|
T18 |
36 |
| auto[1] |
auto[0] |
auto[1] |
152448 |
1 |
|
|
T1 |
11 |
|
T11 |
99 |
|
T18 |
1 |
| auto[1] |
auto[1] |
auto[0] |
1037752 |
1 |
|
|
T1 |
432 |
|
T11 |
1206 |
|
T18 |
20 |
| auto[1] |
auto[1] |
auto[1] |
147638 |
1 |
|
|
T1 |
16 |
|
T11 |
137 |
|
T18 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |