Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4599938 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
883 |
| auto[1] |
2432808 |
1 |
|
|
T1 |
1101 |
|
T11 |
3154 |
|
T18 |
105 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6729588 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1935 |
| auto[1] |
303158 |
1 |
|
|
T1 |
49 |
|
T11 |
252 |
|
T18 |
9 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4618131 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
885 |
| auto[1] |
2414615 |
1 |
|
|
T1 |
1099 |
|
T11 |
2529 |
|
T18 |
103 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1055757 |
1 |
|
|
T1 |
461 |
|
T11 |
1061 |
|
T18 |
70 |
| auto[1] |
auto[0] |
auto[1] |
151317 |
1 |
|
|
T1 |
14 |
|
T11 |
121 |
|
T18 |
6 |
| auto[1] |
auto[1] |
auto[0] |
1055700 |
1 |
|
|
T1 |
589 |
|
T11 |
1216 |
|
T18 |
24 |
| auto[1] |
auto[1] |
auto[1] |
151841 |
1 |
|
|
T1 |
35 |
|
T11 |
131 |
|
T18 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |