Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4614077 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
853 |
| auto[1] |
2418669 |
1 |
|
|
T1 |
1131 |
|
T11 |
1970 |
|
T18 |
128 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6728952 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1939 |
| auto[1] |
303794 |
1 |
|
|
T1 |
45 |
|
T11 |
231 |
|
T18 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4616322 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
855 |
| auto[1] |
2416424 |
1 |
|
|
T1 |
1129 |
|
T11 |
2293 |
|
T18 |
84 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1050195 |
1 |
|
|
T1 |
509 |
|
T11 |
1159 |
|
T18 |
46 |
| auto[1] |
auto[0] |
auto[1] |
150832 |
1 |
|
|
T1 |
21 |
|
T11 |
143 |
|
T18 |
4 |
| auto[1] |
auto[1] |
auto[0] |
1062435 |
1 |
|
|
T1 |
575 |
|
T11 |
903 |
|
T18 |
33 |
| auto[1] |
auto[1] |
auto[1] |
152962 |
1 |
|
|
T1 |
24 |
|
T11 |
88 |
|
T18 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |