Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4620158 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
973 |
| auto[1] |
2412588 |
1 |
|
|
T1 |
1011 |
|
T11 |
2965 |
|
T18 |
115 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6728874 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1958 |
| auto[1] |
303872 |
1 |
|
|
T1 |
26 |
|
T11 |
285 |
|
T18 |
10 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4610657 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
955 |
| auto[1] |
2422089 |
1 |
|
|
T1 |
1029 |
|
T11 |
2953 |
|
T18 |
114 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1062453 |
1 |
|
|
T1 |
525 |
|
T11 |
1128 |
|
T18 |
49 |
| auto[1] |
auto[0] |
auto[1] |
152321 |
1 |
|
|
T1 |
18 |
|
T11 |
112 |
|
T18 |
6 |
| auto[1] |
auto[1] |
auto[0] |
1055764 |
1 |
|
|
T1 |
478 |
|
T11 |
1540 |
|
T18 |
55 |
| auto[1] |
auto[1] |
auto[1] |
151551 |
1 |
|
|
T1 |
8 |
|
T11 |
173 |
|
T18 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |