Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4614982 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
990 |
| auto[1] |
2417764 |
1 |
|
|
T1 |
994 |
|
T11 |
2711 |
|
T18 |
106 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5847996 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1167 |
| auto[1] |
1184750 |
1 |
|
|
T1 |
817 |
|
T11 |
1052 |
|
T18 |
31 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4604501 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
932 |
| auto[1] |
2428245 |
1 |
|
|
T1 |
1052 |
|
T11 |
3064 |
|
T18 |
66 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
627067 |
1 |
|
|
T1 |
144 |
|
T11 |
814 |
|
T18 |
20 |
| auto[1] |
auto[0] |
auto[1] |
594774 |
1 |
|
|
T1 |
440 |
|
T11 |
504 |
|
T18 |
18 |
| auto[1] |
auto[1] |
auto[0] |
616428 |
1 |
|
|
T1 |
91 |
|
T11 |
1198 |
|
T18 |
15 |
| auto[1] |
auto[1] |
auto[1] |
589976 |
1 |
|
|
T1 |
377 |
|
T11 |
548 |
|
T18 |
13 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |