Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4617455 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
920 |
| auto[1] |
2415291 |
1 |
|
|
T1 |
1064 |
|
T11 |
2284 |
|
T18 |
139 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5854679 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1145 |
| auto[1] |
1178067 |
1 |
|
|
T1 |
839 |
|
T11 |
947 |
|
T18 |
56 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4610849 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
972 |
| auto[1] |
2421897 |
1 |
|
|
T1 |
1012 |
|
T11 |
2379 |
|
T18 |
86 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
617919 |
1 |
|
|
T1 |
74 |
|
T11 |
774 |
|
T18 |
10 |
| auto[1] |
auto[0] |
auto[1] |
587215 |
1 |
|
|
T1 |
382 |
|
T11 |
541 |
|
T18 |
36 |
| auto[1] |
auto[1] |
auto[0] |
625911 |
1 |
|
|
T1 |
99 |
|
T11 |
658 |
|
T18 |
20 |
| auto[1] |
auto[1] |
auto[1] |
590852 |
1 |
|
|
T1 |
457 |
|
T11 |
406 |
|
T18 |
20 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |