Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4612817 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
990 |
| auto[1] |
2419929 |
1 |
|
|
T1 |
994 |
|
T11 |
2908 |
|
T18 |
86 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5850321 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1262 |
| auto[1] |
1182425 |
1 |
|
|
T1 |
722 |
|
T11 |
1040 |
|
T18 |
54 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4599861 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1085 |
| auto[1] |
2432885 |
1 |
|
|
T1 |
899 |
|
T11 |
3004 |
|
T18 |
108 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
627902 |
1 |
|
|
T1 |
94 |
|
T11 |
810 |
|
T18 |
38 |
| auto[1] |
auto[0] |
auto[1] |
590583 |
1 |
|
|
T1 |
304 |
|
T11 |
434 |
|
T18 |
29 |
| auto[1] |
auto[1] |
auto[0] |
622558 |
1 |
|
|
T1 |
83 |
|
T11 |
1154 |
|
T18 |
16 |
| auto[1] |
auto[1] |
auto[1] |
591842 |
1 |
|
|
T1 |
418 |
|
T11 |
606 |
|
T18 |
25 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |