Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4622701 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1128 |
| auto[1] |
2410045 |
1 |
|
|
T1 |
856 |
|
T11 |
2954 |
|
T18 |
135 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5858765 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1183 |
| auto[1] |
1173981 |
1 |
|
|
T1 |
801 |
|
T11 |
967 |
|
T18 |
88 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4623166 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
945 |
| auto[1] |
2409580 |
1 |
|
|
T1 |
1039 |
|
T11 |
2600 |
|
T18 |
158 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
622332 |
1 |
|
|
T1 |
124 |
|
T11 |
845 |
|
T18 |
30 |
| auto[1] |
auto[0] |
auto[1] |
593399 |
1 |
|
|
T1 |
447 |
|
T11 |
500 |
|
T18 |
39 |
| auto[1] |
auto[1] |
auto[0] |
613267 |
1 |
|
|
T1 |
114 |
|
T11 |
788 |
|
T18 |
40 |
| auto[1] |
auto[1] |
auto[1] |
580582 |
1 |
|
|
T1 |
354 |
|
T11 |
467 |
|
T18 |
49 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |