Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4608297 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
859 |
| auto[1] |
2424449 |
1 |
|
|
T1 |
1125 |
|
T11 |
3253 |
|
T18 |
114 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6729604 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1945 |
| auto[1] |
303142 |
1 |
|
|
T1 |
39 |
|
T11 |
161 |
|
T18 |
15 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4615926 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
944 |
| auto[1] |
2416820 |
1 |
|
|
T1 |
1040 |
|
T11 |
1957 |
|
T18 |
158 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1054970 |
1 |
|
|
T1 |
441 |
|
T11 |
747 |
|
T18 |
82 |
| auto[1] |
auto[0] |
auto[1] |
151056 |
1 |
|
|
T1 |
16 |
|
T11 |
89 |
|
T18 |
7 |
| auto[1] |
auto[1] |
auto[0] |
1058708 |
1 |
|
|
T1 |
560 |
|
T11 |
1049 |
|
T18 |
61 |
| auto[1] |
auto[1] |
auto[1] |
152086 |
1 |
|
|
T1 |
23 |
|
T11 |
72 |
|
T18 |
8 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |