Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4600653 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
963 |
| auto[1] |
2432093 |
1 |
|
|
T1 |
1021 |
|
T11 |
2926 |
|
T18 |
91 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5861721 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1333 |
| auto[1] |
1171025 |
1 |
|
|
T1 |
651 |
|
T11 |
658 |
|
T18 |
65 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4623745 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1145 |
| auto[1] |
2409001 |
1 |
|
|
T1 |
839 |
|
T11 |
2012 |
|
T18 |
116 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
617001 |
1 |
|
|
T1 |
79 |
|
T11 |
742 |
|
T18 |
37 |
| auto[1] |
auto[0] |
auto[1] |
586032 |
1 |
|
|
T1 |
343 |
|
T11 |
391 |
|
T18 |
38 |
| auto[1] |
auto[1] |
auto[0] |
620975 |
1 |
|
|
T1 |
109 |
|
T11 |
612 |
|
T18 |
14 |
| auto[1] |
auto[1] |
auto[1] |
584993 |
1 |
|
|
T1 |
308 |
|
T11 |
267 |
|
T18 |
27 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |