Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4617298 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1031 |
| auto[1] |
2415448 |
1 |
|
|
T1 |
953 |
|
T11 |
3126 |
|
T18 |
69 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5860453 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1197 |
| auto[1] |
1172293 |
1 |
|
|
T1 |
787 |
|
T11 |
848 |
|
T18 |
60 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4628181 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
992 |
| auto[1] |
2404565 |
1 |
|
|
T1 |
992 |
|
T11 |
2344 |
|
T18 |
121 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
617037 |
1 |
|
|
T1 |
132 |
|
T11 |
667 |
|
T18 |
39 |
| auto[1] |
auto[0] |
auto[1] |
585943 |
1 |
|
|
T1 |
388 |
|
T11 |
322 |
|
T18 |
45 |
| auto[1] |
auto[1] |
auto[0] |
615235 |
1 |
|
|
T1 |
73 |
|
T11 |
829 |
|
T18 |
22 |
| auto[1] |
auto[1] |
auto[1] |
586350 |
1 |
|
|
T1 |
399 |
|
T11 |
526 |
|
T18 |
15 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |