Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4603851 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
960 |
| auto[1] |
2428895 |
1 |
|
|
T1 |
1024 |
|
T11 |
2923 |
|
T18 |
145 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5855566 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1140 |
| auto[1] |
1177180 |
1 |
|
|
T1 |
844 |
|
T11 |
935 |
|
T18 |
34 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4611275 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
935 |
| auto[1] |
2421471 |
1 |
|
|
T1 |
1049 |
|
T11 |
2832 |
|
T18 |
111 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
620524 |
1 |
|
|
T1 |
99 |
|
T11 |
678 |
|
T18 |
29 |
| auto[1] |
auto[0] |
auto[1] |
588454 |
1 |
|
|
T1 |
378 |
|
T11 |
412 |
|
T18 |
11 |
| auto[1] |
auto[1] |
auto[0] |
623767 |
1 |
|
|
T1 |
106 |
|
T11 |
1219 |
|
T18 |
48 |
| auto[1] |
auto[1] |
auto[1] |
588726 |
1 |
|
|
T1 |
466 |
|
T11 |
523 |
|
T18 |
23 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |