Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4593353 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
933 |
| auto[1] |
2439393 |
1 |
|
|
T1 |
1051 |
|
T11 |
2796 |
|
T18 |
91 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5857535 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1114 |
| auto[1] |
1175211 |
1 |
|
|
T1 |
870 |
|
T11 |
999 |
|
T18 |
41 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4627593 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
906 |
| auto[1] |
2405153 |
1 |
|
|
T1 |
1078 |
|
T11 |
2724 |
|
T18 |
93 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
607722 |
1 |
|
|
T1 |
105 |
|
T11 |
827 |
|
T18 |
31 |
| auto[1] |
auto[0] |
auto[1] |
582151 |
1 |
|
|
T1 |
465 |
|
T11 |
566 |
|
T18 |
15 |
| auto[1] |
auto[1] |
auto[0] |
622220 |
1 |
|
|
T1 |
103 |
|
T11 |
898 |
|
T18 |
21 |
| auto[1] |
auto[1] |
auto[1] |
593060 |
1 |
|
|
T1 |
405 |
|
T11 |
433 |
|
T18 |
26 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |