Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4618874 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1003 |
| auto[1] |
2413872 |
1 |
|
|
T1 |
981 |
|
T11 |
1979 |
|
T18 |
126 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5863396 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1191 |
| auto[1] |
1169350 |
1 |
|
|
T1 |
793 |
|
T11 |
824 |
|
T18 |
71 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4631100 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
988 |
| auto[1] |
2401646 |
1 |
|
|
T1 |
996 |
|
T11 |
2399 |
|
T18 |
158 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
623278 |
1 |
|
|
T1 |
97 |
|
T11 |
799 |
|
T18 |
41 |
| auto[1] |
auto[0] |
auto[1] |
584235 |
1 |
|
|
T1 |
386 |
|
T11 |
468 |
|
T18 |
29 |
| auto[1] |
auto[1] |
auto[0] |
609018 |
1 |
|
|
T1 |
106 |
|
T11 |
776 |
|
T18 |
46 |
| auto[1] |
auto[1] |
auto[1] |
585115 |
1 |
|
|
T1 |
407 |
|
T11 |
356 |
|
T18 |
42 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |