Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4611293 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1108 |
| auto[1] |
2421453 |
1 |
|
|
T1 |
876 |
|
T11 |
2212 |
|
T18 |
143 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6729648 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1943 |
| auto[1] |
303098 |
1 |
|
|
T1 |
41 |
|
T11 |
237 |
|
T18 |
7 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4617144 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1035 |
| auto[1] |
2415602 |
1 |
|
|
T1 |
949 |
|
T11 |
2334 |
|
T18 |
125 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1056517 |
1 |
|
|
T1 |
518 |
|
T11 |
1101 |
|
T18 |
45 |
| auto[1] |
auto[0] |
auto[1] |
151256 |
1 |
|
|
T1 |
22 |
|
T11 |
124 |
|
T18 |
4 |
| auto[1] |
auto[1] |
auto[0] |
1055987 |
1 |
|
|
T1 |
390 |
|
T11 |
996 |
|
T18 |
73 |
| auto[1] |
auto[1] |
auto[1] |
151842 |
1 |
|
|
T1 |
19 |
|
T11 |
113 |
|
T18 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |