Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4613201 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1103 |
| auto[1] |
2419545 |
1 |
|
|
T1 |
881 |
|
T11 |
3037 |
|
T18 |
88 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5860523 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1234 |
| auto[1] |
1172223 |
1 |
|
|
T1 |
750 |
|
T11 |
852 |
|
T18 |
47 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4620904 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
942 |
| auto[1] |
2411842 |
1 |
|
|
T1 |
1042 |
|
T11 |
2047 |
|
T18 |
82 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
623740 |
1 |
|
|
T1 |
157 |
|
T11 |
548 |
|
T18 |
18 |
| auto[1] |
auto[0] |
auto[1] |
590082 |
1 |
|
|
T1 |
436 |
|
T11 |
450 |
|
T18 |
26 |
| auto[1] |
auto[1] |
auto[0] |
615879 |
1 |
|
|
T1 |
135 |
|
T11 |
647 |
|
T18 |
17 |
| auto[1] |
auto[1] |
auto[1] |
582141 |
1 |
|
|
T1 |
314 |
|
T11 |
402 |
|
T18 |
21 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |