Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4616934 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1102 |
| auto[1] |
2415812 |
1 |
|
|
T1 |
882 |
|
T11 |
2198 |
|
T18 |
121 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6727129 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1941 |
| auto[1] |
305617 |
1 |
|
|
T1 |
43 |
|
T11 |
310 |
|
T18 |
9 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4595680 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
963 |
| auto[1] |
2437066 |
1 |
|
|
T1 |
1021 |
|
T11 |
2917 |
|
T18 |
129 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1067958 |
1 |
|
|
T1 |
566 |
|
T11 |
1605 |
|
T18 |
55 |
| auto[1] |
auto[0] |
auto[1] |
152910 |
1 |
|
|
T1 |
20 |
|
T11 |
181 |
|
T18 |
5 |
| auto[1] |
auto[1] |
auto[0] |
1063491 |
1 |
|
|
T1 |
412 |
|
T11 |
1002 |
|
T18 |
65 |
| auto[1] |
auto[1] |
auto[1] |
152707 |
1 |
|
|
T1 |
23 |
|
T11 |
129 |
|
T18 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |