Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4608593 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1142 |
| auto[1] |
2424153 |
1 |
|
|
T1 |
842 |
|
T11 |
3063 |
|
T18 |
104 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6732796 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1948 |
| auto[1] |
299950 |
1 |
|
|
T1 |
36 |
|
T11 |
193 |
|
T18 |
7 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4638175 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
978 |
| auto[1] |
2394571 |
1 |
|
|
T1 |
1006 |
|
T11 |
2105 |
|
T18 |
97 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1050596 |
1 |
|
|
T1 |
562 |
|
T11 |
961 |
|
T18 |
64 |
| auto[1] |
auto[0] |
auto[1] |
150171 |
1 |
|
|
T1 |
21 |
|
T11 |
108 |
|
T18 |
4 |
| auto[1] |
auto[1] |
auto[0] |
1044025 |
1 |
|
|
T1 |
408 |
|
T11 |
951 |
|
T18 |
26 |
| auto[1] |
auto[1] |
auto[1] |
149779 |
1 |
|
|
T1 |
15 |
|
T11 |
85 |
|
T18 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |