Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4601529 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
813 |
| auto[1] |
2431217 |
1 |
|
|
T1 |
1171 |
|
T11 |
2468 |
|
T18 |
79 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6727193 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1943 |
| auto[1] |
305553 |
1 |
|
|
T1 |
41 |
|
T11 |
196 |
|
T18 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4609441 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1004 |
| auto[1] |
2423305 |
1 |
|
|
T1 |
980 |
|
T11 |
2047 |
|
T18 |
78 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1063429 |
1 |
|
|
T1 |
434 |
|
T11 |
1076 |
|
T18 |
60 |
| auto[1] |
auto[0] |
auto[1] |
154136 |
1 |
|
|
T1 |
20 |
|
T11 |
98 |
|
T18 |
4 |
| auto[1] |
auto[1] |
auto[0] |
1054323 |
1 |
|
|
T1 |
505 |
|
T11 |
775 |
|
T18 |
14 |
| auto[1] |
auto[1] |
auto[1] |
151417 |
1 |
|
|
T1 |
21 |
|
T11 |
98 |
|
T26 |
3475 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |