Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4619973 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1146 |
| auto[1] |
2412773 |
1 |
|
|
T1 |
838 |
|
T11 |
2538 |
|
T18 |
82 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6728582 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1947 |
| auto[1] |
304164 |
1 |
|
|
T1 |
37 |
|
T11 |
230 |
|
T18 |
10 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4604576 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
838 |
| auto[1] |
2428170 |
1 |
|
|
T1 |
1146 |
|
T11 |
2377 |
|
T18 |
126 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1070091 |
1 |
|
|
T1 |
661 |
|
T11 |
1006 |
|
T18 |
78 |
| auto[1] |
auto[0] |
auto[1] |
152738 |
1 |
|
|
T1 |
20 |
|
T11 |
104 |
|
T18 |
6 |
| auto[1] |
auto[1] |
auto[0] |
1053915 |
1 |
|
|
T1 |
448 |
|
T11 |
1141 |
|
T18 |
38 |
| auto[1] |
auto[1] |
auto[1] |
151426 |
1 |
|
|
T1 |
17 |
|
T11 |
126 |
|
T18 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |